2 * DTS file for CSR SiRFatlas7 SoC
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 /include/ "skeleton.dtsi"
11 compatible = "sirf,atlas7";
14 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
36 compatible = "arm,cortex-a7";
43 compatible = "fixed-clock";
45 clock-frequency = <32768>;
46 clock-output-names = "xinw";
49 compatible = "fixed-clock";
51 clock-frequency = <26000000>;
52 clock-output-names = "xin";
57 compatible = "simple-bus";
60 ranges = <0x10000000 0x10000000 0xc0000000>;
62 gic: interrupt-controller@10301000 {
63 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 reg = <0x10301000 0x1000>,
70 pmu_regulator: pmu_regulator@10E30020 {
71 compatible = "sirf,atlas7-pmu-ldo";
72 reg = <0x10E30020 0x4>;
74 regulator-name = "ldo";
78 atlas7_codec: atlas7_codec@10E30000 {
79 #sound-dai-cells = <0>;
80 compatible = "sirf,atlas7-codec";
81 reg = <0x10E30000 0x400>;
86 atlas7_iacc: atlas7_iacc@10D01000 {
87 #sound-dai-cells = <0>;
88 compatible = "sirf,atlas7-iacc";
89 reg = <0x10D01000 0x100>;
90 dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
91 <&dmac3 3>, <&dmac3 9>;
92 dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
97 compatible = "sirf,atlas7-ipc";
98 ranges = <0x13240000 0x13240000 0x00010000>;
103 compatible = "sirf,hwspinlock";
104 reg = <0x13240000 0x00010000>;
106 num-spinlocks = <30>;
110 compatible = "sirf,ns2m30-rproc";
111 reg = <0x13240000 0x00010000>;
112 interrupts = <0 123 0>;
116 compatible = "sirf,ns2m31-rproc";
117 reg = <0x13240000 0x00010000>;
118 interrupts = <0 126 0>;
122 compatible = "sirf,ns2kal0-rproc";
123 reg = <0x13240000 0x00010000>;
124 interrupts = <0 124 0>;
128 compatible = "sirf,ns2kal1-rproc";
129 reg = <0x13240000 0x00010000>;
130 interrupts = <0 127 0>;
134 pinctrl: ioc@18880000 {
135 compatible = "sirf,atlas7-ioc";
136 reg = <0x18880000 0x1000>,
139 audio_ac97_pmx: audio_ac97@0 {
141 groups = "audio_ac97_grp";
142 function = "audio_ac97";
146 audio_func_dbg_pmx: audio_func_dbg@0 {
148 groups = "audio_func_dbg_grp";
149 function = "audio_func_dbg";
153 audio_i2s_pmx: audio_i2s@0 {
155 groups = "audio_i2s_grp";
156 function = "audio_i2s";
160 audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
162 groups = "audio_i2s_2ch_grp";
163 function = "audio_i2s_2ch";
167 audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
169 groups = "audio_i2s_extclk_grp";
170 function = "audio_i2s_extclk";
174 audio_uart0_pmx: audio_uart0@0 {
176 groups = "audio_uart0_grp";
177 function = "audio_uart0";
181 audio_uart1_pmx: audio_uart1@0 {
183 groups = "audio_uart1_grp";
184 function = "audio_uart1";
188 audio_uart2_pmx0: audio_uart2@0 {
190 groups = "audio_uart2_grp0";
191 function = "audio_uart2_m0";
195 audio_uart2_pmx1: audio_uart2@1 {
197 groups = "audio_uart2_grp1";
198 function = "audio_uart2_m1";
202 c_can_trnsvr_pmx: c_can_trnsvr@0 {
204 groups = "c_can_trnsvr_grp";
205 function = "c_can_trnsvr";
209 c0_can_pmx0: c0_can@0 {
211 groups = "c0_can_grp0";
212 function = "c0_can_m0";
216 c0_can_pmx1: c0_can@1 {
218 groups = "c0_can_grp1";
219 function = "c0_can_m1";
223 c1_can_pmx0: c1_can@0 {
225 groups = "c1_can_grp0";
226 function = "c1_can_m0";
230 c1_can_pmx1: c1_can@1 {
232 groups = "c1_can_grp1";
233 function = "c1_can_m1";
237 c1_can_pmx2: c1_can@2 {
239 groups = "c1_can_grp2";
240 function = "c1_can_m2";
244 ca_audio_lpc_pmx: ca_audio_lpc@0 {
246 groups = "ca_audio_lpc_grp";
247 function = "ca_audio_lpc";
251 ca_bt_lpc_pmx: ca_bt_lpc@0 {
253 groups = "ca_bt_lpc_grp";
254 function = "ca_bt_lpc";
258 ca_coex_pmx: ca_coex@0 {
260 groups = "ca_coex_grp";
261 function = "ca_coex";
265 ca_curator_lpc_pmx: ca_curator_lpc@0 {
267 groups = "ca_curator_lpc_grp";
268 function = "ca_curator_lpc";
272 ca_pcm_debug_pmx: ca_pcm_debug@0 {
274 groups = "ca_pcm_debug_grp";
275 function = "ca_pcm_debug";
279 ca_pio_pmx: ca_pio@0 {
281 groups = "ca_pio_grp";
286 ca_sdio_debug_pmx: ca_sdio_debug@0 {
288 groups = "ca_sdio_debug_grp";
289 function = "ca_sdio_debug";
293 ca_spi_pmx: ca_spi@0 {
295 groups = "ca_spi_grp";
300 ca_trb_pmx: ca_trb@0 {
302 groups = "ca_trb_grp";
307 ca_uart_debug_pmx: ca_uart_debug@0 {
309 groups = "ca_uart_debug_grp";
310 function = "ca_uart_debug";
316 groups = "clkc_grp0";
317 function = "clkc_m0";
323 groups = "clkc_grp1";
324 function = "clkc_m1";
328 gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
330 groups = "gn_gnss_i2c_grp";
331 function = "gn_gnss_i2c";
335 gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
336 gn_gnss_uart_nopause {
337 groups = "gn_gnss_uart_nopause_grp";
338 function = "gn_gnss_uart_nopause";
342 gn_gnss_uart_pmx: gn_gnss_uart@0 {
344 groups = "gn_gnss_uart_grp";
345 function = "gn_gnss_uart";
349 gn_trg_spi_pmx0: gn_trg_spi@0 {
351 groups = "gn_trg_spi_grp0";
352 function = "gn_trg_spi_m0";
356 gn_trg_spi_pmx1: gn_trg_spi@1 {
358 groups = "gn_trg_spi_grp1";
359 function = "gn_trg_spi_m1";
363 cvbs_dbg_pmx: cvbs_dbg@0 {
365 groups = "cvbs_dbg_grp";
366 function = "cvbs_dbg";
370 cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
372 groups = "cvbs_dbg_test_grp0";
373 function = "cvbs_dbg_test_m0";
377 cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
379 groups = "cvbs_dbg_test_grp1";
380 function = "cvbs_dbg_test_m1";
384 cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
386 groups = "cvbs_dbg_test_grp2";
387 function = "cvbs_dbg_test_m2";
391 cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
393 groups = "cvbs_dbg_test_grp3";
394 function = "cvbs_dbg_test_m3";
398 cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
400 groups = "cvbs_dbg_test_grp4";
401 function = "cvbs_dbg_test_m4";
405 cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
407 groups = "cvbs_dbg_test_grp5";
408 function = "cvbs_dbg_test_m5";
412 cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
414 groups = "cvbs_dbg_test_grp6";
415 function = "cvbs_dbg_test_m6";
419 cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
421 groups = "cvbs_dbg_test_grp7";
422 function = "cvbs_dbg_test_m7";
426 cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
428 groups = "cvbs_dbg_test_grp8";
429 function = "cvbs_dbg_test_m8";
433 cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
435 groups = "cvbs_dbg_test_grp9";
436 function = "cvbs_dbg_test_m9";
440 cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
442 groups = "cvbs_dbg_test_grp10";
443 function = "cvbs_dbg_test_m10";
447 cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
449 groups = "cvbs_dbg_test_grp11";
450 function = "cvbs_dbg_test_m11";
454 cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
456 groups = "cvbs_dbg_test_grp12";
457 function = "cvbs_dbg_test_m12";
461 cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
463 groups = "cvbs_dbg_test_grp13";
464 function = "cvbs_dbg_test_m13";
468 cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
470 groups = "cvbs_dbg_test_grp14";
471 function = "cvbs_dbg_test_m14";
475 cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
477 groups = "cvbs_dbg_test_grp15";
478 function = "cvbs_dbg_test_m15";
482 gn_gnss_power_pmx: gn_gnss_power@0 {
484 groups = "gn_gnss_power_grp";
485 function = "gn_gnss_power";
489 gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
491 groups = "gn_gnss_sw_status_grp";
492 function = "gn_gnss_sw_status";
496 gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
498 groups = "gn_gnss_eclk_grp";
499 function = "gn_gnss_eclk";
503 gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
505 groups = "gn_gnss_irq1_grp0";
506 function = "gn_gnss_irq1_m0";
510 gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
512 groups = "gn_gnss_irq2_grp0";
513 function = "gn_gnss_irq2_m0";
517 gn_gnss_tm_pmx: gn_gnss_tm@0 {
519 groups = "gn_gnss_tm_grp";
520 function = "gn_gnss_tm";
524 gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
526 groups = "gn_gnss_tsync_grp";
527 function = "gn_gnss_tsync";
531 gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
532 gn_io_gnsssys_sw_cfg {
533 groups = "gn_io_gnsssys_sw_cfg_grp";
534 function = "gn_io_gnsssys_sw_cfg";
538 gn_trg_pmx0: gn_trg@0 {
540 groups = "gn_trg_grp0";
541 function = "gn_trg_m0";
545 gn_trg_pmx1: gn_trg@1 {
547 groups = "gn_trg_grp1";
548 function = "gn_trg_m1";
552 gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
554 groups = "gn_trg_shutdown_grp0";
555 function = "gn_trg_shutdown_m0";
559 gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
561 groups = "gn_trg_shutdown_grp1";
562 function = "gn_trg_shutdown_m1";
566 gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
568 groups = "gn_trg_shutdown_grp2";
569 function = "gn_trg_shutdown_m2";
573 gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
575 groups = "gn_trg_shutdown_grp3";
576 function = "gn_trg_shutdown_m3";
596 groups = "jtag_grp0";
597 function = "jtag_m0";
601 ks_kas_spi_pmx0: ks_kas_spi@0 {
603 groups = "ks_kas_spi_grp0";
604 function = "ks_kas_spi_m0";
608 ld_ldd_pmx: ld_ldd@0 {
610 groups = "ld_ldd_grp";
615 ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
617 groups = "ld_ldd_16bit_grp";
618 function = "ld_ldd_16bit";
622 ld_ldd_fck_pmx: ld_ldd_fck@0 {
624 groups = "ld_ldd_fck_grp";
625 function = "ld_ldd_fck";
629 ld_ldd_lck_pmx: ld_ldd_lck@0 {
631 groups = "ld_ldd_lck_grp";
632 function = "ld_ldd_lck";
636 lr_lcdrom_pmx: lr_lcdrom@0 {
638 groups = "lr_lcdrom_grp";
639 function = "lr_lcdrom";
643 lvds_analog_pmx: lvds_analog@0 {
645 groups = "lvds_analog_grp";
646 function = "lvds_analog";
652 groups = "nd_df_grp";
657 nd_df_nowp_pmx: nd_df_nowp@0 {
659 groups = "nd_df_nowp_grp";
660 function = "nd_df_nowp";
671 pwc_core_on_pmx: pwc_core_on@0 {
673 groups = "pwc_core_on_grp";
674 function = "pwc_core_on";
678 pwc_ext_on_pmx: pwc_ext_on@0 {
680 groups = "pwc_ext_on_grp";
681 function = "pwc_ext_on";
685 pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
687 groups = "pwc_gpio3_clk_grp";
688 function = "pwc_gpio3_clk";
692 pwc_io_on_pmx: pwc_io_on@0 {
694 groups = "pwc_io_on_grp";
695 function = "pwc_io_on";
699 pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
701 groups = "pwc_lowbatt_b_grp0";
702 function = "pwc_lowbatt_b_m0";
706 pwc_mem_on_pmx: pwc_mem_on@0 {
708 groups = "pwc_mem_on_grp";
709 function = "pwc_mem_on";
713 pwc_on_key_b_pmx0: pwc_on_key_b@0 {
715 groups = "pwc_on_key_b_grp0";
716 function = "pwc_on_key_b_m0";
720 pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
722 groups = "pwc_wakeup_src0_grp";
723 function = "pwc_wakeup_src0";
727 pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
729 groups = "pwc_wakeup_src1_grp";
730 function = "pwc_wakeup_src1";
734 pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
736 groups = "pwc_wakeup_src2_grp";
737 function = "pwc_wakeup_src2";
741 pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
743 groups = "pwc_wakeup_src3_grp";
744 function = "pwc_wakeup_src3";
748 pw_cko0_pmx0: pw_cko0@0 {
750 groups = "pw_cko0_grp0";
751 function = "pw_cko0_m0";
755 pw_cko0_pmx1: pw_cko0@1 {
757 groups = "pw_cko0_grp1";
758 function = "pw_cko0_m1";
762 pw_cko0_pmx2: pw_cko0@2 {
764 groups = "pw_cko0_grp2";
765 function = "pw_cko0_m2";
769 pw_cko1_pmx0: pw_cko1@0 {
771 groups = "pw_cko1_grp0";
772 function = "pw_cko1_m0";
776 pw_cko1_pmx1: pw_cko1@1 {
778 groups = "pw_cko1_grp1";
779 function = "pw_cko1_m1";
783 pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
785 groups = "pw_i2s01_clk_grp0";
786 function = "pw_i2s01_clk_m0";
790 pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
792 groups = "pw_i2s01_clk_grp1";
793 function = "pw_i2s01_clk_m1";
797 pw_pwm0_pmx: pw_pwm0@0 {
799 groups = "pw_pwm0_grp";
800 function = "pw_pwm0";
804 pw_pwm1_pmx: pw_pwm1@0 {
806 groups = "pw_pwm1_grp";
807 function = "pw_pwm1";
811 pw_pwm2_pmx0: pw_pwm2@0 {
813 groups = "pw_pwm2_grp0";
814 function = "pw_pwm2_m0";
818 pw_pwm2_pmx1: pw_pwm2@1 {
820 groups = "pw_pwm2_grp1";
821 function = "pw_pwm2_m1";
825 pw_pwm3_pmx0: pw_pwm3@0 {
827 groups = "pw_pwm3_grp0";
828 function = "pw_pwm3_m0";
832 pw_pwm3_pmx1: pw_pwm3@1 {
834 groups = "pw_pwm3_grp1";
835 function = "pw_pwm3_m1";
839 pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
841 groups = "pw_pwm_cpu_vol_grp0";
842 function = "pw_pwm_cpu_vol_m0";
846 pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
848 groups = "pw_pwm_cpu_vol_grp1";
849 function = "pw_pwm_cpu_vol_m1";
853 pw_backlight_pmx0: pw_backlight@0 {
855 groups = "pw_backlight_grp0";
856 function = "pw_backlight_m0";
860 pw_backlight_pmx1: pw_backlight@1 {
862 groups = "pw_backlight_grp1";
863 function = "pw_backlight_m1";
867 rg_eth_mac_pmx: rg_eth_mac@0 {
869 groups = "rg_eth_mac_grp";
870 function = "rg_eth_mac";
874 rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
876 groups = "rg_gmac_phy_intr_n_grp";
877 function = "rg_gmac_phy_intr_n";
881 rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
883 groups = "rg_rgmii_mac_grp";
884 function = "rg_rgmii_mac";
888 rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
889 rg_rgmii_phy_ref_clk_0 {
891 "rg_rgmii_phy_ref_clk_grp0";
893 "rg_rgmii_phy_ref_clk_m0";
897 rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
898 rg_rgmii_phy_ref_clk_1 {
900 "rg_rgmii_phy_ref_clk_grp1";
902 "rg_rgmii_phy_ref_clk_m1";
913 sd0_4bit_pmx: sd0_4bit@0 {
915 groups = "sd0_4bit_grp";
916 function = "sd0_4bit";
927 sd1_4bit_pmx0: sd1_4bit@0 {
929 groups = "sd1_4bit_grp0";
930 function = "sd1_4bit_m0";
934 sd1_4bit_pmx1: sd1_4bit@1 {
936 groups = "sd1_4bit_grp1";
937 function = "sd1_4bit_m1";
948 sd2_no_cdb_pmx0: sd2_no_cdb@0 {
950 groups = "sd2_no_cdb_grp0";
951 function = "sd2_no_cdb_m0";
983 sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
985 groups = "sp0_ext_ldo_on_grp";
986 function = "sp0_ext_ldo_on";
990 sp0_qspi_pmx: sp0_qspi@0 {
992 groups = "sp0_qspi_grp";
993 function = "sp0_qspi";
997 sp1_spi_pmx: sp1_spi@0 {
999 groups = "sp1_spi_grp";
1000 function = "sp1_spi";
1004 tpiu_trace_pmx: tpiu_trace@0 {
1006 groups = "tpiu_trace_grp";
1007 function = "tpiu_trace";
1011 uart0_pmx: uart0@0 {
1013 groups = "uart0_grp";
1018 uart0_nopause_pmx: uart0_nopause@0 {
1020 groups = "uart0_nopause_grp";
1021 function = "uart0_nopause";
1025 uart1_pmx: uart1@0 {
1027 groups = "uart1_grp";
1032 uart2_pmx: uart2@0 {
1034 groups = "uart2_grp";
1039 uart3_pmx0: uart3@0 {
1041 groups = "uart3_grp0";
1042 function = "uart3_m0";
1046 uart3_pmx1: uart3@1 {
1048 groups = "uart3_grp1";
1049 function = "uart3_m1";
1053 uart3_pmx2: uart3@2 {
1055 groups = "uart3_grp2";
1056 function = "uart3_m2";
1060 uart3_pmx3: uart3@3 {
1062 groups = "uart3_grp3";
1063 function = "uart3_m3";
1067 uart3_nopause_pmx0: uart3_nopause@0 {
1069 groups = "uart3_nopause_grp0";
1070 function = "uart3_nopause_m0";
1074 uart3_nopause_pmx1: uart3_nopause@1 {
1076 groups = "uart3_nopause_grp1";
1077 function = "uart3_nopause_m1";
1081 uart4_pmx0: uart4@0 {
1083 groups = "uart4_grp0";
1084 function = "uart4_m0";
1088 uart4_pmx1: uart4@1 {
1090 groups = "uart4_grp1";
1091 function = "uart4_m1";
1095 uart4_pmx2: uart4@2 {
1097 groups = "uart4_grp2";
1098 function = "uart4_m2";
1102 uart4_nopause_pmx: uart4_nopause@0 {
1104 groups = "uart4_nopause_grp";
1105 function = "uart4_nopause";
1109 usb0_drvvbus_pmx: usb0_drvvbus@0 {
1111 groups = "usb0_drvvbus_grp";
1112 function = "usb0_drvvbus";
1116 usb1_drvvbus_pmx: usb1_drvvbus@0 {
1118 groups = "usb1_drvvbus_grp";
1119 function = "usb1_drvvbus";
1123 visbus_dout_pmx: visbus_dout@0 {
1125 groups = "visbus_dout_grp";
1126 function = "visbus_dout";
1130 vi_vip1_pmx: vi_vip1@0 {
1132 groups = "vi_vip1_grp";
1133 function = "vi_vip1";
1137 vi_vip1_ext_pmx: vi_vip1_ext@0 {
1139 groups = "vi_vip1_ext_grp";
1140 function = "vi_vip1_ext";
1144 vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1146 groups = "vi_vip1_low8bit_grp";
1147 function = "vi_vip1_low8bit";
1151 vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1153 groups = "vi_vip1_high8bit_grp";
1154 function = "vi_vip1_high8bit";
1160 compatible = "arteris, flexnoc", "simple-bus";
1161 #address-cells = <1>;
1163 ranges = <0x13240000 0x13240000 0x00010000>;
1165 compatible = "sirf,atlas7-pmipc";
1166 reg = <0x13240000 0x00010000>;
1171 compatible = "arteris, flexnoc", "simple-bus";
1172 #address-cells = <1>;
1174 ranges = <0x10830000 0x10830000 0x18000>;
1176 compatible = "sirf,nocfw-dramfw";
1177 reg = <0x10830000 0x18000>;
1182 compatible = "arteris, flexnoc", "simple-bus";
1183 #address-cells = <1>;
1185 ranges = <0x10250000 0x10250000 0x3000>;
1187 compatible = "sirf,nocfw-spramfw";
1188 reg = <0x10250000 0x3000>;
1193 compatible = "arteris, flexnoc", "simple-bus";
1194 #address-cells = <1>;
1196 ranges = <0x10200000 0x10200000 0x3000>;
1198 compatible = "sirf,nocfw-cpum";
1199 reg = <0x10200000 0x3000>;
1204 compatible = "arteris, flexnoc", "simple-bus";
1205 #address-cells = <1>;
1207 ranges = <0x18641000 0x18641000 0x3000>,
1208 <0x18620000 0x18620000 0x1000>;
1211 compatible = "sirf,nocfw-cgum";
1212 reg = <0x18641000 0x3000>;
1215 car: clock-controller@18620000 {
1216 compatible = "sirf,atlas7-car";
1217 reg = <0x18620000 0x1000>;
1224 compatible = "arteris, flexnoc", "simple-bus";
1225 #address-cells = <1>;
1227 ranges = <0x18000000 0x18000000 0x0000ffff>,
1228 <0x18010000 0x18010000 0x1000>,
1229 <0x18020000 0x18020000 0x1000>,
1230 <0x18030000 0x18030000 0x1000>,
1231 <0x18040000 0x18040000 0x1000>,
1232 <0x18050000 0x18050000 0x1000>,
1233 <0x18060000 0x18060000 0x1000>,
1234 <0x18100000 0x18100000 0x3000>,
1235 <0x18250000 0x18250000 0x10000>,
1236 <0x18200000 0x18200000 0x1000>;
1238 dmac0: dma-controller@18000000 {
1240 compatible = "sirf,atlas7-dmac";
1241 reg = <0x18000000 0x1000>;
1242 interrupts = <0 12 0>;
1244 dma-channels = <16>;
1248 gnssmfw@0x18100000 {
1249 compatible = "sirf,nocfw-gnssm";
1250 reg = <0x18100000 0x3000>;
1253 uart0: uart@18010000 {
1255 compatible = "sirf,atlas7-uart";
1256 reg = <0x18010000 0x1000>;
1257 interrupts = <0 17 0>;
1260 dmas = <&dmac0 3>, <&dmac0 2>;
1261 dma-names = "rx", "tx";
1264 uart1: uart@18020000 {
1266 compatible = "sirf,atlas7-uart";
1267 reg = <0x18020000 0x1000>;
1268 interrupts = <0 18 0>;
1273 uart2: uart@18030000 {
1275 compatible = "sirf,atlas7-uart";
1276 reg = <0x18030000 0x1000>;
1277 interrupts = <0 19 0>;
1280 dmas = <&dmac0 6>, <&dmac0 7>;
1281 dma-names = "rx", "tx";
1282 status = "disabled";
1284 uart3: uart@18040000 {
1286 compatible = "sirf,atlas7-uart";
1287 reg = <0x18040000 0x1000>;
1288 interrupts = <0 66 0>;
1291 dmas = <&dmac0 4>, <&dmac0 5>;
1292 dma-names = "rx", "tx";
1293 status = "disabled";
1295 uart4: uart@18050000 {
1297 compatible = "sirf,atlas7-uart";
1298 reg = <0x18050000 0x1000>;
1299 interrupts = <0 69 0>;
1302 dmas = <&dmac0 0>, <&dmac0 1>;
1303 dma-names = "rx", "tx";
1304 status = "disabled";
1306 uart5: uart@18060000 {
1308 compatible = "sirf,atlas7-uart";
1309 reg = <0x18060000 0x1000>;
1310 interrupts = <0 71 0>;
1313 dmas = <&dmac0 8>, <&dmac0 9>;
1314 dma-names = "rx", "tx";
1315 status = "disabled";
1318 compatible = "dx,cc44p";
1319 reg = <0x18250000 0x10000>;
1320 interrupts = <0 27 0>;
1323 spi1: spi@18200000 {
1324 compatible = "sirf,prima2-spi";
1325 reg = <0x18200000 0x1000>;
1326 interrupts = <0 16 0>;
1328 #address-cells = <1>;
1330 dmas = <&dmac0 12>, <&dmac0 13>;
1331 dma-names = "rx", "tx";
1332 status = "disabled";
1338 compatible = "arteris, flexnoc", "simple-bus";
1339 #address-cells = <1>;
1341 ranges = <0x13000000 0x13000000 0x3000>;
1343 compatible = "sirf,nocfw-gpum";
1344 reg = <0x13000000 0x3000>;
1349 compatible = "arteris, flexnoc", "simple-bus";
1350 #address-cells = <1>;
1352 ranges = <0x16000000 0x16000000 0x00200000>,
1353 <0x17020000 0x17020000 0x1000>,
1354 <0x17030000 0x17030000 0x1000>,
1355 <0x17040000 0x17040000 0x1000>,
1356 <0x17050000 0x17050000 0x10000>,
1357 <0x17060000 0x17060000 0x200>,
1358 <0x17060200 0x17060200 0x100>,
1359 <0x17070000 0x17070000 0x200>,
1360 <0x17070200 0x17070200 0x100>,
1361 <0x170A0000 0x170A0000 0x3000>;
1364 compatible = "sirf,nocfw-mediam";
1365 reg = <0x170A0000 0x3000>;
1368 gpio_0: gpio_mediam@17040000 {
1370 #interrupt-cells = <2>;
1371 compatible = "sirf,atlas7-gpio";
1372 reg = <0x17040000 0x1000>;
1373 interrupts = <0 13 0>, <0 14 0>;
1374 clocks = <&car 107>;
1375 clock-names = "gpio0_io";
1377 interrupt-controller;
1380 gpio-ranges = <&pinctrl 0 0 0>,
1382 gpio-ranges-group-names = "lvds_gpio_grp",
1383 "uart_nand_gpio_grp";
1387 compatible = "sirf,atlas7-nand";
1388 reg = <0x17050000 0x10000>;
1389 interrupts = <0 41 0>;
1390 clocks = <&car 108>, <&car 112>;
1391 clock-names = "nand_io", "nand_nand";
1394 sd0: sdhci@16000000 {
1396 compatible = "sirf,atlas7-sdhc";
1397 reg = <0x16000000 0x100000>;
1398 interrupts = <0 38 0>;
1399 clocks = <&car 109>, <&car 111>;
1400 clock-names = "core", "iface";
1403 status = "disabled";
1407 sd1: sdhci@16100000 {
1409 compatible = "sirf,atlas7-sdhc";
1410 reg = <0x16100000 0x100000>;
1411 interrupts = <0 38 0>;
1412 clocks = <&car 109>, <&car 111>;
1413 clock-names = "core", "iface";
1415 status = "disabled";
1419 usb0: usb@17060000 {
1421 compatible = "sirf,atlas7-usb";
1422 reg = <0x17060000 0x200>;
1423 interrupts = <0 10 0>;
1424 clocks = <&car 113>;
1425 sirf,usbphy = <&usbphy0>;
1428 maximum-speed = "high-speed";
1432 usb1: usb@17070000 {
1434 compatible = "sirf,atlas7-usb";
1435 reg = <0x17070000 0x200>;
1436 interrupts = <0 11 0>;
1437 clocks = <&car 114>;
1438 sirf,usbphy = <&usbphy1>;
1441 maximum-speed = "high-speed";
1446 compatible = "sirf,atlas7-usbphy";
1447 reg = <0x17060200 0x100>;
1448 clocks = <&car 115>;
1453 compatible = "sirf,atlas7-usbphy";
1454 reg = <0x17070200 0x100>;
1455 clocks = <&car 116>;
1459 i2c0: i2c@17020000 {
1461 compatible = "sirf,prima2-i2c";
1462 reg = <0x17020000 0x1000>;
1463 interrupts = <0 24 0>;
1464 clocks = <&car 105>;
1465 #address-cells = <1>;
1472 compatible = "arteris, flexnoc", "simple-bus";
1473 #address-cells = <1>;
1475 ranges = <0x13290000 0x13290000 0x3000>,
1476 <0x13300000 0x13300000 0x1000>,
1477 <0x14200000 0x14200000 0x600000>;
1480 compatible = "sirf,nocfw-vdifm";
1481 reg = <0x13290000 0x3000>;
1484 gpio_1: gpio_vdifm@13300000 {
1486 #interrupt-cells = <2>;
1487 compatible = "sirf,atlas7-gpio";
1488 reg = <0x13300000 0x1000>;
1489 interrupts = <0 43 0>, <0 44 0>,
1492 clock-names = "gpio1_io";
1494 interrupt-controller;
1497 gpio-ranges = <&pinctrl 0 0 0>,
1501 gpio-ranges-group-names = "gnss_gpio_grp",
1503 "sdio_i2s_gpio_grp",
1504 "sp_rgmii_gpio_grp";
1507 sd2: sdhci@14200000 {
1509 compatible = "sirf,atlas7-sdhc";
1510 reg = <0x14200000 0x100000>;
1511 interrupts = <0 23 0>;
1512 clocks = <&car 70>, <&car 75>;
1513 clock-names = "core", "iface";
1514 status = "disabled";
1517 vqmmc-supply = <&vqmmc>;
1519 regulator-min-microvolt = <1650000>;
1520 regulator-max-microvolt = <1950000>;
1521 regulator-name = "vqmmc-ldo";
1522 regulator-type = "voltage";
1524 regulator-allow-bypass;
1528 sd3: sdhci@14300000 {
1530 compatible = "sirf,atlas7-sdhc";
1531 reg = <0x14300000 0x100000>;
1532 interrupts = <0 23 0>;
1533 clocks = <&car 76>, <&car 81>;
1534 clock-names = "core", "iface";
1535 status = "disabled";
1539 sd5: sdhci@14500000 {
1541 compatible = "sirf,atlas7-sdhc";
1542 reg = <0x14500000 0x100000>;
1543 interrupts = <0 39 0>;
1544 clocks = <&car 71>, <&car 76>;
1545 clock-names = "core", "iface";
1546 status = "disabled";
1551 sd6: sdhci@14600000 {
1553 compatible = "sirf,atlas7-sdhc";
1554 reg = <0x14600000 0x100000>;
1555 interrupts = <0 98 0>;
1556 clocks = <&car 72>, <&car 77>;
1557 clock-names = "core", "iface";
1558 status = "disabled";
1562 sd7: sdhci@14700000 {
1564 compatible = "sirf,atlas7-sdhc";
1565 reg = <0x14700000 0x100000>;
1566 interrupts = <0 98 0>;
1567 clocks = <&car 72>, <&car 77>;
1568 clock-names = "core", "iface";
1569 status = "disabled";
1575 compatible = "arteris, flexnoc", "simple-bus";
1576 #address-cells = <1>;
1578 ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1579 <0x10d60000 0x10d60000 0x0000ffff>,
1580 <0x10d80000 0x10d80000 0x0000ffff>,
1581 <0x10d90000 0x10d90000 0x0000ffff>,
1582 <0x10ED0000 0x10ED0000 0x3000>,
1583 <0x10dc8000 0x10dc8000 0x1000>,
1584 <0x10dc0000 0x10dc0000 0x1000>,
1585 <0x10db0000 0x10db0000 0x4000>,
1586 <0x10d40000 0x10d40000 0x1000>,
1587 <0x10d30000 0x10d30000 0x1000>;
1590 compatible = "sirf,atlas7-tick";
1591 reg = <0x10dc0000 0x1000>;
1592 interrupts = <0 0 0>,
1602 compatible = "sirf,atlas7-tick";
1603 reg = <0x10dc8000 0x1000>;
1604 interrupts = <0 74 0>,
1614 compatible = "sirf,atlas7-vip0";
1615 reg = <0x10db0000 0x2000>;
1616 interrupts = <0 85 0>;
1617 sirf,vip_cma_size = <0xC00000>;
1621 compatible = "sirf,cvd";
1622 reg = <0x10db2000 0x2000>;
1626 dmac2: dma-controller@10d50000 {
1628 compatible = "sirf,atlas7-dmac";
1629 reg = <0x10d50000 0xffff>;
1630 interrupts = <0 55 0>;
1632 dma-channels = <16>;
1636 dmac3: dma-controller@10d60000 {
1638 compatible = "sirf,atlas7-dmac";
1639 reg = <0x10d60000 0xffff>;
1640 interrupts = <0 56 0>;
1642 dma-channels = <16>;
1647 compatible = "sirf,atlas7-adc";
1648 reg = <0x10d80000 0xffff>;
1649 interrupts = <0 34 0>;
1651 #io-channel-cells = <1>;
1655 compatible = "sirf,prima2-pulsec";
1656 reg = <0x10d90000 0xffff>;
1657 interrupts = <0 42 0>;
1662 compatible = "sirf,nocfw-audiom";
1663 reg = <0x10ED0000 0x3000>;
1664 interrupts = <0 102 0>;
1667 usp1: usp@10d30000 {
1669 reg = <0x10d30000 0x1000>;
1672 dmas = <&dmac2 6>, <&dmac2 7>;
1673 dma-names = "rx", "tx";
1676 usp2: usp@10d40000 {
1678 reg = <0x10d40000 0x1000>;
1679 interrupts = <0 22 0>;
1681 dmas = <&dmac2 12>, <&dmac2 13>;
1682 dma-names = "rx", "tx";
1683 #address-cells = <1>;
1685 status = "disabled";
1690 compatible = "arteris, flexnoc", "simple-bus";
1691 #address-cells = <1>;
1693 ranges = <0x10820000 0x10820000 0x3000>,
1694 <0x10800000 0x10800000 0x2000>;
1696 compatible = "sirf,nocfw-ddrm";
1697 reg = <0x10820000 0x3000>;
1698 interrupts = <0 105 0>;
1701 memory-controller@0x10800000 {
1702 compatible = "sirf,atlas7-memc";
1703 reg = <0x10800000 0x2000>;
1709 compatible = "arteris, flexnoc", "simple-bus";
1710 #address-cells = <1>;
1712 ranges = <0x11002000 0x11002000 0x0000ffff>,
1713 <0x11010000 0x11010000 0x3000>,
1714 <0x11000000 0x11000000 0x1000>,
1715 <0x11001000 0x11001000 0x1000>;
1717 dmac4: dma-controller@11002000 {
1719 compatible = "sirf,atlas7-dmac";
1720 reg = <0x11002000 0x1000>;
1721 interrupts = <0 99 0>;
1722 clocks = <&car 130>;
1723 dma-channels = <16>;
1726 uart6: uart@11000000 {
1728 compatible = "sirf,atlas7-bt-uart",
1730 reg = <0x11000000 0x1000>;
1731 interrupts = <0 100 0>;
1732 clocks = <&car 131>, <&car 133>, <&car 134>;
1733 clock-names = "uart", "general", "noc";
1735 dmas = <&dmac4 12>, <&dmac4 13>;
1736 dma-names = "rx", "tx";
1737 status = "disabled";
1740 usp3: usp@11001000 {
1741 compatible = "sirf,atlas7-bt-usp",
1742 "sirf,prima2-usp-pcm";
1744 reg = <0x11001000 0x1000>;
1746 clocks = <&car 132>, <&car 129>, <&car 133>,
1747 <&car 134>, <&car 135>;
1748 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
1749 "noc_btm_io", "thbtm_io";
1750 dmas = <&dmac4 0>, <&dmac4 1>;
1751 dma-names = "rx", "tx";
1755 compatible = "sirf,nocfw-btm";
1756 reg = <0x11010000 0x3000>;
1761 compatible = "arteris, flexnoc", "simple-bus";
1762 #address-cells = <1>;
1764 ranges = <0x18810000 0x18810000 0x3000>,
1765 <0x18840000 0x18840000 0x1000>,
1766 <0x18890000 0x18890000 0x1000>,
1767 <0x188B0000 0x188B0000 0x10000>,
1768 <0x188D0000 0x188D0000 0x1000>;
1770 compatible = "sirf,nocfw-rtcm";
1771 reg = <0x18810000 0x3000>;
1772 interrupts = <0 109 0>;
1775 gpio_2: gpio_rtcm@18890000 {
1777 #interrupt-cells = <2>;
1778 compatible = "sirf,atlas7-gpio";
1779 reg = <0x18890000 0x1000>;
1780 interrupts = <0 47 0>;
1782 interrupt-controller;
1785 gpio-ranges = <&pinctrl 0 0 0>;
1786 gpio-ranges-group-names = "rtc_gpio_grp";
1790 compatible = "sirf,prima2-rtciobg",
1791 "sirf-prima2-rtciobg-bus",
1793 #address-cells = <1>;
1795 reg = <0x18840000 0x1000>;
1798 compatible = "sirf,prima2-sysrtc";
1799 reg = <0x2000 0x100>;
1800 interrupts = <0 52 0>;
1803 compatible = "sirf,atlas7-pwrc";
1804 reg = <0x3000 0x100>;
1808 qspi: flash@188B0000 {
1810 compatible = "sirf,atlas7-qspi-nor";
1811 reg = <0x188B0000 0x10000>;
1812 interrupts = <0 15 0>;
1813 #address-cells = <1>;
1818 compatible = "sirf,atlas7-retain";
1819 reg = <0x188D0000 0x1000>;
1825 compatible = "simple-bus";
1826 #address-cells = <1>;
1828 ranges = <0x13100000 0x13100000 0x20000>,
1829 <0x10e10000 0x10e10000 0x10000>;
1832 compatible = "sirf,atlas7-lcdc";
1833 reg = <0x13100000 0x10000>;
1834 interrupts = <0 30 0>;
1838 compatible = "sirf,atlas7-vpp";
1839 reg = <0x13110000 0x10000>;
1840 interrupts = <0 31 0>;
1845 compatible = "sirf,atlas7-lvdsc";
1846 reg = <0x10e10000 0x10000>;
1847 interrupts = <0 64 0>;
1855 compatible = "simple-bus";
1856 #address-cells = <1>;
1858 ranges = <0x12000000 0x12000000 0x1000000>;
1861 compatible = "powervr,sgx531";
1862 reg = <0x12000000 0x1000000>;
1863 interrupts = <0 6 0>;
1864 clocks = <&car 126>;