1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2500";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm1176jzf-s";
46 device_type = "memory";
51 compatible = "simple-bus";
57 reg = < 0x1e620000 0xc4
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
73 compatible = "jedec,spi-nor";
74 spi-max-frequency = <50000000>;
79 compatible = "jedec,spi-nor";
80 spi-max-frequency = <50000000>;
86 reg = < 0x1e630000 0xc4
87 0x30000000 0x08000000 >;
90 compatible = "aspeed,ast2500-spi";
91 clocks = <&syscon ASPEED_CLK_AHB>;
95 compatible = "jedec,spi-nor";
96 spi-max-frequency = <50000000>;
101 compatible = "jedec,spi-nor";
102 spi-max-frequency = <50000000>;
108 reg = < 0x1e631000 0xc4
109 0x38000000 0x08000000 >;
110 #address-cells = <1>;
112 compatible = "aspeed,ast2500-spi";
113 clocks = <&syscon ASPEED_CLK_AHB>;
117 compatible = "jedec,spi-nor";
118 spi-max-frequency = <50000000>;
123 compatible = "jedec,spi-nor";
124 spi-max-frequency = <50000000>;
129 vic: interrupt-controller@1e6c0080 {
130 compatible = "aspeed,ast2400-vic";
131 interrupt-controller;
132 #interrupt-cells = <1>;
133 valid-sources = <0xfefff7ff 0x0807ffff>;
134 reg = <0x1e6c0080 0x80>;
137 cvic: copro-interrupt-controller@1e6c2000 {
138 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
139 valid-sources = <0xffffffff>;
140 copro-sw-interrupts = <1>;
141 reg = <0x1e6c2000 0x80>;
144 mac0: ethernet@1e660000 {
145 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
146 reg = <0x1e660000 0x180>;
148 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
152 mac1: ethernet@1e680000 {
153 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
154 reg = <0x1e680000 0x180>;
156 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
160 ehci0: usb@1e6a1000 {
161 compatible = "aspeed,ast2500-ehci", "generic-ehci";
162 reg = <0x1e6a1000 0x100>;
164 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usb2ah_default>;
170 ehci1: usb@1e6a3000 {
171 compatible = "aspeed,ast2500-ehci", "generic-ehci";
172 reg = <0x1e6a3000 0x100>;
174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_usb2bh_default>;
181 compatible = "aspeed,ast2500-uhci", "generic-uhci";
182 reg = <0x1e6b0000 0x100>;
185 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
188 * No default pinmux, it will follow EHCI, use an explicit pinmux
189 * override if you don't enable EHCI
193 vhub: usb-vhub@1e6a0000 {
194 compatible = "aspeed,ast2500-usb-vhub";
195 reg = <0x1e6a0000 0x300>;
197 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
198 aspeed,vhub-downstream-ports = <5>;
199 aspeed,vhub-generic-endpoints = <15>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_usb2ad_default>;
206 compatible = "simple-bus";
207 #address-cells = <1>;
211 edac: memory-controller@1e6e0000 {
212 compatible = "aspeed,ast2500-sdram-edac";
213 reg = <0x1e6e0000 0x174>;
218 syscon: syscon@1e6e2000 {
219 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
220 reg = <0x1e6e2000 0x1a8>;
221 #address-cells = <1>;
223 ranges = <0 0x1e6e2000 0x1000>;
227 scu_ic: interrupt-controller@18 {
228 #interrupt-cells = <1>;
229 compatible = "aspeed,ast2500-scu-ic";
232 interrupt-controller;
235 p2a: p2a-control@2c {
236 compatible = "aspeed,ast2500-p2a-ctrl";
241 pinctrl: pinctrl@80 {
242 compatible = "aspeed,ast2500-pinctrl";
243 reg = <0x80 0x18>, <0xa0 0x10>;
244 aspeed,external-nodes = <&gfx>, <&lhc>;
248 rng: hwrng@1e6e2078 {
249 compatible = "timeriomem_rng";
250 reg = <0x1e6e2078 0x4>;
255 gfx: display@1e6e6000 {
256 compatible = "aspeed,ast2500-gfx", "syscon";
257 reg = <0x1e6e6000 0x1000>;
259 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
260 resets = <&syscon ASPEED_RESET_CRT1>;
265 xdma: xdma@1e6e7000 {
266 compatible = "aspeed,ast2500-xdma";
267 reg = <0x1e6e7000 0x100>;
268 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
269 resets = <&syscon ASPEED_RESET_XDMA>;
270 interrupts-extended = <&vic 6>, <&scu_ic 2>;
272 aspeed,scu = <&syscon>;
277 compatible = "aspeed,ast2500-adc";
278 reg = <0x1e6e9000 0xb0>;
279 clocks = <&syscon ASPEED_CLK_APB>;
280 resets = <&syscon ASPEED_RESET_ADC>;
281 #io-channel-cells = <1>;
285 video: video@1e700000 {
286 compatible = "aspeed,ast2500-video-engine";
287 reg = <0x1e700000 0x1000>;
288 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
289 <&syscon ASPEED_CLK_GATE_ECLK>;
290 clock-names = "vclk", "eclk";
295 sram: sram@1e720000 {
296 compatible = "mmio-sram";
297 reg = <0x1e720000 0x9000>; // 36K
300 sdmmc: sd-controller@1e740000 {
301 compatible = "aspeed,ast2500-sd-controller";
302 reg = <0x1e740000 0x100>;
303 #address-cells = <1>;
305 ranges = <0 0x1e740000 0x10000>;
306 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
310 compatible = "aspeed,ast2500-sdhci";
314 clocks = <&syscon ASPEED_CLK_SDIO>;
319 compatible = "aspeed,ast2500-sdhci";
323 clocks = <&syscon ASPEED_CLK_SDIO>;
328 gpio: gpio@1e780000 {
331 compatible = "aspeed,ast2500-gpio";
332 reg = <0x1e780000 0x200>;
334 gpio-ranges = <&pinctrl 0 0 232>;
335 clocks = <&syscon ASPEED_CLK_APB>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
340 sgpio: sgpio@1e780200 {
342 compatible = "aspeed,ast2500-sgpio";
345 reg = <0x1e780200 0x0100>;
346 clocks = <&syscon ASPEED_CLK_APB>;
347 interrupt-controller;
349 bus-frequency = <12000000>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_sgpm_default>;
356 compatible = "aspeed,ast2500-rtc";
357 reg = <0x1e781000 0x18>;
361 timer: timer@1e782000 {
362 /* This timer is a Faraday FTTMR010 derivative */
363 compatible = "aspeed,ast2400-timer";
364 reg = <0x1e782000 0x90>;
365 interrupts = <16 17 18 35 36 37 38 39>;
366 clocks = <&syscon ASPEED_CLK_APB>;
367 clock-names = "PCLK";
370 uart1: serial@1e783000 {
371 compatible = "ns16550a";
372 reg = <0x1e783000 0x20>;
375 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
376 resets = <&lpc_reset 4>;
381 uart5: serial@1e784000 {
382 compatible = "ns16550a";
383 reg = <0x1e784000 0x20>;
386 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
391 wdt1: watchdog@1e785000 {
392 compatible = "aspeed,ast2500-wdt";
393 reg = <0x1e785000 0x20>;
394 clocks = <&syscon ASPEED_CLK_APB>;
397 wdt2: watchdog@1e785020 {
398 compatible = "aspeed,ast2500-wdt";
399 reg = <0x1e785020 0x20>;
400 clocks = <&syscon ASPEED_CLK_APB>;
403 wdt3: watchdog@1e785040 {
404 compatible = "aspeed,ast2500-wdt";
405 reg = <0x1e785040 0x20>;
406 clocks = <&syscon ASPEED_CLK_APB>;
410 pwm_tacho: pwm-tacho-controller@1e786000 {
411 compatible = "aspeed,ast2500-pwm-tacho";
412 #address-cells = <1>;
414 reg = <0x1e786000 0x1000>;
415 clocks = <&syscon ASPEED_CLK_24M>;
416 resets = <&syscon ASPEED_RESET_PWM>;
420 vuart: serial@1e787000 {
421 compatible = "aspeed,ast2500-vuart";
422 reg = <0x1e787000 0x40>;
425 clocks = <&syscon ASPEED_CLK_APB>;
427 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
432 compatible = "aspeed,ast2500-lpc", "simple-mfd";
433 reg = <0x1e789000 0x1000>;
435 #address-cells = <1>;
437 ranges = <0x0 0x1e789000 0x1000>;
440 compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
444 #address-cells = <1>;
446 ranges = <0x0 0x0 0x80>;
449 compatible = "aspeed,ast2500-kcs-bmc-v2";
450 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
455 compatible = "aspeed,ast2500-kcs-bmc-v2";
456 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
461 compatible = "aspeed,ast2500-kcs-bmc-v2";
462 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
468 lpc_host: lpc-host@80 {
469 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
473 #address-cells = <1>;
475 ranges = <0x0 0x80 0x1e0>;
478 compatible = "aspeed,ast2500-kcs-bmc-v2";
479 reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
484 lpc_ctrl: lpc-ctrl@0 {
485 compatible = "aspeed,ast2500-lpc-ctrl";
487 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
491 lpc_snoop: lpc-snoop@10 {
492 compatible = "aspeed,ast2500-lpc-snoop";
498 lpc_reset: reset-controller@18 {
499 compatible = "aspeed,ast2500-lpc-reset";
505 compatible = "aspeed,ast2500-lhc";
506 reg = <0x20 0x24 0x48 0x8>;
511 compatible = "aspeed,ast2500-ibt-bmc";
519 uart2: serial@1e78d000 {
520 compatible = "ns16550a";
521 reg = <0x1e78d000 0x20>;
524 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
525 resets = <&lpc_reset 5>;
530 uart3: serial@1e78e000 {
531 compatible = "ns16550a";
532 reg = <0x1e78e000 0x20>;
535 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
536 resets = <&lpc_reset 6>;
541 uart4: serial@1e78f000 {
542 compatible = "ns16550a";
543 reg = <0x1e78f000 0x20>;
546 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
547 resets = <&lpc_reset 7>;
553 compatible = "simple-bus";
554 #address-cells = <1>;
556 ranges = <0 0x1e78a000 0x1000>;
563 i2c_ic: interrupt-controller@0 {
564 #interrupt-cells = <1>;
565 compatible = "aspeed,ast2500-i2c-ic";
568 interrupt-controller;
572 #address-cells = <1>;
574 #interrupt-cells = <1>;
577 compatible = "aspeed,ast2500-i2c-bus";
578 clocks = <&syscon ASPEED_CLK_APB>;
579 resets = <&syscon ASPEED_RESET_I2C>;
580 bus-frequency = <100000>;
582 interrupt-parent = <&i2c_ic>;
584 /* Does not need pinctrl properties */
588 #address-cells = <1>;
590 #interrupt-cells = <1>;
593 compatible = "aspeed,ast2500-i2c-bus";
594 clocks = <&syscon ASPEED_CLK_APB>;
595 resets = <&syscon ASPEED_RESET_I2C>;
596 bus-frequency = <100000>;
598 interrupt-parent = <&i2c_ic>;
600 /* Does not need pinctrl properties */
604 #address-cells = <1>;
606 #interrupt-cells = <1>;
609 compatible = "aspeed,ast2500-i2c-bus";
610 clocks = <&syscon ASPEED_CLK_APB>;
611 resets = <&syscon ASPEED_RESET_I2C>;
612 bus-frequency = <100000>;
614 interrupt-parent = <&i2c_ic>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_i2c3_default>;
621 #address-cells = <1>;
623 #interrupt-cells = <1>;
626 compatible = "aspeed,ast2500-i2c-bus";
627 clocks = <&syscon ASPEED_CLK_APB>;
628 resets = <&syscon ASPEED_RESET_I2C>;
629 bus-frequency = <100000>;
631 interrupt-parent = <&i2c_ic>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&pinctrl_i2c4_default>;
638 #address-cells = <1>;
640 #interrupt-cells = <1>;
643 compatible = "aspeed,ast2500-i2c-bus";
644 clocks = <&syscon ASPEED_CLK_APB>;
645 resets = <&syscon ASPEED_RESET_I2C>;
646 bus-frequency = <100000>;
648 interrupt-parent = <&i2c_ic>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&pinctrl_i2c5_default>;
655 #address-cells = <1>;
657 #interrupt-cells = <1>;
660 compatible = "aspeed,ast2500-i2c-bus";
661 clocks = <&syscon ASPEED_CLK_APB>;
662 resets = <&syscon ASPEED_RESET_I2C>;
663 bus-frequency = <100000>;
665 interrupt-parent = <&i2c_ic>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_i2c6_default>;
672 #address-cells = <1>;
674 #interrupt-cells = <1>;
677 compatible = "aspeed,ast2500-i2c-bus";
678 clocks = <&syscon ASPEED_CLK_APB>;
679 resets = <&syscon ASPEED_RESET_I2C>;
680 bus-frequency = <100000>;
682 interrupt-parent = <&i2c_ic>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_i2c7_default>;
689 #address-cells = <1>;
691 #interrupt-cells = <1>;
694 compatible = "aspeed,ast2500-i2c-bus";
695 clocks = <&syscon ASPEED_CLK_APB>;
696 resets = <&syscon ASPEED_RESET_I2C>;
697 bus-frequency = <100000>;
699 interrupt-parent = <&i2c_ic>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_i2c8_default>;
706 #address-cells = <1>;
708 #interrupt-cells = <1>;
711 compatible = "aspeed,ast2500-i2c-bus";
712 clocks = <&syscon ASPEED_CLK_APB>;
713 resets = <&syscon ASPEED_RESET_I2C>;
714 bus-frequency = <100000>;
716 interrupt-parent = <&i2c_ic>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pinctrl_i2c9_default>;
723 #address-cells = <1>;
725 #interrupt-cells = <1>;
728 compatible = "aspeed,ast2500-i2c-bus";
729 clocks = <&syscon ASPEED_CLK_APB>;
730 resets = <&syscon ASPEED_RESET_I2C>;
731 bus-frequency = <100000>;
733 interrupt-parent = <&i2c_ic>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_i2c10_default>;
740 #address-cells = <1>;
742 #interrupt-cells = <1>;
745 compatible = "aspeed,ast2500-i2c-bus";
746 clocks = <&syscon ASPEED_CLK_APB>;
747 resets = <&syscon ASPEED_RESET_I2C>;
748 bus-frequency = <100000>;
750 interrupt-parent = <&i2c_ic>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_i2c11_default>;
757 #address-cells = <1>;
759 #interrupt-cells = <1>;
762 compatible = "aspeed,ast2500-i2c-bus";
763 clocks = <&syscon ASPEED_CLK_APB>;
764 resets = <&syscon ASPEED_RESET_I2C>;
765 bus-frequency = <100000>;
767 interrupt-parent = <&i2c_ic>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&pinctrl_i2c12_default>;
774 #address-cells = <1>;
776 #interrupt-cells = <1>;
779 compatible = "aspeed,ast2500-i2c-bus";
780 clocks = <&syscon ASPEED_CLK_APB>;
781 resets = <&syscon ASPEED_RESET_I2C>;
782 bus-frequency = <100000>;
784 interrupt-parent = <&i2c_ic>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_i2c13_default>;
791 #address-cells = <1>;
793 #interrupt-cells = <1>;
796 compatible = "aspeed,ast2500-i2c-bus";
797 clocks = <&syscon ASPEED_CLK_APB>;
798 resets = <&syscon ASPEED_RESET_I2C>;
799 bus-frequency = <100000>;
801 interrupt-parent = <&i2c_ic>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&pinctrl_i2c14_default>;
809 pinctrl_acpi_default: acpi_default {
814 pinctrl_adc0_default: adc0_default {
819 pinctrl_adc1_default: adc1_default {
824 pinctrl_adc10_default: adc10_default {
829 pinctrl_adc11_default: adc11_default {
834 pinctrl_adc12_default: adc12_default {
839 pinctrl_adc13_default: adc13_default {
844 pinctrl_adc14_default: adc14_default {
849 pinctrl_adc15_default: adc15_default {
854 pinctrl_adc2_default: adc2_default {
859 pinctrl_adc3_default: adc3_default {
864 pinctrl_adc4_default: adc4_default {
869 pinctrl_adc5_default: adc5_default {
874 pinctrl_adc6_default: adc6_default {
879 pinctrl_adc7_default: adc7_default {
884 pinctrl_adc8_default: adc8_default {
889 pinctrl_adc9_default: adc9_default {
894 pinctrl_bmcint_default: bmcint_default {
899 pinctrl_ddcclk_default: ddcclk_default {
904 pinctrl_ddcdat_default: ddcdat_default {
909 pinctrl_espi_default: espi_default {
914 pinctrl_fwspics1_default: fwspics1_default {
915 function = "FWSPICS1";
919 pinctrl_fwspics2_default: fwspics2_default {
920 function = "FWSPICS2";
924 pinctrl_gpid0_default: gpid0_default {
929 pinctrl_gpid2_default: gpid2_default {
934 pinctrl_gpid4_default: gpid4_default {
939 pinctrl_gpid6_default: gpid6_default {
944 pinctrl_gpie0_default: gpie0_default {
949 pinctrl_gpie2_default: gpie2_default {
954 pinctrl_gpie4_default: gpie4_default {
959 pinctrl_gpie6_default: gpie6_default {
964 pinctrl_i2c10_default: i2c10_default {
969 pinctrl_i2c11_default: i2c11_default {
974 pinctrl_i2c12_default: i2c12_default {
979 pinctrl_i2c13_default: i2c13_default {
984 pinctrl_i2c14_default: i2c14_default {
989 pinctrl_i2c3_default: i2c3_default {
994 pinctrl_i2c4_default: i2c4_default {
999 pinctrl_i2c5_default: i2c5_default {
1004 pinctrl_i2c6_default: i2c6_default {
1009 pinctrl_i2c7_default: i2c7_default {
1014 pinctrl_i2c8_default: i2c8_default {
1019 pinctrl_i2c9_default: i2c9_default {
1024 pinctrl_lad0_default: lad0_default {
1029 pinctrl_lad1_default: lad1_default {
1034 pinctrl_lad2_default: lad2_default {
1039 pinctrl_lad3_default: lad3_default {
1044 pinctrl_lclk_default: lclk_default {
1049 pinctrl_lframe_default: lframe_default {
1050 function = "LFRAME";
1054 pinctrl_lpchc_default: lpchc_default {
1059 pinctrl_lpcpd_default: lpcpd_default {
1064 pinctrl_lpcplus_default: lpcplus_default {
1065 function = "LPCPLUS";
1069 pinctrl_lpcpme_default: lpcpme_default {
1070 function = "LPCPME";
1074 pinctrl_lpcrst_default: lpcrst_default {
1075 function = "LPCRST";
1079 pinctrl_lpcsmi_default: lpcsmi_default {
1080 function = "LPCSMI";
1084 pinctrl_lsirq_default: lsirq_default {
1089 pinctrl_mac1link_default: mac1link_default {
1090 function = "MAC1LINK";
1091 groups = "MAC1LINK";
1094 pinctrl_mac2link_default: mac2link_default {
1095 function = "MAC2LINK";
1096 groups = "MAC2LINK";
1099 pinctrl_mdio1_default: mdio1_default {
1104 pinctrl_mdio2_default: mdio2_default {
1109 pinctrl_ncts1_default: ncts1_default {
1114 pinctrl_ncts2_default: ncts2_default {
1119 pinctrl_ncts3_default: ncts3_default {
1124 pinctrl_ncts4_default: ncts4_default {
1129 pinctrl_ndcd1_default: ndcd1_default {
1134 pinctrl_ndcd2_default: ndcd2_default {
1139 pinctrl_ndcd3_default: ndcd3_default {
1144 pinctrl_ndcd4_default: ndcd4_default {
1149 pinctrl_ndsr1_default: ndsr1_default {
1154 pinctrl_ndsr2_default: ndsr2_default {
1159 pinctrl_ndsr3_default: ndsr3_default {
1164 pinctrl_ndsr4_default: ndsr4_default {
1169 pinctrl_ndtr1_default: ndtr1_default {
1174 pinctrl_ndtr2_default: ndtr2_default {
1179 pinctrl_ndtr3_default: ndtr3_default {
1184 pinctrl_ndtr4_default: ndtr4_default {
1189 pinctrl_nri1_default: nri1_default {
1194 pinctrl_nri2_default: nri2_default {
1199 pinctrl_nri3_default: nri3_default {
1204 pinctrl_nri4_default: nri4_default {
1209 pinctrl_nrts1_default: nrts1_default {
1214 pinctrl_nrts2_default: nrts2_default {
1219 pinctrl_nrts3_default: nrts3_default {
1224 pinctrl_nrts4_default: nrts4_default {
1229 pinctrl_oscclk_default: oscclk_default {
1230 function = "OSCCLK";
1234 pinctrl_pewake_default: pewake_default {
1235 function = "PEWAKE";
1239 pinctrl_pnor_default: pnor_default {
1244 pinctrl_pwm0_default: pwm0_default {
1249 pinctrl_pwm1_default: pwm1_default {
1254 pinctrl_pwm2_default: pwm2_default {
1259 pinctrl_pwm3_default: pwm3_default {
1264 pinctrl_pwm4_default: pwm4_default {
1269 pinctrl_pwm5_default: pwm5_default {
1274 pinctrl_pwm6_default: pwm6_default {
1279 pinctrl_pwm7_default: pwm7_default {
1284 pinctrl_rgmii1_default: rgmii1_default {
1285 function = "RGMII1";
1289 pinctrl_rgmii2_default: rgmii2_default {
1290 function = "RGMII2";
1294 pinctrl_rmii1_default: rmii1_default {
1299 pinctrl_rmii2_default: rmii2_default {
1304 pinctrl_rxd1_default: rxd1_default {
1309 pinctrl_rxd2_default: rxd2_default {
1314 pinctrl_rxd3_default: rxd3_default {
1319 pinctrl_rxd4_default: rxd4_default {
1324 pinctrl_salt1_default: salt1_default {
1329 pinctrl_salt10_default: salt10_default {
1330 function = "SALT10";
1334 pinctrl_salt11_default: salt11_default {
1335 function = "SALT11";
1339 pinctrl_salt12_default: salt12_default {
1340 function = "SALT12";
1344 pinctrl_salt13_default: salt13_default {
1345 function = "SALT13";
1349 pinctrl_salt14_default: salt14_default {
1350 function = "SALT14";
1354 pinctrl_salt2_default: salt2_default {
1359 pinctrl_salt3_default: salt3_default {
1364 pinctrl_salt4_default: salt4_default {
1369 pinctrl_salt5_default: salt5_default {
1374 pinctrl_salt6_default: salt6_default {
1379 pinctrl_salt7_default: salt7_default {
1384 pinctrl_salt8_default: salt8_default {
1389 pinctrl_salt9_default: salt9_default {
1394 pinctrl_scl1_default: scl1_default {
1399 pinctrl_scl2_default: scl2_default {
1404 pinctrl_sd1_default: sd1_default {
1409 pinctrl_sd2_default: sd2_default {
1414 pinctrl_sda1_default: sda1_default {
1419 pinctrl_sda2_default: sda2_default {
1424 pinctrl_sgpm_default: sgpm_default {
1429 pinctrl_sgps1_default: sgps1_default {
1434 pinctrl_sgps2_default: sgps2_default {
1439 pinctrl_sioonctrl_default: sioonctrl_default {
1440 function = "SIOONCTRL";
1441 groups = "SIOONCTRL";
1444 pinctrl_siopbi_default: siopbi_default {
1445 function = "SIOPBI";
1449 pinctrl_siopbo_default: siopbo_default {
1450 function = "SIOPBO";
1454 pinctrl_siopwreq_default: siopwreq_default {
1455 function = "SIOPWREQ";
1456 groups = "SIOPWREQ";
1459 pinctrl_siopwrgd_default: siopwrgd_default {
1460 function = "SIOPWRGD";
1461 groups = "SIOPWRGD";
1464 pinctrl_sios3_default: sios3_default {
1469 pinctrl_sios5_default: sios5_default {
1474 pinctrl_siosci_default: siosci_default {
1475 function = "SIOSCI";
1479 pinctrl_spi1_default: spi1_default {
1484 pinctrl_spi1cs1_default: spi1cs1_default {
1485 function = "SPI1CS1";
1489 pinctrl_spi1debug_default: spi1debug_default {
1490 function = "SPI1DEBUG";
1491 groups = "SPI1DEBUG";
1494 pinctrl_spi1passthru_default: spi1passthru_default {
1495 function = "SPI1PASSTHRU";
1496 groups = "SPI1PASSTHRU";
1499 pinctrl_spi2ck_default: spi2ck_default {
1500 function = "SPI2CK";
1504 pinctrl_spi2cs0_default: spi2cs0_default {
1505 function = "SPI2CS0";
1509 pinctrl_spi2cs1_default: spi2cs1_default {
1510 function = "SPI2CS1";
1514 pinctrl_spi2miso_default: spi2miso_default {
1515 function = "SPI2MISO";
1516 groups = "SPI2MISO";
1519 pinctrl_spi2mosi_default: spi2mosi_default {
1520 function = "SPI2MOSI";
1521 groups = "SPI2MOSI";
1524 pinctrl_timer3_default: timer3_default {
1525 function = "TIMER3";
1529 pinctrl_timer4_default: timer4_default {
1530 function = "TIMER4";
1534 pinctrl_timer5_default: timer5_default {
1535 function = "TIMER5";
1539 pinctrl_timer6_default: timer6_default {
1540 function = "TIMER6";
1544 pinctrl_timer7_default: timer7_default {
1545 function = "TIMER7";
1549 pinctrl_timer8_default: timer8_default {
1550 function = "TIMER8";
1554 pinctrl_txd1_default: txd1_default {
1559 pinctrl_txd2_default: txd2_default {
1564 pinctrl_txd3_default: txd3_default {
1569 pinctrl_txd4_default: txd4_default {
1574 pinctrl_uart6_default: uart6_default {
1579 pinctrl_usbcki_default: usbcki_default {
1580 function = "USBCKI";
1584 pinctrl_usb2ah_default: usb2ah_default {
1585 function = "USB2AH";
1589 pinctrl_usb2ad_default: usb2ad_default {
1590 function = "USB2AD";
1594 pinctrl_usb11bhid_default: usb11bhid_default {
1595 function = "USB11BHID";
1596 groups = "USB11BHID";
1599 pinctrl_usb2bh_default: usb2bh_default {
1600 function = "USB2BH";
1604 pinctrl_vgabiosrom_default: vgabiosrom_default {
1605 function = "VGABIOSROM";
1606 groups = "VGABIOSROM";
1609 pinctrl_vgahs_default: vgahs_default {
1614 pinctrl_vgavs_default: vgavs_default {
1619 pinctrl_vpi24_default: vpi24_default {
1624 pinctrl_vpo_default: vpo_default {
1629 pinctrl_wdtrst1_default: wdtrst1_default {
1630 function = "WDTRST1";
1634 pinctrl_wdtrst2_default: wdtrst2_default {
1635 function = "WDTRST2";