1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2500";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm1176jzf-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0xc4
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 compatible = "jedec,spi-nor";
77 compatible = "jedec,spi-nor";
82 spi1: flash-controller@1e630000 {
83 reg = < 0x1e630000 0xc4
84 0x30000000 0x08000000 >;
87 compatible = "aspeed,ast2500-spi";
88 clocks = <&syscon ASPEED_CLK_AHB>;
92 compatible = "jedec,spi-nor";
97 compatible = "jedec,spi-nor";
102 spi2: flash-controller@1e631000 {
103 reg = < 0x1e631000 0xc4
104 0x38000000 0x08000000 >;
105 #address-cells = <1>;
107 compatible = "aspeed,ast2500-spi";
108 clocks = <&syscon ASPEED_CLK_AHB>;
112 compatible = "jedec,spi-nor";
117 compatible = "jedec,spi-nor";
122 vic: interrupt-controller@1e6c0080 {
123 compatible = "aspeed,ast2400-vic";
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 valid-sources = <0xfefff7ff 0x0807ffff>;
127 reg = <0x1e6c0080 0x80>;
130 mac0: ethernet@1e660000 {
131 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
132 reg = <0x1e660000 0x180>;
134 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
138 mac1: ethernet@1e680000 {
139 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
140 reg = <0x1e680000 0x180>;
142 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
147 compatible = "simple-bus";
148 #address-cells = <1>;
152 syscon: syscon@1e6e2000 {
153 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
154 reg = <0x1e6e2000 0x1a8>;
155 #address-cells = <1>;
161 compatible = "aspeed,g5-pinctrl";
162 aspeed,external-nodes = <&gfx &lhc>;
167 gfx: display@1e6e6000 {
168 compatible = "aspeed,ast2500-gfx", "syscon";
169 reg = <0x1e6e6000 0x1000>;
174 compatible = "aspeed,ast2500-adc";
175 reg = <0x1e6e9000 0xb0>;
176 clocks = <&syscon ASPEED_CLK_APB>;
177 resets = <&syscon ASPEED_RESET_ADC>;
178 #io-channel-cells = <1>;
183 compatible = "mmio-sram";
184 reg = <0x1e720000 0x9000>; // 36K
187 gpio: gpio@1e780000 {
190 compatible = "aspeed,ast2500-gpio";
191 reg = <0x1e780000 0x1000>;
193 gpio-ranges = <&pinctrl 0 0 220>;
194 clocks = <&syscon ASPEED_CLK_APB>;
195 interrupt-controller;
198 timer: timer@1e782000 {
199 /* This timer is a Faraday FTTMR010 derivative */
200 compatible = "aspeed,ast2400-timer";
201 reg = <0x1e782000 0x90>;
202 interrupts = <16 17 18 35 36 37 38 39>;
203 clocks = <&syscon ASPEED_CLK_APB>;
204 clock-names = "PCLK";
207 uart1: serial@1e783000 {
208 compatible = "ns16550a";
209 reg = <0x1e783000 0x20>;
212 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
213 resets = <&lpc_reset 4>;
218 uart5: serial@1e784000 {
219 compatible = "ns16550a";
220 reg = <0x1e784000 0x20>;
223 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
228 wdt1: watchdog@1e785000 {
229 compatible = "aspeed,ast2500-wdt";
230 reg = <0x1e785000 0x20>;
231 clocks = <&syscon ASPEED_CLK_APB>;
234 wdt2: watchdog@1e785020 {
235 compatible = "aspeed,ast2500-wdt";
236 reg = <0x1e785020 0x20>;
237 clocks = <&syscon ASPEED_CLK_APB>;
240 wdt3: watchdog@1e785040 {
241 compatible = "aspeed,ast2500-wdt";
242 reg = <0x1e785040 0x20>;
243 clocks = <&syscon ASPEED_CLK_APB>;
247 pwm_tacho: pwm-tacho-controller@1e786000 {
248 compatible = "aspeed,ast2500-pwm-tacho";
249 #address-cells = <1>;
251 reg = <0x1e786000 0x1000>;
252 clocks = <&syscon ASPEED_CLK_APB>;
253 resets = <&syscon ASPEED_RESET_PWM>;
257 vuart: serial@1e787000 {
258 compatible = "aspeed,ast2500-vuart";
259 reg = <0x1e787000 0x40>;
262 clocks = <&syscon ASPEED_CLK_APB>;
268 compatible = "aspeed,ast2500-lpc", "simple-mfd";
269 reg = <0x1e789000 0x1000>;
271 #address-cells = <1>;
273 ranges = <0x0 0x1e789000 0x1000>;
276 compatible = "aspeed,ast2500-lpc-bmc";
280 lpc_host: lpc-host@80 {
281 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
285 #address-cells = <1>;
287 ranges = <0x0 0x80 0x1e0>;
289 lpc_ctrl: lpc-ctrl@0 {
290 compatible = "aspeed,ast2500-lpc-ctrl";
292 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
296 lpc_snoop: lpc-snoop@0 {
297 compatible = "aspeed,ast2500-lpc-snoop";
304 compatible = "aspeed,ast2500-lhc";
305 reg = <0x20 0x24 0x48 0x8>;
308 lpc_reset: reset-controller@18 {
309 compatible = "aspeed,ast2500-lpc-reset";
315 compatible = "aspeed,ast2500-ibt-bmc";
323 uart2: serial@1e78d000 {
324 compatible = "ns16550a";
325 reg = <0x1e78d000 0x20>;
328 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
329 resets = <&lpc_reset 5>;
334 uart3: serial@1e78e000 {
335 compatible = "ns16550a";
336 reg = <0x1e78e000 0x20>;
339 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
340 resets = <&lpc_reset 6>;
345 uart4: serial@1e78f000 {
346 compatible = "ns16550a";
347 reg = <0x1e78f000 0x20>;
350 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
351 resets = <&lpc_reset 7>;
357 compatible = "simple-bus";
358 #address-cells = <1>;
360 ranges = <0 0x1e78a000 0x1000>;
367 i2c_ic: interrupt-controller@0 {
368 #interrupt-cells = <1>;
369 compatible = "aspeed,ast2500-i2c-ic";
372 interrupt-controller;
376 #address-cells = <1>;
378 #interrupt-cells = <1>;
381 compatible = "aspeed,ast2500-i2c-bus";
382 clocks = <&syscon ASPEED_CLK_APB>;
383 resets = <&syscon ASPEED_RESET_I2C>;
384 bus-frequency = <100000>;
386 interrupt-parent = <&i2c_ic>;
388 /* Does not need pinctrl properties */
392 #address-cells = <1>;
394 #interrupt-cells = <1>;
397 compatible = "aspeed,ast2500-i2c-bus";
398 clocks = <&syscon ASPEED_CLK_APB>;
399 resets = <&syscon ASPEED_RESET_I2C>;
400 bus-frequency = <100000>;
402 interrupt-parent = <&i2c_ic>;
404 /* Does not need pinctrl properties */
408 #address-cells = <1>;
410 #interrupt-cells = <1>;
413 compatible = "aspeed,ast2500-i2c-bus";
414 clocks = <&syscon ASPEED_CLK_APB>;
415 resets = <&syscon ASPEED_RESET_I2C>;
416 bus-frequency = <100000>;
418 interrupt-parent = <&i2c_ic>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_i2c3_default>;
425 #address-cells = <1>;
427 #interrupt-cells = <1>;
430 compatible = "aspeed,ast2500-i2c-bus";
431 clocks = <&syscon ASPEED_CLK_APB>;
432 resets = <&syscon ASPEED_RESET_I2C>;
433 bus-frequency = <100000>;
435 interrupt-parent = <&i2c_ic>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_i2c4_default>;
442 #address-cells = <1>;
444 #interrupt-cells = <1>;
447 compatible = "aspeed,ast2500-i2c-bus";
448 clocks = <&syscon ASPEED_CLK_APB>;
449 resets = <&syscon ASPEED_RESET_I2C>;
450 bus-frequency = <100000>;
452 interrupt-parent = <&i2c_ic>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_i2c5_default>;
459 #address-cells = <1>;
461 #interrupt-cells = <1>;
464 compatible = "aspeed,ast2500-i2c-bus";
465 clocks = <&syscon ASPEED_CLK_APB>;
466 resets = <&syscon ASPEED_RESET_I2C>;
467 bus-frequency = <100000>;
469 interrupt-parent = <&i2c_ic>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_i2c6_default>;
476 #address-cells = <1>;
478 #interrupt-cells = <1>;
481 compatible = "aspeed,ast2500-i2c-bus";
482 clocks = <&syscon ASPEED_CLK_APB>;
483 resets = <&syscon ASPEED_RESET_I2C>;
484 bus-frequency = <100000>;
486 interrupt-parent = <&i2c_ic>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_i2c7_default>;
493 #address-cells = <1>;
495 #interrupt-cells = <1>;
498 compatible = "aspeed,ast2500-i2c-bus";
499 clocks = <&syscon ASPEED_CLK_APB>;
500 resets = <&syscon ASPEED_RESET_I2C>;
501 bus-frequency = <100000>;
503 interrupt-parent = <&i2c_ic>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_i2c8_default>;
510 #address-cells = <1>;
512 #interrupt-cells = <1>;
515 compatible = "aspeed,ast2500-i2c-bus";
516 clocks = <&syscon ASPEED_CLK_APB>;
517 resets = <&syscon ASPEED_RESET_I2C>;
518 bus-frequency = <100000>;
520 interrupt-parent = <&i2c_ic>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_i2c9_default>;
527 #address-cells = <1>;
529 #interrupt-cells = <1>;
532 compatible = "aspeed,ast2500-i2c-bus";
533 clocks = <&syscon ASPEED_CLK_APB>;
534 resets = <&syscon ASPEED_RESET_I2C>;
535 bus-frequency = <100000>;
537 interrupt-parent = <&i2c_ic>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_i2c10_default>;
544 #address-cells = <1>;
546 #interrupt-cells = <1>;
549 compatible = "aspeed,ast2500-i2c-bus";
550 clocks = <&syscon ASPEED_CLK_APB>;
551 resets = <&syscon ASPEED_RESET_I2C>;
552 bus-frequency = <100000>;
554 interrupt-parent = <&i2c_ic>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_i2c11_default>;
561 #address-cells = <1>;
563 #interrupt-cells = <1>;
566 compatible = "aspeed,ast2500-i2c-bus";
567 clocks = <&syscon ASPEED_CLK_APB>;
568 resets = <&syscon ASPEED_RESET_I2C>;
569 bus-frequency = <100000>;
571 interrupt-parent = <&i2c_ic>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_i2c12_default>;
578 #address-cells = <1>;
580 #interrupt-cells = <1>;
583 compatible = "aspeed,ast2500-i2c-bus";
584 clocks = <&syscon ASPEED_CLK_APB>;
585 resets = <&syscon ASPEED_RESET_I2C>;
586 bus-frequency = <100000>;
588 interrupt-parent = <&i2c_ic>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_i2c13_default>;
595 #address-cells = <1>;
597 #interrupt-cells = <1>;
600 compatible = "aspeed,ast2500-i2c-bus";
601 clocks = <&syscon ASPEED_CLK_APB>;
602 resets = <&syscon ASPEED_RESET_I2C>;
603 bus-frequency = <100000>;
605 interrupt-parent = <&i2c_ic>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&pinctrl_i2c14_default>;
613 pinctrl_acpi_default: acpi_default {
618 pinctrl_adc0_default: adc0_default {
623 pinctrl_adc1_default: adc1_default {
628 pinctrl_adc10_default: adc10_default {
633 pinctrl_adc11_default: adc11_default {
638 pinctrl_adc12_default: adc12_default {
643 pinctrl_adc13_default: adc13_default {
648 pinctrl_adc14_default: adc14_default {
653 pinctrl_adc15_default: adc15_default {
658 pinctrl_adc2_default: adc2_default {
663 pinctrl_adc3_default: adc3_default {
668 pinctrl_adc4_default: adc4_default {
673 pinctrl_adc5_default: adc5_default {
678 pinctrl_adc6_default: adc6_default {
683 pinctrl_adc7_default: adc7_default {
688 pinctrl_adc8_default: adc8_default {
693 pinctrl_adc9_default: adc9_default {
698 pinctrl_bmcint_default: bmcint_default {
703 pinctrl_ddcclk_default: ddcclk_default {
708 pinctrl_ddcdat_default: ddcdat_default {
713 pinctrl_espi_default: espi_default {
718 pinctrl_fwspics1_default: fwspics1_default {
719 function = "FWSPICS1";
723 pinctrl_fwspics2_default: fwspics2_default {
724 function = "FWSPICS2";
728 pinctrl_gpid0_default: gpid0_default {
733 pinctrl_gpid2_default: gpid2_default {
738 pinctrl_gpid4_default: gpid4_default {
743 pinctrl_gpid6_default: gpid6_default {
748 pinctrl_gpie0_default: gpie0_default {
753 pinctrl_gpie2_default: gpie2_default {
758 pinctrl_gpie4_default: gpie4_default {
763 pinctrl_gpie6_default: gpie6_default {
768 pinctrl_i2c10_default: i2c10_default {
773 pinctrl_i2c11_default: i2c11_default {
778 pinctrl_i2c12_default: i2c12_default {
783 pinctrl_i2c13_default: i2c13_default {
788 pinctrl_i2c14_default: i2c14_default {
793 pinctrl_i2c3_default: i2c3_default {
798 pinctrl_i2c4_default: i2c4_default {
803 pinctrl_i2c5_default: i2c5_default {
808 pinctrl_i2c6_default: i2c6_default {
813 pinctrl_i2c7_default: i2c7_default {
818 pinctrl_i2c8_default: i2c8_default {
823 pinctrl_i2c9_default: i2c9_default {
828 pinctrl_lad0_default: lad0_default {
833 pinctrl_lad1_default: lad1_default {
838 pinctrl_lad2_default: lad2_default {
843 pinctrl_lad3_default: lad3_default {
848 pinctrl_lclk_default: lclk_default {
853 pinctrl_lframe_default: lframe_default {
858 pinctrl_lpchc_default: lpchc_default {
863 pinctrl_lpcpd_default: lpcpd_default {
868 pinctrl_lpcplus_default: lpcplus_default {
869 function = "LPCPLUS";
873 pinctrl_lpcpme_default: lpcpme_default {
878 pinctrl_lpcrst_default: lpcrst_default {
883 pinctrl_lpcsmi_default: lpcsmi_default {
888 pinctrl_lsirq_default: lsirq_default {
893 pinctrl_mac1link_default: mac1link_default {
894 function = "MAC1LINK";
898 pinctrl_mac2link_default: mac2link_default {
899 function = "MAC2LINK";
903 pinctrl_mdio1_default: mdio1_default {
908 pinctrl_mdio2_default: mdio2_default {
913 pinctrl_ncts1_default: ncts1_default {
918 pinctrl_ncts2_default: ncts2_default {
923 pinctrl_ncts3_default: ncts3_default {
928 pinctrl_ncts4_default: ncts4_default {
933 pinctrl_ndcd1_default: ndcd1_default {
938 pinctrl_ndcd2_default: ndcd2_default {
943 pinctrl_ndcd3_default: ndcd3_default {
948 pinctrl_ndcd4_default: ndcd4_default {
953 pinctrl_ndsr1_default: ndsr1_default {
958 pinctrl_ndsr2_default: ndsr2_default {
963 pinctrl_ndsr3_default: ndsr3_default {
968 pinctrl_ndsr4_default: ndsr4_default {
973 pinctrl_ndtr1_default: ndtr1_default {
978 pinctrl_ndtr2_default: ndtr2_default {
983 pinctrl_ndtr3_default: ndtr3_default {
988 pinctrl_ndtr4_default: ndtr4_default {
993 pinctrl_nri1_default: nri1_default {
998 pinctrl_nri2_default: nri2_default {
1003 pinctrl_nri3_default: nri3_default {
1008 pinctrl_nri4_default: nri4_default {
1013 pinctrl_nrts1_default: nrts1_default {
1018 pinctrl_nrts2_default: nrts2_default {
1023 pinctrl_nrts3_default: nrts3_default {
1028 pinctrl_nrts4_default: nrts4_default {
1033 pinctrl_oscclk_default: oscclk_default {
1034 function = "OSCCLK";
1038 pinctrl_pewake_default: pewake_default {
1039 function = "PEWAKE";
1043 pinctrl_pnor_default: pnor_default {
1048 pinctrl_pwm0_default: pwm0_default {
1053 pinctrl_pwm1_default: pwm1_default {
1058 pinctrl_pwm2_default: pwm2_default {
1063 pinctrl_pwm3_default: pwm3_default {
1068 pinctrl_pwm4_default: pwm4_default {
1073 pinctrl_pwm5_default: pwm5_default {
1078 pinctrl_pwm6_default: pwm6_default {
1083 pinctrl_pwm7_default: pwm7_default {
1088 pinctrl_rgmii1_default: rgmii1_default {
1089 function = "RGMII1";
1093 pinctrl_rgmii2_default: rgmii2_default {
1094 function = "RGMII2";
1098 pinctrl_rmii1_default: rmii1_default {
1103 pinctrl_rmii2_default: rmii2_default {
1108 pinctrl_rxd1_default: rxd1_default {
1113 pinctrl_rxd2_default: rxd2_default {
1118 pinctrl_rxd3_default: rxd3_default {
1123 pinctrl_rxd4_default: rxd4_default {
1128 pinctrl_salt1_default: salt1_default {
1133 pinctrl_salt10_default: salt10_default {
1134 function = "SALT10";
1138 pinctrl_salt11_default: salt11_default {
1139 function = "SALT11";
1143 pinctrl_salt12_default: salt12_default {
1144 function = "SALT12";
1148 pinctrl_salt13_default: salt13_default {
1149 function = "SALT13";
1153 pinctrl_salt14_default: salt14_default {
1154 function = "SALT14";
1158 pinctrl_salt2_default: salt2_default {
1163 pinctrl_salt3_default: salt3_default {
1168 pinctrl_salt4_default: salt4_default {
1173 pinctrl_salt5_default: salt5_default {
1178 pinctrl_salt6_default: salt6_default {
1183 pinctrl_salt7_default: salt7_default {
1188 pinctrl_salt8_default: salt8_default {
1193 pinctrl_salt9_default: salt9_default {
1198 pinctrl_scl1_default: scl1_default {
1203 pinctrl_scl2_default: scl2_default {
1208 pinctrl_sd1_default: sd1_default {
1213 pinctrl_sd2_default: sd2_default {
1218 pinctrl_sda1_default: sda1_default {
1223 pinctrl_sda2_default: sda2_default {
1228 pinctrl_sgps1_default: sgps1_default {
1233 pinctrl_sgps2_default: sgps2_default {
1238 pinctrl_sioonctrl_default: sioonctrl_default {
1239 function = "SIOONCTRL";
1240 groups = "SIOONCTRL";
1243 pinctrl_siopbi_default: siopbi_default {
1244 function = "SIOPBI";
1248 pinctrl_siopbo_default: siopbo_default {
1249 function = "SIOPBO";
1253 pinctrl_siopwreq_default: siopwreq_default {
1254 function = "SIOPWREQ";
1255 groups = "SIOPWREQ";
1258 pinctrl_siopwrgd_default: siopwrgd_default {
1259 function = "SIOPWRGD";
1260 groups = "SIOPWRGD";
1263 pinctrl_sios3_default: sios3_default {
1268 pinctrl_sios5_default: sios5_default {
1273 pinctrl_siosci_default: siosci_default {
1274 function = "SIOSCI";
1278 pinctrl_spi1_default: spi1_default {
1283 pinctrl_spi1cs1_default: spi1cs1_default {
1284 function = "SPI1CS1";
1288 pinctrl_spi1debug_default: spi1debug_default {
1289 function = "SPI1DEBUG";
1290 groups = "SPI1DEBUG";
1293 pinctrl_spi1passthru_default: spi1passthru_default {
1294 function = "SPI1PASSTHRU";
1295 groups = "SPI1PASSTHRU";
1298 pinctrl_spi2ck_default: spi2ck_default {
1299 function = "SPI2CK";
1303 pinctrl_spi2cs0_default: spi2cs0_default {
1304 function = "SPI2CS0";
1308 pinctrl_spi2cs1_default: spi2cs1_default {
1309 function = "SPI2CS1";
1313 pinctrl_spi2miso_default: spi2miso_default {
1314 function = "SPI2MISO";
1315 groups = "SPI2MISO";
1318 pinctrl_spi2mosi_default: spi2mosi_default {
1319 function = "SPI2MOSI";
1320 groups = "SPI2MOSI";
1323 pinctrl_timer3_default: timer3_default {
1324 function = "TIMER3";
1328 pinctrl_timer4_default: timer4_default {
1329 function = "TIMER4";
1333 pinctrl_timer5_default: timer5_default {
1334 function = "TIMER5";
1338 pinctrl_timer6_default: timer6_default {
1339 function = "TIMER6";
1343 pinctrl_timer7_default: timer7_default {
1344 function = "TIMER7";
1348 pinctrl_timer8_default: timer8_default {
1349 function = "TIMER8";
1353 pinctrl_txd1_default: txd1_default {
1358 pinctrl_txd2_default: txd2_default {
1363 pinctrl_txd3_default: txd3_default {
1368 pinctrl_txd4_default: txd4_default {
1373 pinctrl_uart6_default: uart6_default {
1378 pinctrl_usbcki_default: usbcki_default {
1379 function = "USBCKI";
1383 pinctrl_vgabiosrom_default: vgabiosrom_default {
1384 function = "VGABIOSROM";
1385 groups = "VGABIOSROM";
1388 pinctrl_vgahs_default: vgahs_default {
1393 pinctrl_vgavs_default: vgavs_default {
1398 pinctrl_vpi24_default: vpi24_default {
1403 pinctrl_vpo_default: vpo_default {
1408 pinctrl_wdtrst1_default: wdtrst1_default {
1409 function = "WDTRST1";
1413 pinctrl_wdtrst2_default: wdtrst2_default {
1414 function = "WDTRST2";