1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2500";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm1176jzf-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0xc4
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 compatible = "jedec,spi-nor";
77 compatible = "jedec,spi-nor";
82 spi1: flash-controller@1e630000 {
83 reg = < 0x1e630000 0xc4
84 0x30000000 0x08000000 >;
87 compatible = "aspeed,ast2500-spi";
88 clocks = <&syscon ASPEED_CLK_AHB>;
92 compatible = "jedec,spi-nor";
97 compatible = "jedec,spi-nor";
102 spi2: flash-controller@1e631000 {
103 reg = < 0x1e631000 0xc4
104 0x38000000 0x08000000 >;
105 #address-cells = <1>;
107 compatible = "aspeed,ast2500-spi";
108 clocks = <&syscon ASPEED_CLK_AHB>;
112 compatible = "jedec,spi-nor";
117 compatible = "jedec,spi-nor";
122 vic: interrupt-controller@1e6c0080 {
123 compatible = "aspeed,ast2400-vic";
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 valid-sources = <0xfefff7ff 0x0807ffff>;
127 reg = <0x1e6c0080 0x80>;
130 mac0: ethernet@1e660000 {
131 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
132 reg = <0x1e660000 0x180>;
134 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
138 mac1: ethernet@1e680000 {
139 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
140 reg = <0x1e680000 0x180>;
142 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
147 compatible = "simple-bus";
148 #address-cells = <1>;
152 syscon: syscon@1e6e2000 {
153 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
154 reg = <0x1e6e2000 0x1a8>;
155 #address-cells = <1>;
161 compatible = "aspeed,g5-pinctrl";
162 aspeed,external-nodes = <&gfx &lhc>;
167 gfx: display@1e6e6000 {
168 compatible = "aspeed,ast2500-gfx", "syscon";
169 reg = <0x1e6e6000 0x1000>;
174 compatible = "aspeed,ast2500-adc";
175 reg = <0x1e6e9000 0xb0>;
176 clocks = <&syscon ASPEED_CLK_APB>;
177 resets = <&syscon ASPEED_RESET_ADC>;
178 #io-channel-cells = <1>;
183 compatible = "mmio-sram";
184 reg = <0x1e720000 0x9000>; // 36K
187 gpio: gpio@1e780000 {
190 compatible = "aspeed,ast2500-gpio";
191 reg = <0x1e780000 0x1000>;
193 gpio-ranges = <&pinctrl 0 0 220>;
194 clocks = <&syscon ASPEED_CLK_APB>;
195 interrupt-controller;
198 timer: timer@1e782000 {
199 /* This timer is a Faraday FTTMR010 derivative */
200 compatible = "aspeed,ast2400-timer";
201 reg = <0x1e782000 0x90>;
202 interrupts = <16 17 18 35 36 37 38 39>;
203 clocks = <&syscon ASPEED_CLK_APB>;
204 clock-names = "PCLK";
207 uart1: serial@1e783000 {
208 compatible = "ns16550a";
209 reg = <0x1e783000 0x20>;
212 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
217 uart5: serial@1e784000 {
218 compatible = "ns16550a";
219 reg = <0x1e784000 0x20>;
222 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
227 wdt1: watchdog@1e785000 {
228 compatible = "aspeed,ast2500-wdt";
229 reg = <0x1e785000 0x20>;
230 clocks = <&syscon ASPEED_CLK_APB>;
233 wdt2: watchdog@1e785020 {
234 compatible = "aspeed,ast2500-wdt";
235 reg = <0x1e785020 0x20>;
236 clocks = <&syscon ASPEED_CLK_APB>;
239 wdt3: watchdog@1e785040 {
240 compatible = "aspeed,ast2500-wdt";
241 reg = <0x1e785040 0x20>;
242 clocks = <&syscon ASPEED_CLK_APB>;
246 pwm_tacho: pwm-tacho-controller@1e786000 {
247 compatible = "aspeed,ast2500-pwm-tacho";
248 #address-cells = <1>;
250 reg = <0x1e786000 0x1000>;
251 clocks = <&syscon ASPEED_CLK_APB>;
252 resets = <&syscon ASPEED_RESET_PWM>;
256 vuart: serial@1e787000 {
257 compatible = "aspeed,ast2500-vuart";
258 reg = <0x1e787000 0x40>;
261 clocks = <&syscon ASPEED_CLK_APB>;
267 compatible = "aspeed,ast2500-lpc", "simple-mfd";
268 reg = <0x1e789000 0x1000>;
270 #address-cells = <1>;
272 ranges = <0 0x1e789000 0x1000>;
275 compatible = "aspeed,ast2500-lpc-bmc";
279 lpc_host: lpc-host@80 {
280 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
283 #address-cells = <1>;
285 ranges = <0 0x80 0x1e0>;
289 lpc_ctrl: lpc-ctrl@0 {
290 compatible = "aspeed,ast2500-lpc-ctrl";
295 lpc_snoop: lpc-snoop@0 {
296 compatible = "aspeed,ast2500-lpc-snoop";
303 compatible = "aspeed,ast2500-lhc";
304 reg = <0x20 0x24 0x48 0x8>;
309 uart2: serial@1e78d000 {
310 compatible = "ns16550a";
311 reg = <0x1e78d000 0x20>;
314 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
319 uart3: serial@1e78e000 {
320 compatible = "ns16550a";
321 reg = <0x1e78e000 0x20>;
324 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
329 uart4: serial@1e78f000 {
330 compatible = "ns16550a";
331 reg = <0x1e78f000 0x20>;
334 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
340 compatible = "simple-bus";
341 #address-cells = <1>;
343 ranges = <0 0x1e78a000 0x1000>;
350 i2c_ic: interrupt-controller@0 {
351 #interrupt-cells = <1>;
352 compatible = "aspeed,ast2500-i2c-ic";
355 interrupt-controller;
359 #address-cells = <1>;
361 #interrupt-cells = <1>;
364 compatible = "aspeed,ast2500-i2c-bus";
365 clocks = <&syscon ASPEED_CLK_APB>;
366 resets = <&syscon ASPEED_RESET_I2C>;
367 bus-frequency = <100000>;
369 interrupt-parent = <&i2c_ic>;
371 /* Does not need pinctrl properties */
375 #address-cells = <1>;
377 #interrupt-cells = <1>;
380 compatible = "aspeed,ast2500-i2c-bus";
381 clocks = <&syscon ASPEED_CLK_APB>;
382 resets = <&syscon ASPEED_RESET_I2C>;
383 bus-frequency = <100000>;
385 interrupt-parent = <&i2c_ic>;
387 /* Does not need pinctrl properties */
391 #address-cells = <1>;
393 #interrupt-cells = <1>;
396 compatible = "aspeed,ast2500-i2c-bus";
397 clocks = <&syscon ASPEED_CLK_APB>;
398 resets = <&syscon ASPEED_RESET_I2C>;
399 bus-frequency = <100000>;
401 interrupt-parent = <&i2c_ic>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_i2c3_default>;
408 #address-cells = <1>;
410 #interrupt-cells = <1>;
413 compatible = "aspeed,ast2500-i2c-bus";
414 clocks = <&syscon ASPEED_CLK_APB>;
415 resets = <&syscon ASPEED_RESET_I2C>;
416 bus-frequency = <100000>;
418 interrupt-parent = <&i2c_ic>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_i2c4_default>;
425 #address-cells = <1>;
427 #interrupt-cells = <1>;
430 compatible = "aspeed,ast2500-i2c-bus";
431 clocks = <&syscon ASPEED_CLK_APB>;
432 resets = <&syscon ASPEED_RESET_I2C>;
433 bus-frequency = <100000>;
435 interrupt-parent = <&i2c_ic>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_i2c5_default>;
442 #address-cells = <1>;
444 #interrupt-cells = <1>;
447 compatible = "aspeed,ast2500-i2c-bus";
448 clocks = <&syscon ASPEED_CLK_APB>;
449 resets = <&syscon ASPEED_RESET_I2C>;
450 bus-frequency = <100000>;
452 interrupt-parent = <&i2c_ic>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_i2c6_default>;
459 #address-cells = <1>;
461 #interrupt-cells = <1>;
464 compatible = "aspeed,ast2500-i2c-bus";
465 clocks = <&syscon ASPEED_CLK_APB>;
466 resets = <&syscon ASPEED_RESET_I2C>;
467 bus-frequency = <100000>;
469 interrupt-parent = <&i2c_ic>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_i2c7_default>;
476 #address-cells = <1>;
478 #interrupt-cells = <1>;
481 compatible = "aspeed,ast2500-i2c-bus";
482 clocks = <&syscon ASPEED_CLK_APB>;
483 resets = <&syscon ASPEED_RESET_I2C>;
484 bus-frequency = <100000>;
486 interrupt-parent = <&i2c_ic>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_i2c8_default>;
493 #address-cells = <1>;
495 #interrupt-cells = <1>;
498 compatible = "aspeed,ast2500-i2c-bus";
499 clocks = <&syscon ASPEED_CLK_APB>;
500 resets = <&syscon ASPEED_RESET_I2C>;
501 bus-frequency = <100000>;
503 interrupt-parent = <&i2c_ic>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_i2c9_default>;
510 #address-cells = <1>;
512 #interrupt-cells = <1>;
515 compatible = "aspeed,ast2500-i2c-bus";
516 clocks = <&syscon ASPEED_CLK_APB>;
517 resets = <&syscon ASPEED_RESET_I2C>;
518 bus-frequency = <100000>;
520 interrupt-parent = <&i2c_ic>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_i2c10_default>;
527 #address-cells = <1>;
529 #interrupt-cells = <1>;
532 compatible = "aspeed,ast2500-i2c-bus";
533 clocks = <&syscon ASPEED_CLK_APB>;
534 resets = <&syscon ASPEED_RESET_I2C>;
535 bus-frequency = <100000>;
537 interrupt-parent = <&i2c_ic>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_i2c11_default>;
544 #address-cells = <1>;
546 #interrupt-cells = <1>;
549 compatible = "aspeed,ast2500-i2c-bus";
550 clocks = <&syscon ASPEED_CLK_APB>;
551 resets = <&syscon ASPEED_RESET_I2C>;
552 bus-frequency = <100000>;
554 interrupt-parent = <&i2c_ic>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_i2c12_default>;
561 #address-cells = <1>;
563 #interrupt-cells = <1>;
566 compatible = "aspeed,ast2500-i2c-bus";
567 clocks = <&syscon ASPEED_CLK_APB>;
568 resets = <&syscon ASPEED_RESET_I2C>;
569 bus-frequency = <100000>;
571 interrupt-parent = <&i2c_ic>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_i2c13_default>;
578 #address-cells = <1>;
580 #interrupt-cells = <1>;
583 compatible = "aspeed,ast2500-i2c-bus";
584 clocks = <&syscon ASPEED_CLK_APB>;
585 resets = <&syscon ASPEED_RESET_I2C>;
586 bus-frequency = <100000>;
588 interrupt-parent = <&i2c_ic>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_i2c14_default>;
596 pinctrl_acpi_default: acpi_default {
601 pinctrl_adc0_default: adc0_default {
606 pinctrl_adc1_default: adc1_default {
611 pinctrl_adc10_default: adc10_default {
616 pinctrl_adc11_default: adc11_default {
621 pinctrl_adc12_default: adc12_default {
626 pinctrl_adc13_default: adc13_default {
631 pinctrl_adc14_default: adc14_default {
636 pinctrl_adc15_default: adc15_default {
641 pinctrl_adc2_default: adc2_default {
646 pinctrl_adc3_default: adc3_default {
651 pinctrl_adc4_default: adc4_default {
656 pinctrl_adc5_default: adc5_default {
661 pinctrl_adc6_default: adc6_default {
666 pinctrl_adc7_default: adc7_default {
671 pinctrl_adc8_default: adc8_default {
676 pinctrl_adc9_default: adc9_default {
681 pinctrl_bmcint_default: bmcint_default {
686 pinctrl_ddcclk_default: ddcclk_default {
691 pinctrl_ddcdat_default: ddcdat_default {
696 pinctrl_espi_default: espi_default {
701 pinctrl_fwspics1_default: fwspics1_default {
702 function = "FWSPICS1";
706 pinctrl_fwspics2_default: fwspics2_default {
707 function = "FWSPICS2";
711 pinctrl_gpid0_default: gpid0_default {
716 pinctrl_gpid2_default: gpid2_default {
721 pinctrl_gpid4_default: gpid4_default {
726 pinctrl_gpid6_default: gpid6_default {
731 pinctrl_gpie0_default: gpie0_default {
736 pinctrl_gpie2_default: gpie2_default {
741 pinctrl_gpie4_default: gpie4_default {
746 pinctrl_gpie6_default: gpie6_default {
751 pinctrl_i2c10_default: i2c10_default {
756 pinctrl_i2c11_default: i2c11_default {
761 pinctrl_i2c12_default: i2c12_default {
766 pinctrl_i2c13_default: i2c13_default {
771 pinctrl_i2c14_default: i2c14_default {
776 pinctrl_i2c3_default: i2c3_default {
781 pinctrl_i2c4_default: i2c4_default {
786 pinctrl_i2c5_default: i2c5_default {
791 pinctrl_i2c6_default: i2c6_default {
796 pinctrl_i2c7_default: i2c7_default {
801 pinctrl_i2c8_default: i2c8_default {
806 pinctrl_i2c9_default: i2c9_default {
811 pinctrl_lad0_default: lad0_default {
816 pinctrl_lad1_default: lad1_default {
821 pinctrl_lad2_default: lad2_default {
826 pinctrl_lad3_default: lad3_default {
831 pinctrl_lclk_default: lclk_default {
836 pinctrl_lframe_default: lframe_default {
841 pinctrl_lpchc_default: lpchc_default {
846 pinctrl_lpcpd_default: lpcpd_default {
851 pinctrl_lpcplus_default: lpcplus_default {
852 function = "LPCPLUS";
856 pinctrl_lpcpme_default: lpcpme_default {
861 pinctrl_lpcrst_default: lpcrst_default {
866 pinctrl_lpcsmi_default: lpcsmi_default {
871 pinctrl_lsirq_default: lsirq_default {
876 pinctrl_mac1link_default: mac1link_default {
877 function = "MAC1LINK";
881 pinctrl_mac2link_default: mac2link_default {
882 function = "MAC2LINK";
886 pinctrl_mdio1_default: mdio1_default {
891 pinctrl_mdio2_default: mdio2_default {
896 pinctrl_ncts1_default: ncts1_default {
901 pinctrl_ncts2_default: ncts2_default {
906 pinctrl_ncts3_default: ncts3_default {
911 pinctrl_ncts4_default: ncts4_default {
916 pinctrl_ndcd1_default: ndcd1_default {
921 pinctrl_ndcd2_default: ndcd2_default {
926 pinctrl_ndcd3_default: ndcd3_default {
931 pinctrl_ndcd4_default: ndcd4_default {
936 pinctrl_ndsr1_default: ndsr1_default {
941 pinctrl_ndsr2_default: ndsr2_default {
946 pinctrl_ndsr3_default: ndsr3_default {
951 pinctrl_ndsr4_default: ndsr4_default {
956 pinctrl_ndtr1_default: ndtr1_default {
961 pinctrl_ndtr2_default: ndtr2_default {
966 pinctrl_ndtr3_default: ndtr3_default {
971 pinctrl_ndtr4_default: ndtr4_default {
976 pinctrl_nri1_default: nri1_default {
981 pinctrl_nri2_default: nri2_default {
986 pinctrl_nri3_default: nri3_default {
991 pinctrl_nri4_default: nri4_default {
996 pinctrl_nrts1_default: nrts1_default {
1001 pinctrl_nrts2_default: nrts2_default {
1006 pinctrl_nrts3_default: nrts3_default {
1011 pinctrl_nrts4_default: nrts4_default {
1016 pinctrl_oscclk_default: oscclk_default {
1017 function = "OSCCLK";
1021 pinctrl_pewake_default: pewake_default {
1022 function = "PEWAKE";
1026 pinctrl_pnor_default: pnor_default {
1031 pinctrl_pwm0_default: pwm0_default {
1036 pinctrl_pwm1_default: pwm1_default {
1041 pinctrl_pwm2_default: pwm2_default {
1046 pinctrl_pwm3_default: pwm3_default {
1051 pinctrl_pwm4_default: pwm4_default {
1056 pinctrl_pwm5_default: pwm5_default {
1061 pinctrl_pwm6_default: pwm6_default {
1066 pinctrl_pwm7_default: pwm7_default {
1071 pinctrl_rgmii1_default: rgmii1_default {
1072 function = "RGMII1";
1076 pinctrl_rgmii2_default: rgmii2_default {
1077 function = "RGMII2";
1081 pinctrl_rmii1_default: rmii1_default {
1086 pinctrl_rmii2_default: rmii2_default {
1091 pinctrl_rxd1_default: rxd1_default {
1096 pinctrl_rxd2_default: rxd2_default {
1101 pinctrl_rxd3_default: rxd3_default {
1106 pinctrl_rxd4_default: rxd4_default {
1111 pinctrl_salt1_default: salt1_default {
1116 pinctrl_salt10_default: salt10_default {
1117 function = "SALT10";
1121 pinctrl_salt11_default: salt11_default {
1122 function = "SALT11";
1126 pinctrl_salt12_default: salt12_default {
1127 function = "SALT12";
1131 pinctrl_salt13_default: salt13_default {
1132 function = "SALT13";
1136 pinctrl_salt14_default: salt14_default {
1137 function = "SALT14";
1141 pinctrl_salt2_default: salt2_default {
1146 pinctrl_salt3_default: salt3_default {
1151 pinctrl_salt4_default: salt4_default {
1156 pinctrl_salt5_default: salt5_default {
1161 pinctrl_salt6_default: salt6_default {
1166 pinctrl_salt7_default: salt7_default {
1171 pinctrl_salt8_default: salt8_default {
1176 pinctrl_salt9_default: salt9_default {
1181 pinctrl_scl1_default: scl1_default {
1186 pinctrl_scl2_default: scl2_default {
1191 pinctrl_sd1_default: sd1_default {
1196 pinctrl_sd2_default: sd2_default {
1201 pinctrl_sda1_default: sda1_default {
1206 pinctrl_sda2_default: sda2_default {
1211 pinctrl_sgps1_default: sgps1_default {
1216 pinctrl_sgps2_default: sgps2_default {
1221 pinctrl_sioonctrl_default: sioonctrl_default {
1222 function = "SIOONCTRL";
1223 groups = "SIOONCTRL";
1226 pinctrl_siopbi_default: siopbi_default {
1227 function = "SIOPBI";
1231 pinctrl_siopbo_default: siopbo_default {
1232 function = "SIOPBO";
1236 pinctrl_siopwreq_default: siopwreq_default {
1237 function = "SIOPWREQ";
1238 groups = "SIOPWREQ";
1241 pinctrl_siopwrgd_default: siopwrgd_default {
1242 function = "SIOPWRGD";
1243 groups = "SIOPWRGD";
1246 pinctrl_sios3_default: sios3_default {
1251 pinctrl_sios5_default: sios5_default {
1256 pinctrl_siosci_default: siosci_default {
1257 function = "SIOSCI";
1261 pinctrl_spi1_default: spi1_default {
1266 pinctrl_spi1cs1_default: spi1cs1_default {
1267 function = "SPI1CS1";
1271 pinctrl_spi1debug_default: spi1debug_default {
1272 function = "SPI1DEBUG";
1273 groups = "SPI1DEBUG";
1276 pinctrl_spi1passthru_default: spi1passthru_default {
1277 function = "SPI1PASSTHRU";
1278 groups = "SPI1PASSTHRU";
1281 pinctrl_spi2ck_default: spi2ck_default {
1282 function = "SPI2CK";
1286 pinctrl_spi2cs0_default: spi2cs0_default {
1287 function = "SPI2CS0";
1291 pinctrl_spi2cs1_default: spi2cs1_default {
1292 function = "SPI2CS1";
1296 pinctrl_spi2miso_default: spi2miso_default {
1297 function = "SPI2MISO";
1298 groups = "SPI2MISO";
1301 pinctrl_spi2mosi_default: spi2mosi_default {
1302 function = "SPI2MOSI";
1303 groups = "SPI2MOSI";
1306 pinctrl_timer3_default: timer3_default {
1307 function = "TIMER3";
1311 pinctrl_timer4_default: timer4_default {
1312 function = "TIMER4";
1316 pinctrl_timer5_default: timer5_default {
1317 function = "TIMER5";
1321 pinctrl_timer6_default: timer6_default {
1322 function = "TIMER6";
1326 pinctrl_timer7_default: timer7_default {
1327 function = "TIMER7";
1331 pinctrl_timer8_default: timer8_default {
1332 function = "TIMER8";
1336 pinctrl_txd1_default: txd1_default {
1341 pinctrl_txd2_default: txd2_default {
1346 pinctrl_txd3_default: txd3_default {
1351 pinctrl_txd4_default: txd4_default {
1356 pinctrl_uart6_default: uart6_default {
1361 pinctrl_usbcki_default: usbcki_default {
1362 function = "USBCKI";
1366 pinctrl_vgabiosrom_default: vgabiosrom_default {
1367 function = "VGABIOSROM";
1368 groups = "VGABIOSROM";
1371 pinctrl_vgahs_default: vgahs_default {
1376 pinctrl_vgavs_default: vgavs_default {
1381 pinctrl_vpi24_default: vpi24_default {
1386 pinctrl_vpo_default: vpo_default {
1391 pinctrl_wdtrst1_default: wdtrst1_default {
1392 function = "WDTRST1";
1396 pinctrl_wdtrst2_default: wdtrst2_default {
1397 function = "WDTRST2";