arch/arm/boot/dts/aspeed-g5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2500";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm1176jzf-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@80000000 {
  46                 device_type = "memory";
  47                 reg = <0x80000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: spi@1e620000 {
  57                         reg = < 0x1e620000 0xc4
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2500-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 spi-max-frequency = <50000000>;
  69                                 status = "disabled";
  70                         };
  71                         flash@1 {
  72                                 reg = < 1 >;
  73                                 compatible = "jedec,spi-nor";
  74                                 spi-max-frequency = <50000000>;
  75                                 status = "disabled";
  76                         };
  77                         flash@2 {
  78                                 reg = < 2 >;
  79                                 compatible = "jedec,spi-nor";
  80                                 spi-max-frequency = <50000000>;
  81                                 status = "disabled";
  82                         };
  83                 };
  84
  85                 spi1: spi@1e630000 {
  86                         reg = < 0x1e630000 0xc4
  87                                 0x30000000 0x08000000 >;
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90                         compatible = "aspeed,ast2500-spi";
  91                         clocks = <&syscon ASPEED_CLK_AHB>;
  92                         status = "disabled";
  93                         flash@0 {
  94                                 reg = < 0 >;
  95                                 compatible = "jedec,spi-nor";
  96                                 spi-max-frequency = <50000000>;
  97                                 status = "disabled";
  98                         };
  99                         flash@1 {
 100                                 reg = < 1 >;
 101                                 compatible = "jedec,spi-nor";
 102                                 spi-max-frequency = <50000000>;
 103                                 status = "disabled";
 104                         };
 105                 };
 106
 107                 spi2: spi@1e631000 {
 108                         reg = < 0x1e631000 0xc4
 109                                 0x38000000 0x08000000 >;
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         compatible = "aspeed,ast2500-spi";
 113                         clocks = <&syscon ASPEED_CLK_AHB>;
 114                         status = "disabled";
 115                         flash@0 {
 116                                 reg = < 0 >;
 117                                 compatible = "jedec,spi-nor";
 118                                 spi-max-frequency = <50000000>;
 119                                 status = "disabled";
 120                         };
 121                         flash@1 {
 122                                 reg = < 1 >;
 123                                 compatible = "jedec,spi-nor";
 124                                 spi-max-frequency = <50000000>;
 125                                 status = "disabled";
 126                         };
 127                 };
 128
 129                 vic: interrupt-controller@1e6c0080 {
 130                         compatible = "aspeed,ast2400-vic";
 131                         interrupt-controller;
 132                         #interrupt-cells = <1>;
 133                         valid-sources = <0xfefff7ff 0x0807ffff>;
 134                         reg = <0x1e6c0080 0x80>;
 135                 };
 136
 137                 cvic: copro-interrupt-controller@1e6c2000 {
 138                         compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
 139                         valid-sources = <0xffffffff>;
 140                         copro-sw-interrupts = <1>;
 141                         reg = <0x1e6c2000 0x80>;
 142                 };
 143
 144                 mac0: ethernet@1e660000 {
 145                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 146                         reg = <0x1e660000 0x180>;
 147                         interrupts = <2>;
 148                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 149                         status = "disabled";
 150                 };
 151
 152                 mac1: ethernet@1e680000 {
 153                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 154                         reg = <0x1e680000 0x180>;
 155                         interrupts = <3>;
 156                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 157                         status = "disabled";
 158                 };
 159
 160                 ehci0: usb@1e6a1000 {
 161                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 162                         reg = <0x1e6a1000 0x100>;
 163                         interrupts = <5>;
 164                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 165                         pinctrl-names = "default";
 166                         pinctrl-0 = <&pinctrl_usb2ah_default>;
 167                         status = "disabled";
 168                 };
 169
 170                 ehci1: usb@1e6a3000 {
 171                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 172                         reg = <0x1e6a3000 0x100>;
 173                         interrupts = <13>;
 174                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_usb2bh_default>;
 177                         status = "disabled";
 178                 };
 179
 180                 uhci: usb@1e6b0000 {
 181                         compatible = "aspeed,ast2500-uhci", "generic-uhci";
 182                         reg = <0x1e6b0000 0x100>;
 183                         interrupts = <14>;
 184                         #ports = <2>;
 185                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 186                         status = "disabled";
 187                         /*
 188                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 189                          * override if you don't enable EHCI
 190                          */
 191                 };
 192
 193                 vhub: usb-vhub@1e6a0000 {
 194                         compatible = "aspeed,ast2500-usb-vhub";
 195                         reg = <0x1e6a0000 0x300>;
 196                         interrupts = <5>;
 197                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 198                         aspeed,vhub-downstream-ports = <5>;
 199                         aspeed,vhub-generic-endpoints = <15>;
 200                         pinctrl-names = "default";
 201                         pinctrl-0 = <&pinctrl_usb2ad_default>;
 202                         status = "disabled";
 203                 };
 204
 205                 apb {
 206                         compatible = "simple-bus";
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209                         ranges;
 210
 211                         edac: memory-controller@1e6e0000 {
 212                                 compatible = "aspeed,ast2500-sdram-edac";
 213                                 reg = <0x1e6e0000 0x174>;
 214                                 interrupts = <0>;
 215                                 status = "disabled";
 216                         };
 217
 218                         syscon: syscon@1e6e2000 {
 219                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 220                                 reg = <0x1e6e2000 0x1a8>;
 221                                 #address-cells = <1>;
 222                                 #size-cells = <1>;
 223                                 ranges = <0 0x1e6e2000 0x1000>;
 224                                 #clock-cells = <1>;
 225                                 #reset-cells = <1>;
 226
 227                                 scu_ic: interrupt-controller@18 {
 228                                         #interrupt-cells = <1>;
 229                                         compatible = "aspeed,ast2500-scu-ic";
 230                                         reg = <0x18 0x4>;
 231                                         interrupts = <21>;
 232                                         interrupt-controller;
 233                                 };
 234
 235                                 p2a: p2a-control@2c {
 236                                         compatible = "aspeed,ast2500-p2a-ctrl";
 237                                         reg = <0x2c 0x4>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 pinctrl: pinctrl@80 {
 242                                         compatible = "aspeed,ast2500-pinctrl";
 243                                         reg = <0x80 0x18>, <0xa0 0x10>;
 244                                         aspeed,external-nodes = <&gfx>, <&lhc>;
 245                                 };
 246                         };
 247
 248                         rng: hwrng@1e6e2078 {
 249                                 compatible = "timeriomem_rng";
 250                                 reg = <0x1e6e2078 0x4>;
 251                                 period = <1>;
 252                                 quality = <100>;
 253                         };
 254
 255                         gfx: display@1e6e6000 {
 256                                 compatible = "aspeed,ast2500-gfx", "syscon";
 257                                 reg = <0x1e6e6000 0x1000>;
 258                                 reg-io-width = <4>;
 259                                 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
 260                                 resets = <&syscon ASPEED_RESET_CRT1>;
 261                                 status = "disabled";
 262                                 interrupts = <0x19>;
 263                         };
 264
 265                         xdma: xdma@1e6e7000 {
 266                                 compatible = "aspeed,ast2500-xdma";
 267                                 reg = <0x1e6e7000 0x100>;
 268                                 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
 269                                 resets = <&syscon ASPEED_RESET_XDMA>;
 270                                 interrupts-extended = <&vic 6>, <&scu_ic 2>;
 271                                 pcie-device = "bmc";
 272                                 aspeed,scu = <&syscon>;
 273                                 status = "disabled";
 274                         };
 275
 276                         adc: adc@1e6e9000 {
 277                                 compatible = "aspeed,ast2500-adc";
 278                                 reg = <0x1e6e9000 0xb0>;
 279                                 clocks = <&syscon ASPEED_CLK_APB>;
 280                                 resets = <&syscon ASPEED_RESET_ADC>;
 281                                 #io-channel-cells = <1>;
 282                                 status = "disabled";
 283                         };
 284
 285                         video: video@1e700000 {
 286                                 compatible = "aspeed,ast2500-video-engine";
 287                                 reg = <0x1e700000 0x1000>;
 288                                 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
 289                                          <&syscon ASPEED_CLK_GATE_ECLK>;
 290                                 clock-names = "vclk", "eclk";
 291                                 interrupts = <7>;
 292                                 status = "disabled";
 293                         };
 294
 295                         sram: sram@1e720000 {
 296                                 compatible = "mmio-sram";
 297                                 reg = <0x1e720000 0x9000>;      // 36K
 298                         };
 299
 300                         sdmmc: sd-controller@1e740000 {
 301                                 compatible = "aspeed,ast2500-sd-controller";
 302                                 reg = <0x1e740000 0x100>;
 303                                 #address-cells = <1>;
 304                                 #size-cells = <1>;
 305                                 ranges = <0 0x1e740000 0x10000>;
 306                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
 307                                 status = "disabled";
 308
 309                                 sdhci0: sdhci@100 {
 310                                         compatible = "aspeed,ast2500-sdhci";
 311                                         reg = <0x100 0x100>;
 312                                         interrupts = <26>;
 313                                         sdhci,auto-cmd12;
 314                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 315                                         status = "disabled";
 316                                 };
 317
 318                                 sdhci1: sdhci@200 {
 319                                         compatible = "aspeed,ast2500-sdhci";
 320                                         reg = <0x200 0x100>;
 321                                         interrupts = <26>;
 322                                         sdhci,auto-cmd12;
 323                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 324                                         status = "disabled";
 325                                 };
 326                         };
 327
 328                         gpio: gpio@1e780000 {
 329                                 #gpio-cells = <2>;
 330                                 gpio-controller;
 331                                 compatible = "aspeed,ast2500-gpio";
 332                                 reg = <0x1e780000 0x200>;
 333                                 interrupts = <20>;
 334                                 gpio-ranges = <&pinctrl 0 0 232>;
 335                                 clocks = <&syscon ASPEED_CLK_APB>;
 336                                 interrupt-controller;
 337                                 #interrupt-cells = <2>;
 338                         };
 339
 340                         sgpio: sgpio@1e780200 {
 341                                 #gpio-cells = <2>;
 342                                 compatible = "aspeed,ast2500-sgpio";
 343                                 gpio-controller;
 344                                 interrupts = <40>;
 345                                 reg = <0x1e780200 0x0100>;
 346                                 clocks = <&syscon ASPEED_CLK_APB>;
 347                                 interrupt-controller;
 348                                 ngpios = <8>;
 349                                 bus-frequency = <12000000>;
 350                                 pinctrl-names = "default";
 351                                 pinctrl-0 = <&pinctrl_sgpm_default>;
 352                                 status = "disabled";
 353                         };
 354
 355                         rtc: rtc@1e781000 {
 356                                 compatible = "aspeed,ast2500-rtc";
 357                                 reg = <0x1e781000 0x18>;
 358                                 status = "disabled";
 359                         };
 360
 361                         timer: timer@1e782000 {
 362                                 /* This timer is a Faraday FTTMR010 derivative */
 363                                 compatible = "aspeed,ast2400-timer";
 364                                 reg = <0x1e782000 0x90>;
 365                                 interrupts = <16 17 18 35 36 37 38 39>;
 366                                 clocks = <&syscon ASPEED_CLK_APB>;
 367                                 clock-names = "PCLK";
 368                         };
 369
 370                         uart1: serial@1e783000 {
 371                                 compatible = "ns16550a";
 372                                 reg = <0x1e783000 0x20>;
 373                                 reg-shift = <2>;
 374                                 interrupts = <9>;
 375                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 376                                 resets = <&lpc_reset 4>;
 377                                 no-loopback-test;
 378                                 status = "disabled";
 379                         };
 380
 381                         uart5: serial@1e784000 {
 382                                 compatible = "ns16550a";
 383                                 reg = <0x1e784000 0x20>;
 384                                 reg-shift = <2>;
 385                                 interrupts = <10>;
 386                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 387                                 no-loopback-test;
 388                                 status = "disabled";
 389                         };
 390
 391                         wdt1: watchdog@1e785000 {
 392                                 compatible = "aspeed,ast2500-wdt";
 393                                 reg = <0x1e785000 0x20>;
 394                                 clocks = <&syscon ASPEED_CLK_APB>;
 395                         };
 396
 397                         wdt2: watchdog@1e785020 {
 398                                 compatible = "aspeed,ast2500-wdt";
 399                                 reg = <0x1e785020 0x20>;
 400                                 clocks = <&syscon ASPEED_CLK_APB>;
 401                         };
 402
 403                         wdt3: watchdog@1e785040 {
 404                                 compatible = "aspeed,ast2500-wdt";
 405                                 reg = <0x1e785040 0x20>;
 406                                 clocks = <&syscon ASPEED_CLK_APB>;
 407                                 status = "disabled";
 408                         };
 409
 410                         pwm_tacho: pwm-tacho-controller@1e786000 {
 411                                 compatible = "aspeed,ast2500-pwm-tacho";
 412                                 #address-cells = <1>;
 413                                 #size-cells = <0>;
 414                                 reg = <0x1e786000 0x1000>;
 415                                 clocks = <&syscon ASPEED_CLK_24M>;
 416                                 resets = <&syscon ASPEED_RESET_PWM>;
 417                                 status = "disabled";
 418                         };
 419
 420                         vuart: serial@1e787000 {
 421                                 compatible = "aspeed,ast2500-vuart";
 422                                 reg = <0x1e787000 0x40>;
 423                                 reg-shift = <2>;
 424                                 interrupts = <8>;
 425                                 clocks = <&syscon ASPEED_CLK_APB>;
 426                                 no-loopback-test;
 427                                 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
 428                                 status = "disabled";
 429                         };
 430
 431                         lpc: lpc@1e789000 {
 432                                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 433                                 reg = <0x1e789000 0x1000>;
 434
 435                                 #address-cells = <1>;
 436                                 #size-cells = <1>;
 437                                 ranges = <0x0 0x1e789000 0x1000>;
 438
 439                                 lpc_bmc: lpc-bmc@0 {
 440                                         compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
 441                                         reg = <0x0 0x80>;
 442                                         reg-io-width = <4>;
 443
 444                                         #address-cells = <1>;
 445                                         #size-cells = <1>;
 446                                         ranges = <0x0 0x0 0x80>;
 447
 448                                         kcs1: kcs@24 {
 449                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 450                                                 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
 451                                                 interrupts = <8>;
 452                                                 status = "disabled";
 453                                         };
 454                                         kcs2: kcs@28 {
 455                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 456                                                 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
 457                                                 interrupts = <8>;
 458                                                 status = "disabled";
 459                                         };
 460                                         kcs3: kcs@2c {
 461                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 462                                                 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
 463                                                 interrupts = <8>;
 464                                                 status = "disabled";
 465                                         };
 466                                 };
 467
 468                                 lpc_host: lpc-host@80 {
 469                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 470                                         reg = <0x80 0x1e0>;
 471                                         reg-io-width = <4>;
 472
 473                                         #address-cells = <1>;
 474                                         #size-cells = <1>;
 475                                         ranges = <0x0 0x80 0x1e0>;
 476
 477                                         kcs4: kcs@94 {
 478                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 479                                                 reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
 480                                                 interrupts = <8>;
 481                                                 status = "disabled";
 482                                         };
 483
 484                                         lpc_ctrl: lpc-ctrl@0 {
 485                                                 compatible = "aspeed,ast2500-lpc-ctrl";
 486                                                 reg = <0x0 0x10>;
 487                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 488                                                 status = "disabled";
 489                                         };
 490
 491                                         lpc_snoop: lpc-snoop@10 {
 492                                                 compatible = "aspeed,ast2500-lpc-snoop";
 493                                                 reg = <0x10 0x8>;
 494                                                 interrupts = <8>;
 495                                                 status = "disabled";
 496                                         };
 497
 498                                         lpc_reset: reset-controller@18 {
 499                                                 compatible = "aspeed,ast2500-lpc-reset";
 500                                                 reg = <0x18 0x4>;
 501                                                 #reset-cells = <1>;
 502                                         };
 503
 504                                         lhc: lhc@20 {
 505                                                 compatible = "aspeed,ast2500-lhc";
 506                                                 reg = <0x20 0x24 0x48 0x8>;
 507                                         };
 508
 509
 510                                         ibt: ibt@c0 {
 511                                                 compatible = "aspeed,ast2500-ibt-bmc";
 512                                                 reg = <0xc0 0x18>;
 513                                                 interrupts = <8>;
 514                                                 status = "disabled";
 515                                         };
 516                                 };
 517                         };
 518
 519                         uart2: serial@1e78d000 {
 520                                 compatible = "ns16550a";
 521                                 reg = <0x1e78d000 0x20>;
 522                                 reg-shift = <2>;
 523                                 interrupts = <32>;
 524                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 525                                 resets = <&lpc_reset 5>;
 526                                 no-loopback-test;
 527                                 status = "disabled";
 528                         };
 529
 530                         uart3: serial@1e78e000 {
 531                                 compatible = "ns16550a";
 532                                 reg = <0x1e78e000 0x20>;
 533                                 reg-shift = <2>;
 534                                 interrupts = <33>;
 535                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 536                                 resets = <&lpc_reset 6>;
 537                                 no-loopback-test;
 538                                 status = "disabled";
 539                         };
 540
 541                         uart4: serial@1e78f000 {
 542                                 compatible = "ns16550a";
 543                                 reg = <0x1e78f000 0x20>;
 544                                 reg-shift = <2>;
 545                                 interrupts = <34>;
 546                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 547                                 resets = <&lpc_reset 7>;
 548                                 no-loopback-test;
 549                                 status = "disabled";
 550                         };
 551
 552                         i2c: bus@1e78a000 {
 553                                 compatible = "simple-bus";
 554                                 #address-cells = <1>;
 555                                 #size-cells = <1>;
 556                                 ranges = <0 0x1e78a000 0x1000>;
 557                         };
 558                 };
 559         };
 560 };
 561
 562 &i2c {
 563         i2c_ic: interrupt-controller@0 {
 564                 #interrupt-cells = <1>;
 565                 compatible = "aspeed,ast2500-i2c-ic";
 566                 reg = <0x0 0x40>;
 567                 interrupts = <12>;
 568                 interrupt-controller;
 569         };
 570
 571         i2c0: i2c-bus@40 {
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 #interrupt-cells = <1>;
 575
 576                 reg = <0x40 0x40>;
 577                 compatible = "aspeed,ast2500-i2c-bus";
 578                 clocks = <&syscon ASPEED_CLK_APB>;
 579                 resets = <&syscon ASPEED_RESET_I2C>;
 580                 bus-frequency = <100000>;
 581                 interrupts = <0>;
 582                 interrupt-parent = <&i2c_ic>;
 583                 status = "disabled";
 584                 /* Does not need pinctrl properties */
 585         };
 586
 587         i2c1: i2c-bus@80 {
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 #interrupt-cells = <1>;
 591
 592                 reg = <0x80 0x40>;
 593                 compatible = "aspeed,ast2500-i2c-bus";
 594                 clocks = <&syscon ASPEED_CLK_APB>;
 595                 resets = <&syscon ASPEED_RESET_I2C>;
 596                 bus-frequency = <100000>;
 597                 interrupts = <1>;
 598                 interrupt-parent = <&i2c_ic>;
 599                 status = "disabled";
 600                 /* Does not need pinctrl properties */
 601         };
 602
 603         i2c2: i2c-bus@c0 {
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 #interrupt-cells = <1>;
 607
 608                 reg = <0xc0 0x40>;
 609                 compatible = "aspeed,ast2500-i2c-bus";
 610                 clocks = <&syscon ASPEED_CLK_APB>;
 611                 resets = <&syscon ASPEED_RESET_I2C>;
 612                 bus-frequency = <100000>;
 613                 interrupts = <2>;
 614                 interrupt-parent = <&i2c_ic>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&pinctrl_i2c3_default>;
 617                 status = "disabled";
 618         };
 619
 620         i2c3: i2c-bus@100 {
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 #interrupt-cells = <1>;
 624
 625                 reg = <0x100 0x40>;
 626                 compatible = "aspeed,ast2500-i2c-bus";
 627                 clocks = <&syscon ASPEED_CLK_APB>;
 628                 resets = <&syscon ASPEED_RESET_I2C>;
 629                 bus-frequency = <100000>;
 630                 interrupts = <3>;
 631                 interrupt-parent = <&i2c_ic>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&pinctrl_i2c4_default>;
 634                 status = "disabled";
 635         };
 636
 637         i2c4: i2c-bus@140 {
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 #interrupt-cells = <1>;
 641
 642                 reg = <0x140 0x40>;
 643                 compatible = "aspeed,ast2500-i2c-bus";
 644                 clocks = <&syscon ASPEED_CLK_APB>;
 645                 resets = <&syscon ASPEED_RESET_I2C>;
 646                 bus-frequency = <100000>;
 647                 interrupts = <4>;
 648                 interrupt-parent = <&i2c_ic>;
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&pinctrl_i2c5_default>;
 651                 status = "disabled";
 652         };
 653
 654         i2c5: i2c-bus@180 {
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 #interrupt-cells = <1>;
 658
 659                 reg = <0x180 0x40>;
 660                 compatible = "aspeed,ast2500-i2c-bus";
 661                 clocks = <&syscon ASPEED_CLK_APB>;
 662                 resets = <&syscon ASPEED_RESET_I2C>;
 663                 bus-frequency = <100000>;
 664                 interrupts = <5>;
 665                 interrupt-parent = <&i2c_ic>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&pinctrl_i2c6_default>;
 668                 status = "disabled";
 669         };
 670
 671         i2c6: i2c-bus@1c0 {
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 #interrupt-cells = <1>;
 675
 676                 reg = <0x1c0 0x40>;
 677                 compatible = "aspeed,ast2500-i2c-bus";
 678                 clocks = <&syscon ASPEED_CLK_APB>;
 679                 resets = <&syscon ASPEED_RESET_I2C>;
 680                 bus-frequency = <100000>;
 681                 interrupts = <6>;
 682                 interrupt-parent = <&i2c_ic>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&pinctrl_i2c7_default>;
 685                 status = "disabled";
 686         };
 687
 688         i2c7: i2c-bus@300 {
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 #interrupt-cells = <1>;
 692
 693                 reg = <0x300 0x40>;
 694                 compatible = "aspeed,ast2500-i2c-bus";
 695                 clocks = <&syscon ASPEED_CLK_APB>;
 696                 resets = <&syscon ASPEED_RESET_I2C>;
 697                 bus-frequency = <100000>;
 698                 interrupts = <7>;
 699                 interrupt-parent = <&i2c_ic>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&pinctrl_i2c8_default>;
 702                 status = "disabled";
 703         };
 704
 705         i2c8: i2c-bus@340 {
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 #interrupt-cells = <1>;
 709
 710                 reg = <0x340 0x40>;
 711                 compatible = "aspeed,ast2500-i2c-bus";
 712                 clocks = <&syscon ASPEED_CLK_APB>;
 713                 resets = <&syscon ASPEED_RESET_I2C>;
 714                 bus-frequency = <100000>;
 715                 interrupts = <8>;
 716                 interrupt-parent = <&i2c_ic>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pinctrl_i2c9_default>;
 719                 status = "disabled";
 720         };
 721
 722         i2c9: i2c-bus@380 {
 723                 #address-cells = <1>;
 724                 #size-cells = <0>;
 725                 #interrupt-cells = <1>;
 726
 727                 reg = <0x380 0x40>;
 728                 compatible = "aspeed,ast2500-i2c-bus";
 729                 clocks = <&syscon ASPEED_CLK_APB>;
 730                 resets = <&syscon ASPEED_RESET_I2C>;
 731                 bus-frequency = <100000>;
 732                 interrupts = <9>;
 733                 interrupt-parent = <&i2c_ic>;
 734                 pinctrl-names = "default";
 735                 pinctrl-0 = <&pinctrl_i2c10_default>;
 736                 status = "disabled";
 737         };
 738
 739         i2c10: i2c-bus@3c0 {
 740                 #address-cells = <1>;
 741                 #size-cells = <0>;
 742                 #interrupt-cells = <1>;
 743
 744                 reg = <0x3c0 0x40>;
 745                 compatible = "aspeed,ast2500-i2c-bus";
 746                 clocks = <&syscon ASPEED_CLK_APB>;
 747                 resets = <&syscon ASPEED_RESET_I2C>;
 748                 bus-frequency = <100000>;
 749                 interrupts = <10>;
 750                 interrupt-parent = <&i2c_ic>;
 751                 pinctrl-names = "default";
 752                 pinctrl-0 = <&pinctrl_i2c11_default>;
 753                 status = "disabled";
 754         };
 755
 756         i2c11: i2c-bus@400 {
 757                 #address-cells = <1>;
 758                 #size-cells = <0>;
 759                 #interrupt-cells = <1>;
 760
 761                 reg = <0x400 0x40>;
 762                 compatible = "aspeed,ast2500-i2c-bus";
 763                 clocks = <&syscon ASPEED_CLK_APB>;
 764                 resets = <&syscon ASPEED_RESET_I2C>;
 765                 bus-frequency = <100000>;
 766                 interrupts = <11>;
 767                 interrupt-parent = <&i2c_ic>;
 768                 pinctrl-names = "default";
 769                 pinctrl-0 = <&pinctrl_i2c12_default>;
 770                 status = "disabled";
 771         };
 772
 773         i2c12: i2c-bus@440 {
 774                 #address-cells = <1>;
 775                 #size-cells = <0>;
 776                 #interrupt-cells = <1>;
 777
 778                 reg = <0x440 0x40>;
 779                 compatible = "aspeed,ast2500-i2c-bus";
 780                 clocks = <&syscon ASPEED_CLK_APB>;
 781                 resets = <&syscon ASPEED_RESET_I2C>;
 782                 bus-frequency = <100000>;
 783                 interrupts = <12>;
 784                 interrupt-parent = <&i2c_ic>;
 785                 pinctrl-names = "default";
 786                 pinctrl-0 = <&pinctrl_i2c13_default>;
 787                 status = "disabled";
 788         };
 789
 790         i2c13: i2c-bus@480 {
 791                 #address-cells = <1>;
 792                 #size-cells = <0>;
 793                 #interrupt-cells = <1>;
 794
 795                 reg = <0x480 0x40>;
 796                 compatible = "aspeed,ast2500-i2c-bus";
 797                 clocks = <&syscon ASPEED_CLK_APB>;
 798                 resets = <&syscon ASPEED_RESET_I2C>;
 799                 bus-frequency = <100000>;
 800                 interrupts = <13>;
 801                 interrupt-parent = <&i2c_ic>;
 802                 pinctrl-names = "default";
 803                 pinctrl-0 = <&pinctrl_i2c14_default>;
 804                 status = "disabled";
 805         };
 806 };
 807
 808 &pinctrl {
 809         pinctrl_acpi_default: acpi_default {
 810                 function = "ACPI";
 811                 groups = "ACPI";
 812         };
 813
 814         pinctrl_adc0_default: adc0_default {
 815                 function = "ADC0";
 816                 groups = "ADC0";
 817         };
 818
 819         pinctrl_adc1_default: adc1_default {
 820                 function = "ADC1";
 821                 groups = "ADC1";
 822         };
 823
 824         pinctrl_adc10_default: adc10_default {
 825                 function = "ADC10";
 826                 groups = "ADC10";
 827         };
 828
 829         pinctrl_adc11_default: adc11_default {
 830                 function = "ADC11";
 831                 groups = "ADC11";
 832         };
 833
 834         pinctrl_adc12_default: adc12_default {
 835                 function = "ADC12";
 836                 groups = "ADC12";
 837         };
 838
 839         pinctrl_adc13_default: adc13_default {
 840                 function = "ADC13";
 841                 groups = "ADC13";
 842         };
 843
 844         pinctrl_adc14_default: adc14_default {
 845                 function = "ADC14";
 846                 groups = "ADC14";
 847         };
 848
 849         pinctrl_adc15_default: adc15_default {
 850                 function = "ADC15";
 851                 groups = "ADC15";
 852         };
 853
 854         pinctrl_adc2_default: adc2_default {
 855                 function = "ADC2";
 856                 groups = "ADC2";
 857         };
 858
 859         pinctrl_adc3_default: adc3_default {
 860                 function = "ADC3";
 861                 groups = "ADC3";
 862         };
 863
 864         pinctrl_adc4_default: adc4_default {
 865                 function = "ADC4";
 866                 groups = "ADC4";
 867         };
 868
 869         pinctrl_adc5_default: adc5_default {
 870                 function = "ADC5";
 871                 groups = "ADC5";
 872         };
 873
 874         pinctrl_adc6_default: adc6_default {
 875                 function = "ADC6";
 876                 groups = "ADC6";
 877         };
 878
 879         pinctrl_adc7_default: adc7_default {
 880                 function = "ADC7";
 881                 groups = "ADC7";
 882         };
 883
 884         pinctrl_adc8_default: adc8_default {
 885                 function = "ADC8";
 886                 groups = "ADC8";
 887         };
 888
 889         pinctrl_adc9_default: adc9_default {
 890                 function = "ADC9";
 891                 groups = "ADC9";
 892         };
 893
 894         pinctrl_bmcint_default: bmcint_default {
 895                 function = "BMCINT";
 896                 groups = "BMCINT";
 897         };
 898
 899         pinctrl_ddcclk_default: ddcclk_default {
 900                 function = "DDCCLK";
 901                 groups = "DDCCLK";
 902         };
 903
 904         pinctrl_ddcdat_default: ddcdat_default {
 905                 function = "DDCDAT";
 906                 groups = "DDCDAT";
 907         };
 908
 909         pinctrl_espi_default: espi_default {
 910                 function = "ESPI";
 911                 groups = "ESPI";
 912         };
 913
 914         pinctrl_fwspics1_default: fwspics1_default {
 915                 function = "FWSPICS1";
 916                 groups = "FWSPICS1";
 917         };
 918
 919         pinctrl_fwspics2_default: fwspics2_default {
 920                 function = "FWSPICS2";
 921                 groups = "FWSPICS2";
 922         };
 923
 924         pinctrl_gpid0_default: gpid0_default {
 925                 function = "GPID0";
 926                 groups = "GPID0";
 927         };
 928
 929         pinctrl_gpid2_default: gpid2_default {
 930                 function = "GPID2";
 931                 groups = "GPID2";
 932         };
 933
 934         pinctrl_gpid4_default: gpid4_default {
 935                 function = "GPID4";
 936                 groups = "GPID4";
 937         };
 938
 939         pinctrl_gpid6_default: gpid6_default {
 940                 function = "GPID6";
 941                 groups = "GPID6";
 942         };
 943
 944         pinctrl_gpie0_default: gpie0_default {
 945                 function = "GPIE0";
 946                 groups = "GPIE0";
 947         };
 948
 949         pinctrl_gpie2_default: gpie2_default {
 950                 function = "GPIE2";
 951                 groups = "GPIE2";
 952         };
 953
 954         pinctrl_gpie4_default: gpie4_default {
 955                 function = "GPIE4";
 956                 groups = "GPIE4";
 957         };
 958
 959         pinctrl_gpie6_default: gpie6_default {
 960                 function = "GPIE6";
 961                 groups = "GPIE6";
 962         };
 963
 964         pinctrl_i2c10_default: i2c10_default {
 965                 function = "I2C10";
 966                 groups = "I2C10";
 967         };
 968
 969         pinctrl_i2c11_default: i2c11_default {
 970                 function = "I2C11";
 971                 groups = "I2C11";
 972         };
 973
 974         pinctrl_i2c12_default: i2c12_default {
 975                 function = "I2C12";
 976                 groups = "I2C12";
 977         };
 978
 979         pinctrl_i2c13_default: i2c13_default {
 980                 function = "I2C13";
 981                 groups = "I2C13";
 982         };
 983
 984         pinctrl_i2c14_default: i2c14_default {
 985                 function = "I2C14";
 986                 groups = "I2C14";
 987         };
 988
 989         pinctrl_i2c3_default: i2c3_default {
 990                 function = "I2C3";
 991                 groups = "I2C3";
 992         };
 993
 994         pinctrl_i2c4_default: i2c4_default {
 995                 function = "I2C4";
 996                 groups = "I2C4";
 997         };
 998
 999         pinctrl_i2c5_default: i2c5_default {
1000                 function = "I2C5";
1001                 groups = "I2C5";
1002         };
1003
1004         pinctrl_i2c6_default: i2c6_default {
1005                 function = "I2C6";
1006                 groups = "I2C6";
1007         };
1008
1009         pinctrl_i2c7_default: i2c7_default {
1010                 function = "I2C7";
1011                 groups = "I2C7";
1012         };
1013
1014         pinctrl_i2c8_default: i2c8_default {
1015                 function = "I2C8";
1016                 groups = "I2C8";
1017         };
1018
1019         pinctrl_i2c9_default: i2c9_default {
1020                 function = "I2C9";
1021                 groups = "I2C9";
1022         };
1023
1024         pinctrl_lad0_default: lad0_default {
1025                 function = "LAD0";
1026                 groups = "LAD0";
1027         };
1028
1029         pinctrl_lad1_default: lad1_default {
1030                 function = "LAD1";
1031                 groups = "LAD1";
1032         };
1033
1034         pinctrl_lad2_default: lad2_default {
1035                 function = "LAD2";
1036                 groups = "LAD2";
1037         };
1038
1039         pinctrl_lad3_default: lad3_default {
1040                 function = "LAD3";
1041                 groups = "LAD3";
1042         };
1043
1044         pinctrl_lclk_default: lclk_default {
1045                 function = "LCLK";
1046                 groups = "LCLK";
1047         };
1048
1049         pinctrl_lframe_default: lframe_default {
1050                 function = "LFRAME";
1051                 groups = "LFRAME";
1052         };
1053
1054         pinctrl_lpchc_default: lpchc_default {
1055                 function = "LPCHC";
1056                 groups = "LPCHC";
1057         };
1058
1059         pinctrl_lpcpd_default: lpcpd_default {
1060                 function = "LPCPD";
1061                 groups = "LPCPD";
1062         };
1063
1064         pinctrl_lpcplus_default: lpcplus_default {
1065                 function = "LPCPLUS";
1066                 groups = "LPCPLUS";
1067         };
1068
1069         pinctrl_lpcpme_default: lpcpme_default {
1070                 function = "LPCPME";
1071                 groups = "LPCPME";
1072         };
1073
1074         pinctrl_lpcrst_default: lpcrst_default {
1075                 function = "LPCRST";
1076                 groups = "LPCRST";
1077         };
1078
1079         pinctrl_lpcsmi_default: lpcsmi_default {
1080                 function = "LPCSMI";
1081                 groups = "LPCSMI";
1082         };
1083
1084         pinctrl_lsirq_default: lsirq_default {
1085                 function = "LSIRQ";
1086                 groups = "LSIRQ";
1087         };
1088
1089         pinctrl_mac1link_default: mac1link_default {
1090                 function = "MAC1LINK";
1091                 groups = "MAC1LINK";
1092         };
1093
1094         pinctrl_mac2link_default: mac2link_default {
1095                 function = "MAC2LINK";
1096                 groups = "MAC2LINK";
1097         };
1098
1099         pinctrl_mdio1_default: mdio1_default {
1100                 function = "MDIO1";
1101                 groups = "MDIO1";
1102         };
1103
1104         pinctrl_mdio2_default: mdio2_default {
1105                 function = "MDIO2";
1106                 groups = "MDIO2";
1107         };
1108
1109         pinctrl_ncts1_default: ncts1_default {
1110                 function = "NCTS1";
1111                 groups = "NCTS1";
1112         };
1113
1114         pinctrl_ncts2_default: ncts2_default {
1115                 function = "NCTS2";
1116                 groups = "NCTS2";
1117         };
1118
1119         pinctrl_ncts3_default: ncts3_default {
1120                 function = "NCTS3";
1121                 groups = "NCTS3";
1122         };
1123
1124         pinctrl_ncts4_default: ncts4_default {
1125                 function = "NCTS4";
1126                 groups = "NCTS4";
1127         };
1128
1129         pinctrl_ndcd1_default: ndcd1_default {
1130                 function = "NDCD1";
1131                 groups = "NDCD1";
1132         };
1133
1134         pinctrl_ndcd2_default: ndcd2_default {
1135                 function = "NDCD2";
1136                 groups = "NDCD2";
1137         };
1138
1139         pinctrl_ndcd3_default: ndcd3_default {
1140                 function = "NDCD3";
1141                 groups = "NDCD3";
1142         };
1143
1144         pinctrl_ndcd4_default: ndcd4_default {
1145                 function = "NDCD4";
1146                 groups = "NDCD4";
1147         };
1148
1149         pinctrl_ndsr1_default: ndsr1_default {
1150                 function = "NDSR1";
1151                 groups = "NDSR1";
1152         };
1153
1154         pinctrl_ndsr2_default: ndsr2_default {
1155                 function = "NDSR2";
1156                 groups = "NDSR2";
1157         };
1158
1159         pinctrl_ndsr3_default: ndsr3_default {
1160                 function = "NDSR3";
1161                 groups = "NDSR3";
1162         };
1163
1164         pinctrl_ndsr4_default: ndsr4_default {
1165                 function = "NDSR4";
1166                 groups = "NDSR4";
1167         };
1168
1169         pinctrl_ndtr1_default: ndtr1_default {
1170                 function = "NDTR1";
1171                 groups = "NDTR1";
1172         };
1173
1174         pinctrl_ndtr2_default: ndtr2_default {
1175                 function = "NDTR2";
1176                 groups = "NDTR2";
1177         };
1178
1179         pinctrl_ndtr3_default: ndtr3_default {
1180                 function = "NDTR3";
1181                 groups = "NDTR3";
1182         };
1183
1184         pinctrl_ndtr4_default: ndtr4_default {
1185                 function = "NDTR4";
1186                 groups = "NDTR4";
1187         };
1188
1189         pinctrl_nri1_default: nri1_default {
1190                 function = "NRI1";
1191                 groups = "NRI1";
1192         };
1193
1194         pinctrl_nri2_default: nri2_default {
1195                 function = "NRI2";
1196                 groups = "NRI2";
1197         };
1198
1199         pinctrl_nri3_default: nri3_default {
1200                 function = "NRI3";
1201                 groups = "NRI3";
1202         };
1203
1204         pinctrl_nri4_default: nri4_default {
1205                 function = "NRI4";
1206                 groups = "NRI4";
1207         };
1208
1209         pinctrl_nrts1_default: nrts1_default {
1210                 function = "NRTS1";
1211                 groups = "NRTS1";
1212         };
1213
1214         pinctrl_nrts2_default: nrts2_default {
1215                 function = "NRTS2";
1216                 groups = "NRTS2";
1217         };
1218
1219         pinctrl_nrts3_default: nrts3_default {
1220                 function = "NRTS3";
1221                 groups = "NRTS3";
1222         };
1223
1224         pinctrl_nrts4_default: nrts4_default {
1225                 function = "NRTS4";
1226                 groups = "NRTS4";
1227         };
1228
1229         pinctrl_oscclk_default: oscclk_default {
1230                 function = "OSCCLK";
1231                 groups = "OSCCLK";
1232         };
1233
1234         pinctrl_pewake_default: pewake_default {
1235                 function = "PEWAKE";
1236                 groups = "PEWAKE";
1237         };
1238
1239         pinctrl_pnor_default: pnor_default {
1240                 function = "PNOR";
1241                 groups = "PNOR";
1242         };
1243
1244         pinctrl_pwm0_default: pwm0_default {
1245                 function = "PWM0";
1246                 groups = "PWM0";
1247         };
1248
1249         pinctrl_pwm1_default: pwm1_default {
1250                 function = "PWM1";
1251                 groups = "PWM1";
1252         };
1253
1254         pinctrl_pwm2_default: pwm2_default {
1255                 function = "PWM2";
1256                 groups = "PWM2";
1257         };
1258
1259         pinctrl_pwm3_default: pwm3_default {
1260                 function = "PWM3";
1261                 groups = "PWM3";
1262         };
1263
1264         pinctrl_pwm4_default: pwm4_default {
1265                 function = "PWM4";
1266                 groups = "PWM4";
1267         };
1268
1269         pinctrl_pwm5_default: pwm5_default {
1270                 function = "PWM5";
1271                 groups = "PWM5";
1272         };
1273
1274         pinctrl_pwm6_default: pwm6_default {
1275                 function = "PWM6";
1276                 groups = "PWM6";
1277         };
1278
1279         pinctrl_pwm7_default: pwm7_default {
1280                 function = "PWM7";
1281                 groups = "PWM7";
1282         };
1283
1284         pinctrl_rgmii1_default: rgmii1_default {
1285                 function = "RGMII1";
1286                 groups = "RGMII1";
1287         };
1288
1289         pinctrl_rgmii2_default: rgmii2_default {
1290                 function = "RGMII2";
1291                 groups = "RGMII2";
1292         };
1293
1294         pinctrl_rmii1_default: rmii1_default {
1295                 function = "RMII1";
1296                 groups = "RMII1";
1297         };
1298
1299         pinctrl_rmii2_default: rmii2_default {
1300                 function = "RMII2";
1301                 groups = "RMII2";
1302         };
1303
1304         pinctrl_rxd1_default: rxd1_default {
1305                 function = "RXD1";
1306                 groups = "RXD1";
1307         };
1308
1309         pinctrl_rxd2_default: rxd2_default {
1310                 function = "RXD2";
1311                 groups = "RXD2";
1312         };
1313
1314         pinctrl_rxd3_default: rxd3_default {
1315                 function = "RXD3";
1316                 groups = "RXD3";
1317         };
1318
1319         pinctrl_rxd4_default: rxd4_default {
1320                 function = "RXD4";
1321                 groups = "RXD4";
1322         };
1323
1324         pinctrl_salt1_default: salt1_default {
1325                 function = "SALT1";
1326                 groups = "SALT1";
1327         };
1328
1329         pinctrl_salt10_default: salt10_default {
1330                 function = "SALT10";
1331                 groups = "SALT10";
1332         };
1333
1334         pinctrl_salt11_default: salt11_default {
1335                 function = "SALT11";
1336                 groups = "SALT11";
1337         };
1338
1339         pinctrl_salt12_default: salt12_default {
1340                 function = "SALT12";
1341                 groups = "SALT12";
1342         };
1343
1344         pinctrl_salt13_default: salt13_default {
1345                 function = "SALT13";
1346                 groups = "SALT13";
1347         };
1348
1349         pinctrl_salt14_default: salt14_default {
1350                 function = "SALT14";
1351                 groups = "SALT14";
1352         };
1353
1354         pinctrl_salt2_default: salt2_default {
1355                 function = "SALT2";
1356                 groups = "SALT2";
1357         };
1358
1359         pinctrl_salt3_default: salt3_default {
1360                 function = "SALT3";
1361                 groups = "SALT3";
1362         };
1363
1364         pinctrl_salt4_default: salt4_default {
1365                 function = "SALT4";
1366                 groups = "SALT4";
1367         };
1368
1369         pinctrl_salt5_default: salt5_default {
1370                 function = "SALT5";
1371                 groups = "SALT5";
1372         };
1373
1374         pinctrl_salt6_default: salt6_default {
1375                 function = "SALT6";
1376                 groups = "SALT6";
1377         };
1378
1379         pinctrl_salt7_default: salt7_default {
1380                 function = "SALT7";
1381                 groups = "SALT7";
1382         };
1383
1384         pinctrl_salt8_default: salt8_default {
1385                 function = "SALT8";
1386                 groups = "SALT8";
1387         };
1388
1389         pinctrl_salt9_default: salt9_default {
1390                 function = "SALT9";
1391                 groups = "SALT9";
1392         };
1393
1394         pinctrl_scl1_default: scl1_default {
1395                 function = "SCL1";
1396                 groups = "SCL1";
1397         };
1398
1399         pinctrl_scl2_default: scl2_default {
1400                 function = "SCL2";
1401                 groups = "SCL2";
1402         };
1403
1404         pinctrl_sd1_default: sd1_default {
1405                 function = "SD1";
1406                 groups = "SD1";
1407         };
1408
1409         pinctrl_sd2_default: sd2_default {
1410                 function = "SD2";
1411                 groups = "SD2";
1412         };
1413
1414         pinctrl_sda1_default: sda1_default {
1415                 function = "SDA1";
1416                 groups = "SDA1";
1417         };
1418
1419         pinctrl_sda2_default: sda2_default {
1420                 function = "SDA2";
1421                 groups = "SDA2";
1422         };
1423
1424         pinctrl_sgpm_default: sgpm_default {
1425                 function = "SGPM";
1426                 groups = "SGPM";
1427         };
1428
1429         pinctrl_sgps1_default: sgps1_default {
1430                 function = "SGPS1";
1431                 groups = "SGPS1";
1432         };
1433
1434         pinctrl_sgps2_default: sgps2_default {
1435                 function = "SGPS2";
1436                 groups = "SGPS2";
1437         };
1438
1439         pinctrl_sioonctrl_default: sioonctrl_default {
1440                 function = "SIOONCTRL";
1441                 groups = "SIOONCTRL";
1442         };
1443
1444         pinctrl_siopbi_default: siopbi_default {
1445                 function = "SIOPBI";
1446                 groups = "SIOPBI";
1447         };
1448
1449         pinctrl_siopbo_default: siopbo_default {
1450                 function = "SIOPBO";
1451                 groups = "SIOPBO";
1452         };
1453
1454         pinctrl_siopwreq_default: siopwreq_default {
1455                 function = "SIOPWREQ";
1456                 groups = "SIOPWREQ";
1457         };
1458
1459         pinctrl_siopwrgd_default: siopwrgd_default {
1460                 function = "SIOPWRGD";
1461                 groups = "SIOPWRGD";
1462         };
1463
1464         pinctrl_sios3_default: sios3_default {
1465                 function = "SIOS3";
1466                 groups = "SIOS3";
1467         };
1468
1469         pinctrl_sios5_default: sios5_default {
1470                 function = "SIOS5";
1471                 groups = "SIOS5";
1472         };
1473
1474         pinctrl_siosci_default: siosci_default {
1475                 function = "SIOSCI";
1476                 groups = "SIOSCI";
1477         };
1478
1479         pinctrl_spi1_default: spi1_default {
1480                 function = "SPI1";
1481                 groups = "SPI1";
1482         };
1483
1484         pinctrl_spi1cs1_default: spi1cs1_default {
1485                 function = "SPI1CS1";
1486                 groups = "SPI1CS1";
1487         };
1488
1489         pinctrl_spi1debug_default: spi1debug_default {
1490                 function = "SPI1DEBUG";
1491                 groups = "SPI1DEBUG";
1492         };
1493
1494         pinctrl_spi1passthru_default: spi1passthru_default {
1495                 function = "SPI1PASSTHRU";
1496                 groups = "SPI1PASSTHRU";
1497         };
1498
1499         pinctrl_spi2ck_default: spi2ck_default {
1500                 function = "SPI2CK";
1501                 groups = "SPI2CK";
1502         };
1503
1504         pinctrl_spi2cs0_default: spi2cs0_default {
1505                 function = "SPI2CS0";
1506                 groups = "SPI2CS0";
1507         };
1508
1509         pinctrl_spi2cs1_default: spi2cs1_default {
1510                 function = "SPI2CS1";
1511                 groups = "SPI2CS1";
1512         };
1513
1514         pinctrl_spi2miso_default: spi2miso_default {
1515                 function = "SPI2MISO";
1516                 groups = "SPI2MISO";
1517         };
1518
1519         pinctrl_spi2mosi_default: spi2mosi_default {
1520                 function = "SPI2MOSI";
1521                 groups = "SPI2MOSI";
1522         };
1523
1524         pinctrl_timer3_default: timer3_default {
1525                 function = "TIMER3";
1526                 groups = "TIMER3";
1527         };
1528
1529         pinctrl_timer4_default: timer4_default {
1530                 function = "TIMER4";
1531                 groups = "TIMER4";
1532         };
1533
1534         pinctrl_timer5_default: timer5_default {
1535                 function = "TIMER5";
1536                 groups = "TIMER5";
1537         };
1538
1539         pinctrl_timer6_default: timer6_default {
1540                 function = "TIMER6";
1541                 groups = "TIMER6";
1542         };
1543
1544         pinctrl_timer7_default: timer7_default {
1545                 function = "TIMER7";
1546                 groups = "TIMER7";
1547         };
1548
1549         pinctrl_timer8_default: timer8_default {
1550                 function = "TIMER8";
1551                 groups = "TIMER8";
1552         };
1553
1554         pinctrl_txd1_default: txd1_default {
1555                 function = "TXD1";
1556                 groups = "TXD1";
1557         };
1558
1559         pinctrl_txd2_default: txd2_default {
1560                 function = "TXD2";
1561                 groups = "TXD2";
1562         };
1563
1564         pinctrl_txd3_default: txd3_default {
1565                 function = "TXD3";
1566                 groups = "TXD3";
1567         };
1568
1569         pinctrl_txd4_default: txd4_default {
1570                 function = "TXD4";
1571                 groups = "TXD4";
1572         };
1573
1574         pinctrl_uart6_default: uart6_default {
1575                 function = "UART6";
1576                 groups = "UART6";
1577         };
1578
1579         pinctrl_usbcki_default: usbcki_default {
1580                 function = "USBCKI";
1581                 groups = "USBCKI";
1582         };
1583
1584         pinctrl_usb2ah_default: usb2ah_default {
1585                 function = "USB2AH";
1586                 groups = "USB2AH";
1587         };
1588
1589         pinctrl_usb2ad_default: usb2ad_default {
1590                 function = "USB2AD";
1591                 groups = "USB2AD";
1592         };
1593
1594         pinctrl_usb11bhid_default: usb11bhid_default {
1595                 function = "USB11BHID";
1596                 groups = "USB11BHID";
1597         };
1598
1599         pinctrl_usb2bh_default: usb2bh_default {
1600                 function = "USB2BH";
1601                 groups = "USB2BH";
1602         };
1603
1604         pinctrl_vgabiosrom_default: vgabiosrom_default {
1605                 function = "VGABIOSROM";
1606                 groups = "VGABIOSROM";
1607         };
1608
1609         pinctrl_vgahs_default: vgahs_default {
1610                 function = "VGAHS";
1611                 groups = "VGAHS";
1612         };
1613
1614         pinctrl_vgavs_default: vgavs_default {
1615                 function = "VGAVS";
1616                 groups = "VGAVS";
1617         };
1618
1619         pinctrl_vpi24_default: vpi24_default {
1620                 function = "VPI24";
1621                 groups = "VPI24";
1622         };
1623
1624         pinctrl_vpo_default: vpo_default {
1625                 function = "VPO";
1626                 groups = "VPO";
1627         };
1628
1629         pinctrl_wdtrst1_default: wdtrst1_default {
1630                 function = "WDTRST1";
1631                 groups = "WDTRST1";
1632         };
1633
1634         pinctrl_wdtrst2_default: wdtrst2_default {
1635                 function = "WDTRST2";
1636                 groups = "WDTRST2";
1637         };
1638 };