1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
7 compatible = "aspeed,ast2500";
10 interrupt-parent = <&vic>;
40 compatible = "arm,arm1176jzf-s";
47 device_type = "memory";
52 compatible = "simple-bus";
58 reg = < 0x1e620000 0xc4
59 0x20000000 0x10000000 >;
62 compatible = "aspeed,ast2500-fmc";
63 clocks = <&syscon ASPEED_CLK_AHB>;
68 compatible = "jedec,spi-nor";
69 spi-max-frequency = <50000000>;
74 compatible = "jedec,spi-nor";
75 spi-max-frequency = <50000000>;
80 compatible = "jedec,spi-nor";
81 spi-max-frequency = <50000000>;
87 reg = < 0x1e630000 0xc4
88 0x30000000 0x08000000 >;
91 compatible = "aspeed,ast2500-spi";
92 clocks = <&syscon ASPEED_CLK_AHB>;
96 compatible = "jedec,spi-nor";
97 spi-max-frequency = <50000000>;
102 compatible = "jedec,spi-nor";
103 spi-max-frequency = <50000000>;
109 reg = < 0x1e631000 0xc4
110 0x38000000 0x08000000 >;
111 #address-cells = <1>;
113 compatible = "aspeed,ast2500-spi";
114 clocks = <&syscon ASPEED_CLK_AHB>;
118 compatible = "jedec,spi-nor";
119 spi-max-frequency = <50000000>;
124 compatible = "jedec,spi-nor";
125 spi-max-frequency = <50000000>;
130 vic: interrupt-controller@1e6c0080 {
131 compatible = "aspeed,ast2400-vic";
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 valid-sources = <0xfefff7ff 0x0807ffff>;
135 reg = <0x1e6c0080 0x80>;
138 cvic: copro-interrupt-controller@1e6c2000 {
139 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
140 valid-sources = <0xffffffff>;
141 copro-sw-interrupts = <1>;
142 reg = <0x1e6c2000 0x80>;
145 mac0: ethernet@1e660000 {
146 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
147 reg = <0x1e660000 0x180>;
149 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
153 mac1: ethernet@1e680000 {
154 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
155 reg = <0x1e680000 0x180>;
157 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
161 ehci0: usb@1e6a1000 {
162 compatible = "aspeed,ast2500-ehci", "generic-ehci";
163 reg = <0x1e6a1000 0x100>;
165 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_usb2ah_default>;
171 ehci1: usb@1e6a3000 {
172 compatible = "aspeed,ast2500-ehci", "generic-ehci";
173 reg = <0x1e6a3000 0x100>;
175 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_usb2bh_default>;
182 compatible = "aspeed,ast2500-uhci", "generic-uhci";
183 reg = <0x1e6b0000 0x100>;
186 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
189 * No default pinmux, it will follow EHCI, use an explicit pinmux
190 * override if you don't enable EHCI
194 vhub: usb-vhub@1e6a0000 {
195 compatible = "aspeed,ast2500-usb-vhub";
196 reg = <0x1e6a0000 0x300>;
198 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
199 aspeed,vhub-downstream-ports = <5>;
200 aspeed,vhub-generic-endpoints = <15>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_usb2ad_default>;
207 compatible = "simple-bus";
208 #address-cells = <1>;
212 edac: memory-controller@1e6e0000 {
213 compatible = "aspeed,ast2500-sdram-edac";
214 reg = <0x1e6e0000 0x174>;
219 syscon: syscon@1e6e2000 {
220 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
221 reg = <0x1e6e2000 0x1a8>;
222 #address-cells = <1>;
224 ranges = <0 0x1e6e2000 0x1000>;
228 scu_ic: interrupt-controller@18 {
229 #interrupt-cells = <1>;
230 compatible = "aspeed,ast2500-scu-ic";
233 interrupt-controller;
236 p2a: p2a-control@2c {
237 compatible = "aspeed,ast2500-p2a-ctrl";
243 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
244 reg = <0x7c 0x4 0x150 0x8>;
247 pinctrl: pinctrl@80 {
248 compatible = "aspeed,ast2500-pinctrl";
249 reg = <0x80 0x18>, <0xa0 0x10>;
250 aspeed,external-nodes = <&gfx>, <&lhc>;
254 rng: hwrng@1e6e2078 {
255 compatible = "timeriomem_rng";
256 reg = <0x1e6e2078 0x4>;
261 gfx: display@1e6e6000 {
262 compatible = "aspeed,ast2500-gfx", "syscon";
263 reg = <0x1e6e6000 0x1000>;
265 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
266 resets = <&syscon ASPEED_RESET_CRT1>;
272 xdma: xdma@1e6e7000 {
273 compatible = "aspeed,ast2500-xdma";
274 reg = <0x1e6e7000 0x100>;
275 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
276 resets = <&syscon ASPEED_RESET_XDMA>;
277 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
278 aspeed,pcie-device = "bmc";
279 aspeed,scu = <&syscon>;
284 compatible = "aspeed,ast2500-adc";
285 reg = <0x1e6e9000 0xb0>;
286 clocks = <&syscon ASPEED_CLK_APB>;
287 resets = <&syscon ASPEED_RESET_ADC>;
288 #io-channel-cells = <1>;
292 video: video@1e700000 {
293 compatible = "aspeed,ast2500-video-engine";
294 reg = <0x1e700000 0x1000>;
295 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
296 <&syscon ASPEED_CLK_GATE_ECLK>;
297 clock-names = "vclk", "eclk";
302 sram: sram@1e720000 {
303 compatible = "mmio-sram";
304 reg = <0x1e720000 0x9000>; // 36K
307 sdmmc: sd-controller@1e740000 {
308 compatible = "aspeed,ast2500-sd-controller";
309 reg = <0x1e740000 0x100>;
310 #address-cells = <1>;
312 ranges = <0 0x1e740000 0x10000>;
313 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
317 compatible = "aspeed,ast2500-sdhci";
321 clocks = <&syscon ASPEED_CLK_SDIO>;
326 compatible = "aspeed,ast2500-sdhci";
330 clocks = <&syscon ASPEED_CLK_SDIO>;
335 gpio: gpio@1e780000 {
338 compatible = "aspeed,ast2500-gpio";
339 reg = <0x1e780000 0x200>;
341 gpio-ranges = <&pinctrl 0 0 232>;
342 clocks = <&syscon ASPEED_CLK_APB>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
347 sgpio: sgpio@1e780200 {
349 compatible = "aspeed,ast2500-sgpio";
352 reg = <0x1e780200 0x0100>;
353 clocks = <&syscon ASPEED_CLK_APB>;
354 interrupt-controller;
355 bus-frequency = <12000000>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_sgpm_default>;
362 compatible = "aspeed,ast2500-rtc";
363 reg = <0x1e781000 0x18>;
367 timer: timer@1e782000 {
368 /* This timer is a Faraday FTTMR010 derivative */
369 compatible = "aspeed,ast2400-timer";
370 reg = <0x1e782000 0x90>;
371 interrupts = <16 17 18 35 36 37 38 39>;
372 clocks = <&syscon ASPEED_CLK_APB>;
373 clock-names = "PCLK";
376 uart1: serial@1e783000 {
377 compatible = "ns16550a";
378 reg = <0x1e783000 0x20>;
381 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
382 resets = <&lpc_reset 4>;
387 uart5: serial@1e784000 {
388 compatible = "ns16550a";
389 reg = <0x1e784000 0x20>;
392 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
397 wdt1: watchdog@1e785000 {
398 compatible = "aspeed,ast2500-wdt";
399 reg = <0x1e785000 0x20>;
400 clocks = <&syscon ASPEED_CLK_APB>;
403 wdt2: watchdog@1e785020 {
404 compatible = "aspeed,ast2500-wdt";
405 reg = <0x1e785020 0x20>;
406 clocks = <&syscon ASPEED_CLK_APB>;
409 wdt3: watchdog@1e785040 {
410 compatible = "aspeed,ast2500-wdt";
411 reg = <0x1e785040 0x20>;
412 clocks = <&syscon ASPEED_CLK_APB>;
416 pwm_tacho: pwm-tacho-controller@1e786000 {
417 compatible = "aspeed,ast2500-pwm-tacho";
418 #address-cells = <1>;
420 reg = <0x1e786000 0x1000>;
421 clocks = <&syscon ASPEED_CLK_24M>;
422 resets = <&syscon ASPEED_RESET_PWM>;
426 vuart: serial@1e787000 {
427 compatible = "aspeed,ast2500-vuart";
428 reg = <0x1e787000 0x40>;
431 clocks = <&syscon ASPEED_CLK_APB>;
437 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
438 reg = <0x1e789000 0x1000>;
441 #address-cells = <1>;
443 ranges = <0x0 0x1e789000 0x1000>;
446 compatible = "aspeed,ast2500-kcs-bmc-v2";
447 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
453 compatible = "aspeed,ast2500-kcs-bmc-v2";
454 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
460 compatible = "aspeed,ast2500-kcs-bmc-v2";
461 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
467 compatible = "aspeed,ast2500-kcs-bmc-v2";
468 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
473 lpc_ctrl: lpc-ctrl@80 {
474 compatible = "aspeed,ast2500-lpc-ctrl";
476 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
480 lpc_snoop: lpc-snoop@90 {
481 compatible = "aspeed,ast2500-lpc-snoop";
484 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
488 lpc_reset: reset-controller@98 {
489 compatible = "aspeed,ast2500-lpc-reset";
495 compatible = "aspeed,ast2500-lhc";
496 reg = <0xa0 0x24 0xc8 0x8>;
501 compatible = "aspeed,ast2500-ibt-bmc";
508 uart2: serial@1e78d000 {
509 compatible = "ns16550a";
510 reg = <0x1e78d000 0x20>;
513 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
514 resets = <&lpc_reset 5>;
519 uart3: serial@1e78e000 {
520 compatible = "ns16550a";
521 reg = <0x1e78e000 0x20>;
524 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
525 resets = <&lpc_reset 6>;
530 uart4: serial@1e78f000 {
531 compatible = "ns16550a";
532 reg = <0x1e78f000 0x20>;
535 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
536 resets = <&lpc_reset 7>;
542 compatible = "simple-bus";
543 #address-cells = <1>;
545 ranges = <0 0x1e78a000 0x1000>;
552 i2c_ic: interrupt-controller@0 {
553 #interrupt-cells = <1>;
554 compatible = "aspeed,ast2500-i2c-ic";
557 interrupt-controller;
561 #address-cells = <1>;
563 #interrupt-cells = <1>;
566 compatible = "aspeed,ast2500-i2c-bus";
567 clocks = <&syscon ASPEED_CLK_APB>;
568 resets = <&syscon ASPEED_RESET_I2C>;
569 bus-frequency = <100000>;
571 interrupt-parent = <&i2c_ic>;
573 /* Does not need pinctrl properties */
577 #address-cells = <1>;
579 #interrupt-cells = <1>;
582 compatible = "aspeed,ast2500-i2c-bus";
583 clocks = <&syscon ASPEED_CLK_APB>;
584 resets = <&syscon ASPEED_RESET_I2C>;
585 bus-frequency = <100000>;
587 interrupt-parent = <&i2c_ic>;
589 /* Does not need pinctrl properties */
593 #address-cells = <1>;
595 #interrupt-cells = <1>;
598 compatible = "aspeed,ast2500-i2c-bus";
599 clocks = <&syscon ASPEED_CLK_APB>;
600 resets = <&syscon ASPEED_RESET_I2C>;
601 bus-frequency = <100000>;
603 interrupt-parent = <&i2c_ic>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_i2c3_default>;
610 #address-cells = <1>;
612 #interrupt-cells = <1>;
615 compatible = "aspeed,ast2500-i2c-bus";
616 clocks = <&syscon ASPEED_CLK_APB>;
617 resets = <&syscon ASPEED_RESET_I2C>;
618 bus-frequency = <100000>;
620 interrupt-parent = <&i2c_ic>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_i2c4_default>;
627 #address-cells = <1>;
629 #interrupt-cells = <1>;
632 compatible = "aspeed,ast2500-i2c-bus";
633 clocks = <&syscon ASPEED_CLK_APB>;
634 resets = <&syscon ASPEED_RESET_I2C>;
635 bus-frequency = <100000>;
637 interrupt-parent = <&i2c_ic>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_i2c5_default>;
644 #address-cells = <1>;
646 #interrupt-cells = <1>;
649 compatible = "aspeed,ast2500-i2c-bus";
650 clocks = <&syscon ASPEED_CLK_APB>;
651 resets = <&syscon ASPEED_RESET_I2C>;
652 bus-frequency = <100000>;
654 interrupt-parent = <&i2c_ic>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&pinctrl_i2c6_default>;
661 #address-cells = <1>;
663 #interrupt-cells = <1>;
666 compatible = "aspeed,ast2500-i2c-bus";
667 clocks = <&syscon ASPEED_CLK_APB>;
668 resets = <&syscon ASPEED_RESET_I2C>;
669 bus-frequency = <100000>;
671 interrupt-parent = <&i2c_ic>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_i2c7_default>;
678 #address-cells = <1>;
680 #interrupt-cells = <1>;
683 compatible = "aspeed,ast2500-i2c-bus";
684 clocks = <&syscon ASPEED_CLK_APB>;
685 resets = <&syscon ASPEED_RESET_I2C>;
686 bus-frequency = <100000>;
688 interrupt-parent = <&i2c_ic>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_i2c8_default>;
695 #address-cells = <1>;
697 #interrupt-cells = <1>;
700 compatible = "aspeed,ast2500-i2c-bus";
701 clocks = <&syscon ASPEED_CLK_APB>;
702 resets = <&syscon ASPEED_RESET_I2C>;
703 bus-frequency = <100000>;
705 interrupt-parent = <&i2c_ic>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_i2c9_default>;
712 #address-cells = <1>;
714 #interrupt-cells = <1>;
717 compatible = "aspeed,ast2500-i2c-bus";
718 clocks = <&syscon ASPEED_CLK_APB>;
719 resets = <&syscon ASPEED_RESET_I2C>;
720 bus-frequency = <100000>;
722 interrupt-parent = <&i2c_ic>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_i2c10_default>;
729 #address-cells = <1>;
731 #interrupt-cells = <1>;
734 compatible = "aspeed,ast2500-i2c-bus";
735 clocks = <&syscon ASPEED_CLK_APB>;
736 resets = <&syscon ASPEED_RESET_I2C>;
737 bus-frequency = <100000>;
739 interrupt-parent = <&i2c_ic>;
740 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_i2c11_default>;
746 #address-cells = <1>;
748 #interrupt-cells = <1>;
751 compatible = "aspeed,ast2500-i2c-bus";
752 clocks = <&syscon ASPEED_CLK_APB>;
753 resets = <&syscon ASPEED_RESET_I2C>;
754 bus-frequency = <100000>;
756 interrupt-parent = <&i2c_ic>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_i2c12_default>;
763 #address-cells = <1>;
765 #interrupt-cells = <1>;
768 compatible = "aspeed,ast2500-i2c-bus";
769 clocks = <&syscon ASPEED_CLK_APB>;
770 resets = <&syscon ASPEED_RESET_I2C>;
771 bus-frequency = <100000>;
773 interrupt-parent = <&i2c_ic>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_i2c13_default>;
780 #address-cells = <1>;
782 #interrupt-cells = <1>;
785 compatible = "aspeed,ast2500-i2c-bus";
786 clocks = <&syscon ASPEED_CLK_APB>;
787 resets = <&syscon ASPEED_RESET_I2C>;
788 bus-frequency = <100000>;
790 interrupt-parent = <&i2c_ic>;
791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_i2c14_default>;
798 pinctrl_acpi_default: acpi_default {
803 pinctrl_adc0_default: adc0_default {
808 pinctrl_adc1_default: adc1_default {
813 pinctrl_adc10_default: adc10_default {
818 pinctrl_adc11_default: adc11_default {
823 pinctrl_adc12_default: adc12_default {
828 pinctrl_adc13_default: adc13_default {
833 pinctrl_adc14_default: adc14_default {
838 pinctrl_adc15_default: adc15_default {
843 pinctrl_adc2_default: adc2_default {
848 pinctrl_adc3_default: adc3_default {
853 pinctrl_adc4_default: adc4_default {
858 pinctrl_adc5_default: adc5_default {
863 pinctrl_adc6_default: adc6_default {
868 pinctrl_adc7_default: adc7_default {
873 pinctrl_adc8_default: adc8_default {
878 pinctrl_adc9_default: adc9_default {
883 pinctrl_bmcint_default: bmcint_default {
888 pinctrl_ddcclk_default: ddcclk_default {
893 pinctrl_ddcdat_default: ddcdat_default {
898 pinctrl_espi_default: espi_default {
903 pinctrl_fwspics1_default: fwspics1_default {
904 function = "FWSPICS1";
908 pinctrl_fwspics2_default: fwspics2_default {
909 function = "FWSPICS2";
913 pinctrl_gpid0_default: gpid0_default {
918 pinctrl_gpid2_default: gpid2_default {
923 pinctrl_gpid4_default: gpid4_default {
928 pinctrl_gpid6_default: gpid6_default {
933 pinctrl_gpie0_default: gpie0_default {
938 pinctrl_gpie2_default: gpie2_default {
943 pinctrl_gpie4_default: gpie4_default {
948 pinctrl_gpie6_default: gpie6_default {
953 pinctrl_i2c10_default: i2c10_default {
958 pinctrl_i2c11_default: i2c11_default {
963 pinctrl_i2c12_default: i2c12_default {
968 pinctrl_i2c13_default: i2c13_default {
973 pinctrl_i2c14_default: i2c14_default {
978 pinctrl_i2c3_default: i2c3_default {
983 pinctrl_i2c4_default: i2c4_default {
988 pinctrl_i2c5_default: i2c5_default {
993 pinctrl_i2c6_default: i2c6_default {
998 pinctrl_i2c7_default: i2c7_default {
1003 pinctrl_i2c8_default: i2c8_default {
1008 pinctrl_i2c9_default: i2c9_default {
1013 pinctrl_lad0_default: lad0_default {
1018 pinctrl_lad1_default: lad1_default {
1023 pinctrl_lad2_default: lad2_default {
1028 pinctrl_lad3_default: lad3_default {
1033 pinctrl_lclk_default: lclk_default {
1038 pinctrl_lframe_default: lframe_default {
1039 function = "LFRAME";
1043 pinctrl_lpchc_default: lpchc_default {
1048 pinctrl_lpcpd_default: lpcpd_default {
1053 pinctrl_lpcplus_default: lpcplus_default {
1054 function = "LPCPLUS";
1058 pinctrl_lpcpme_default: lpcpme_default {
1059 function = "LPCPME";
1063 pinctrl_lpcrst_default: lpcrst_default {
1064 function = "LPCRST";
1068 pinctrl_lpcsmi_default: lpcsmi_default {
1069 function = "LPCSMI";
1073 pinctrl_lsirq_default: lsirq_default {
1078 pinctrl_mac1link_default: mac1link_default {
1079 function = "MAC1LINK";
1080 groups = "MAC1LINK";
1083 pinctrl_mac2link_default: mac2link_default {
1084 function = "MAC2LINK";
1085 groups = "MAC2LINK";
1088 pinctrl_mdio1_default: mdio1_default {
1093 pinctrl_mdio2_default: mdio2_default {
1098 pinctrl_ncts1_default: ncts1_default {
1103 pinctrl_ncts2_default: ncts2_default {
1108 pinctrl_ncts3_default: ncts3_default {
1113 pinctrl_ncts4_default: ncts4_default {
1118 pinctrl_ndcd1_default: ndcd1_default {
1123 pinctrl_ndcd2_default: ndcd2_default {
1128 pinctrl_ndcd3_default: ndcd3_default {
1133 pinctrl_ndcd4_default: ndcd4_default {
1138 pinctrl_ndsr1_default: ndsr1_default {
1143 pinctrl_ndsr2_default: ndsr2_default {
1148 pinctrl_ndsr3_default: ndsr3_default {
1153 pinctrl_ndsr4_default: ndsr4_default {
1158 pinctrl_ndtr1_default: ndtr1_default {
1163 pinctrl_ndtr2_default: ndtr2_default {
1168 pinctrl_ndtr3_default: ndtr3_default {
1173 pinctrl_ndtr4_default: ndtr4_default {
1178 pinctrl_nri1_default: nri1_default {
1183 pinctrl_nri2_default: nri2_default {
1188 pinctrl_nri3_default: nri3_default {
1193 pinctrl_nri4_default: nri4_default {
1198 pinctrl_nrts1_default: nrts1_default {
1203 pinctrl_nrts2_default: nrts2_default {
1208 pinctrl_nrts3_default: nrts3_default {
1213 pinctrl_nrts4_default: nrts4_default {
1218 pinctrl_oscclk_default: oscclk_default {
1219 function = "OSCCLK";
1223 pinctrl_pewake_default: pewake_default {
1224 function = "PEWAKE";
1228 pinctrl_pnor_default: pnor_default {
1233 pinctrl_pwm0_default: pwm0_default {
1238 pinctrl_pwm1_default: pwm1_default {
1243 pinctrl_pwm2_default: pwm2_default {
1248 pinctrl_pwm3_default: pwm3_default {
1253 pinctrl_pwm4_default: pwm4_default {
1258 pinctrl_pwm5_default: pwm5_default {
1263 pinctrl_pwm6_default: pwm6_default {
1268 pinctrl_pwm7_default: pwm7_default {
1273 pinctrl_rgmii1_default: rgmii1_default {
1274 function = "RGMII1";
1278 pinctrl_rgmii2_default: rgmii2_default {
1279 function = "RGMII2";
1283 pinctrl_rmii1_default: rmii1_default {
1288 pinctrl_rmii2_default: rmii2_default {
1293 pinctrl_rxd1_default: rxd1_default {
1298 pinctrl_rxd2_default: rxd2_default {
1303 pinctrl_rxd3_default: rxd3_default {
1308 pinctrl_rxd4_default: rxd4_default {
1313 pinctrl_salt1_default: salt1_default {
1318 pinctrl_salt10_default: salt10_default {
1319 function = "SALT10";
1323 pinctrl_salt11_default: salt11_default {
1324 function = "SALT11";
1328 pinctrl_salt12_default: salt12_default {
1329 function = "SALT12";
1333 pinctrl_salt13_default: salt13_default {
1334 function = "SALT13";
1338 pinctrl_salt14_default: salt14_default {
1339 function = "SALT14";
1343 pinctrl_salt2_default: salt2_default {
1348 pinctrl_salt3_default: salt3_default {
1353 pinctrl_salt4_default: salt4_default {
1358 pinctrl_salt5_default: salt5_default {
1363 pinctrl_salt6_default: salt6_default {
1368 pinctrl_salt7_default: salt7_default {
1373 pinctrl_salt8_default: salt8_default {
1378 pinctrl_salt9_default: salt9_default {
1383 pinctrl_scl1_default: scl1_default {
1388 pinctrl_scl2_default: scl2_default {
1393 pinctrl_sd1_default: sd1_default {
1398 pinctrl_sd2_default: sd2_default {
1403 pinctrl_sda1_default: sda1_default {
1408 pinctrl_sda2_default: sda2_default {
1413 pinctrl_sgpm_default: sgpm_default {
1418 pinctrl_sgps1_default: sgps1_default {
1423 pinctrl_sgps2_default: sgps2_default {
1428 pinctrl_sioonctrl_default: sioonctrl_default {
1429 function = "SIOONCTRL";
1430 groups = "SIOONCTRL";
1433 pinctrl_siopbi_default: siopbi_default {
1434 function = "SIOPBI";
1438 pinctrl_siopbo_default: siopbo_default {
1439 function = "SIOPBO";
1443 pinctrl_siopwreq_default: siopwreq_default {
1444 function = "SIOPWREQ";
1445 groups = "SIOPWREQ";
1448 pinctrl_siopwrgd_default: siopwrgd_default {
1449 function = "SIOPWRGD";
1450 groups = "SIOPWRGD";
1453 pinctrl_sios3_default: sios3_default {
1458 pinctrl_sios5_default: sios5_default {
1463 pinctrl_siosci_default: siosci_default {
1464 function = "SIOSCI";
1468 pinctrl_spi1_default: spi1_default {
1473 pinctrl_spi1cs1_default: spi1cs1_default {
1474 function = "SPI1CS1";
1478 pinctrl_spi1debug_default: spi1debug_default {
1479 function = "SPI1DEBUG";
1480 groups = "SPI1DEBUG";
1483 pinctrl_spi1passthru_default: spi1passthru_default {
1484 function = "SPI1PASSTHRU";
1485 groups = "SPI1PASSTHRU";
1488 pinctrl_spi2ck_default: spi2ck_default {
1489 function = "SPI2CK";
1493 pinctrl_spi2cs0_default: spi2cs0_default {
1494 function = "SPI2CS0";
1498 pinctrl_spi2cs1_default: spi2cs1_default {
1499 function = "SPI2CS1";
1503 pinctrl_spi2miso_default: spi2miso_default {
1504 function = "SPI2MISO";
1505 groups = "SPI2MISO";
1508 pinctrl_spi2mosi_default: spi2mosi_default {
1509 function = "SPI2MOSI";
1510 groups = "SPI2MOSI";
1513 pinctrl_timer3_default: timer3_default {
1514 function = "TIMER3";
1518 pinctrl_timer4_default: timer4_default {
1519 function = "TIMER4";
1523 pinctrl_timer5_default: timer5_default {
1524 function = "TIMER5";
1528 pinctrl_timer6_default: timer6_default {
1529 function = "TIMER6";
1533 pinctrl_timer7_default: timer7_default {
1534 function = "TIMER7";
1538 pinctrl_timer8_default: timer8_default {
1539 function = "TIMER8";
1543 pinctrl_txd1_default: txd1_default {
1548 pinctrl_txd2_default: txd2_default {
1553 pinctrl_txd3_default: txd3_default {
1558 pinctrl_txd4_default: txd4_default {
1563 pinctrl_uart6_default: uart6_default {
1568 pinctrl_usbcki_default: usbcki_default {
1569 function = "USBCKI";
1573 pinctrl_usb2ah_default: usb2ah_default {
1574 function = "USB2AH";
1578 pinctrl_usb2ad_default: usb2ad_default {
1579 function = "USB2AD";
1583 pinctrl_usb11bhid_default: usb11bhid_default {
1584 function = "USB11BHID";
1585 groups = "USB11BHID";
1588 pinctrl_usb2bh_default: usb2bh_default {
1589 function = "USB2BH";
1593 pinctrl_vgabiosrom_default: vgabiosrom_default {
1594 function = "VGABIOSROM";
1595 groups = "VGABIOSROM";
1598 pinctrl_vgahs_default: vgahs_default {
1603 pinctrl_vgavs_default: vgavs_default {
1608 pinctrl_vpi24_default: vpi24_default {
1613 pinctrl_vpo_default: vpo_default {
1618 pinctrl_wdtrst1_default: wdtrst1_default {
1619 function = "WDTRST1";
1623 pinctrl_wdtrst2_default: wdtrst2_default {
1624 function = "WDTRST2";