1 // SPDX-License-Identifier: GPL-2.0
2 #include "skeleton.dtsi"
6 compatible = "aspeed,ast2500";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm1176jzf-s";
46 compatible = "simple-bus";
51 fmc: flash-controller@1e620000 {
52 reg = < 0x1e620000 0xc4
53 0x20000000 0x10000000 >;
56 compatible = "aspeed,ast2500-fmc";
61 compatible = "jedec,spi-nor";
66 compatible = "jedec,spi-nor";
71 compatible = "jedec,spi-nor";
76 spi1: flash-controller@1e630000 {
77 reg = < 0x1e630000 0xc4
78 0x30000000 0x08000000 >;
81 compatible = "aspeed,ast2500-spi";
85 compatible = "jedec,spi-nor";
90 compatible = "jedec,spi-nor";
95 spi2: flash-controller@1e631000 {
96 reg = < 0x1e631000 0xc4
97 0x38000000 0x08000000 >;
100 compatible = "aspeed,ast2500-spi";
104 compatible = "jedec,spi-nor";
109 compatible = "jedec,spi-nor";
114 vic: interrupt-controller@1e6c0080 {
115 compatible = "aspeed,ast2400-vic";
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 valid-sources = <0xfefff7ff 0x0807ffff>;
119 reg = <0x1e6c0080 0x80>;
122 mac0: ethernet@1e660000 {
123 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
124 reg = <0x1e660000 0x180>;
129 mac1: ethernet@1e680000 {
130 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
131 reg = <0x1e680000 0x180>;
137 compatible = "simple-bus";
138 #address-cells = <1>;
142 syscon: syscon@1e6e2000 {
143 compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
144 reg = <0x1e6e2000 0x1a8>;
145 #address-cells = <1>;
148 clk_clkin: clk_clkin@70 {
150 compatible = "aspeed,g5-clkin-clock", "fixed-clock";
152 clock-frequency = <24000000>;
155 clk_hpll: clk_hpll@24 {
157 compatible = "aspeed,g5-hpll-clock", "fixed-clock";
159 clocks = <&clk_clkin>;
160 clock-frequency = <792000000>;
163 clk_ahb: clk_ahb@70 {
165 compatible = "aspeed,g5-ahb-clock", "fixed-clock";
167 clocks = <&clk_hpll>;
168 clock-frequency = <198000000>;
173 compatible = "aspeed,g5-apb-clock", "fixed-clock";
175 clocks = <&clk_hpll>;
176 clock-frequency = <24750000>;
179 clk_uart: clk_uart@2c {
181 compatible = "aspeed,uart-clock", "fixed-clock";
183 clock-frequency = <24000000>;
187 compatible = "aspeed,g5-pinctrl";
188 aspeed,external-nodes = <&gfx &lhc>;
194 gfx: display@1e6e6000 {
195 compatible = "aspeed,ast2500-gfx", "syscon";
196 reg = <0x1e6e6000 0x1000>;
201 compatible = "aspeed,ast2500-adc";
202 reg = <0x1e6e9000 0xb0>;
204 #io-channel-cells = <1>;
209 compatible = "mmio-sram";
210 reg = <0x1e720000 0x9000>; // 36K
213 gpio: gpio@1e780000 {
216 compatible = "aspeed,ast2500-gpio";
217 reg = <0x1e780000 0x1000>;
219 gpio-ranges = <&pinctrl 0 0 220>;
220 interrupt-controller;
223 timer: timer@1e782000 {
224 /* This timer is a Faraday FTTMR010 derivative */
225 compatible = "aspeed,ast2400-timer";
226 reg = <0x1e782000 0x90>;
227 interrupts = <16 17 18 35 36 37 38 39>;
229 clock-names = "PCLK";
232 uart1: serial@1e783000 {
233 compatible = "ns16550a";
234 reg = <0x1e783000 0x20>;
237 clocks = <&clk_uart>;
242 uart5: serial@1e784000 {
243 compatible = "ns16550a";
244 reg = <0x1e784000 0x20>;
247 clocks = <&clk_uart>;
252 wdt1: watchdog@1e785000 {
253 compatible = "aspeed,ast2500-wdt";
254 reg = <0x1e785000 0x20>;
257 wdt2: watchdog@1e785020 {
258 compatible = "aspeed,ast2500-wdt";
259 reg = <0x1e785020 0x20>;
262 wdt3: watchdog@1e785040 {
263 compatible = "aspeed,ast2500-wdt";
264 reg = <0x1e785040 0x20>;
269 compatible = "aspeed,ast2500-lpc", "simple-mfd";
270 reg = <0x1e789000 0x1000>;
272 #address-cells = <1>;
274 ranges = <0 0x1e789000 0x1000>;
277 compatible = "aspeed,ast2500-lpc-bmc";
281 lpc_host: lpc-host@80 {
282 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
285 #address-cells = <1>;
287 ranges = <0 0x80 0x1e0>;
292 compatible = "aspeed,ast2500-lhc";
293 reg = <0x20 0x24 0x48 0x8>;
298 vuart: serial@1e787000 {
299 compatible = "aspeed,ast2500-vuart";
300 reg = <0x1e787000 0x40>;
303 clocks = <&clk_uart>;
308 uart2: serial@1e78d000 {
309 compatible = "ns16550a";
310 reg = <0x1e78d000 0x20>;
313 clocks = <&clk_uart>;
318 uart3: serial@1e78e000 {
319 compatible = "ns16550a";
320 reg = <0x1e78e000 0x20>;
323 clocks = <&clk_uart>;
328 uart4: serial@1e78f000 {
329 compatible = "ns16550a";
330 reg = <0x1e78f000 0x20>;
333 clocks = <&clk_uart>;
339 compatible = "simple-bus";
340 #address-cells = <1>;
342 ranges = <0 0x1e78a000 0x1000>;
349 i2c_ic: interrupt-controller@0 {
350 #interrupt-cells = <1>;
351 compatible = "aspeed,ast2500-i2c-ic";
354 interrupt-controller;
358 #address-cells = <1>;
360 #interrupt-cells = <1>;
363 compatible = "aspeed,ast2500-i2c-bus";
365 bus-frequency = <100000>;
367 interrupt-parent = <&i2c_ic>;
369 /* Does not need pinctrl properties */
373 #address-cells = <1>;
375 #interrupt-cells = <1>;
378 compatible = "aspeed,ast2500-i2c-bus";
380 bus-frequency = <100000>;
382 interrupt-parent = <&i2c_ic>;
384 /* Does not need pinctrl properties */
388 #address-cells = <1>;
390 #interrupt-cells = <1>;
393 compatible = "aspeed,ast2500-i2c-bus";
395 bus-frequency = <100000>;
397 interrupt-parent = <&i2c_ic>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_i2c3_default>;
404 #address-cells = <1>;
406 #interrupt-cells = <1>;
409 compatible = "aspeed,ast2500-i2c-bus";
411 bus-frequency = <100000>;
413 interrupt-parent = <&i2c_ic>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_i2c4_default>;
420 #address-cells = <1>;
422 #interrupt-cells = <1>;
425 compatible = "aspeed,ast2500-i2c-bus";
427 bus-frequency = <100000>;
429 interrupt-parent = <&i2c_ic>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_i2c5_default>;
436 #address-cells = <1>;
438 #interrupt-cells = <1>;
441 compatible = "aspeed,ast2500-i2c-bus";
443 bus-frequency = <100000>;
445 interrupt-parent = <&i2c_ic>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_i2c6_default>;
452 #address-cells = <1>;
454 #interrupt-cells = <1>;
457 compatible = "aspeed,ast2500-i2c-bus";
459 bus-frequency = <100000>;
461 interrupt-parent = <&i2c_ic>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_i2c7_default>;
468 #address-cells = <1>;
470 #interrupt-cells = <1>;
473 compatible = "aspeed,ast2500-i2c-bus";
475 bus-frequency = <100000>;
477 interrupt-parent = <&i2c_ic>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_i2c8_default>;
484 #address-cells = <1>;
486 #interrupt-cells = <1>;
489 compatible = "aspeed,ast2500-i2c-bus";
491 bus-frequency = <100000>;
493 interrupt-parent = <&i2c_ic>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&pinctrl_i2c9_default>;
500 #address-cells = <1>;
502 #interrupt-cells = <1>;
505 compatible = "aspeed,ast2500-i2c-bus";
507 bus-frequency = <100000>;
509 interrupt-parent = <&i2c_ic>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_i2c10_default>;
516 #address-cells = <1>;
518 #interrupt-cells = <1>;
521 compatible = "aspeed,ast2500-i2c-bus";
523 bus-frequency = <100000>;
525 interrupt-parent = <&i2c_ic>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_i2c11_default>;
532 #address-cells = <1>;
534 #interrupt-cells = <1>;
537 compatible = "aspeed,ast2500-i2c-bus";
539 bus-frequency = <100000>;
541 interrupt-parent = <&i2c_ic>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_i2c12_default>;
548 #address-cells = <1>;
550 #interrupt-cells = <1>;
553 compatible = "aspeed,ast2500-i2c-bus";
555 bus-frequency = <100000>;
557 interrupt-parent = <&i2c_ic>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_i2c13_default>;
564 #address-cells = <1>;
566 #interrupt-cells = <1>;
569 compatible = "aspeed,ast2500-i2c-bus";
571 bus-frequency = <100000>;
573 interrupt-parent = <&i2c_ic>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_i2c14_default>;
581 pinctrl_acpi_default: acpi_default {
586 pinctrl_adc0_default: adc0_default {
591 pinctrl_adc1_default: adc1_default {
596 pinctrl_adc10_default: adc10_default {
601 pinctrl_adc11_default: adc11_default {
606 pinctrl_adc12_default: adc12_default {
611 pinctrl_adc13_default: adc13_default {
616 pinctrl_adc14_default: adc14_default {
621 pinctrl_adc15_default: adc15_default {
626 pinctrl_adc2_default: adc2_default {
631 pinctrl_adc3_default: adc3_default {
636 pinctrl_adc4_default: adc4_default {
641 pinctrl_adc5_default: adc5_default {
646 pinctrl_adc6_default: adc6_default {
651 pinctrl_adc7_default: adc7_default {
656 pinctrl_adc8_default: adc8_default {
661 pinctrl_adc9_default: adc9_default {
666 pinctrl_bmcint_default: bmcint_default {
671 pinctrl_ddcclk_default: ddcclk_default {
676 pinctrl_ddcdat_default: ddcdat_default {
681 pinctrl_espi_default: espi_default {
686 pinctrl_fwspics1_default: fwspics1_default {
687 function = "FWSPICS1";
691 pinctrl_fwspics2_default: fwspics2_default {
692 function = "FWSPICS2";
696 pinctrl_gpid0_default: gpid0_default {
701 pinctrl_gpid2_default: gpid2_default {
706 pinctrl_gpid4_default: gpid4_default {
711 pinctrl_gpid6_default: gpid6_default {
716 pinctrl_gpie0_default: gpie0_default {
721 pinctrl_gpie2_default: gpie2_default {
726 pinctrl_gpie4_default: gpie4_default {
731 pinctrl_gpie6_default: gpie6_default {
736 pinctrl_i2c10_default: i2c10_default {
741 pinctrl_i2c11_default: i2c11_default {
746 pinctrl_i2c12_default: i2c12_default {
751 pinctrl_i2c13_default: i2c13_default {
756 pinctrl_i2c14_default: i2c14_default {
761 pinctrl_i2c3_default: i2c3_default {
766 pinctrl_i2c4_default: i2c4_default {
771 pinctrl_i2c5_default: i2c5_default {
776 pinctrl_i2c6_default: i2c6_default {
781 pinctrl_i2c7_default: i2c7_default {
786 pinctrl_i2c8_default: i2c8_default {
791 pinctrl_i2c9_default: i2c9_default {
796 pinctrl_lad0_default: lad0_default {
801 pinctrl_lad1_default: lad1_default {
806 pinctrl_lad2_default: lad2_default {
811 pinctrl_lad3_default: lad3_default {
816 pinctrl_lclk_default: lclk_default {
821 pinctrl_lframe_default: lframe_default {
826 pinctrl_lpchc_default: lpchc_default {
831 pinctrl_lpcpd_default: lpcpd_default {
836 pinctrl_lpcplus_default: lpcplus_default {
837 function = "LPCPLUS";
841 pinctrl_lpcpme_default: lpcpme_default {
846 pinctrl_lpcrst_default: lpcrst_default {
851 pinctrl_lpcsmi_default: lpcsmi_default {
856 pinctrl_lsirq_default: lsirq_default {
861 pinctrl_mac1link_default: mac1link_default {
862 function = "MAC1LINK";
866 pinctrl_mac2link_default: mac2link_default {
867 function = "MAC2LINK";
871 pinctrl_mdio1_default: mdio1_default {
876 pinctrl_mdio2_default: mdio2_default {
881 pinctrl_ncts1_default: ncts1_default {
886 pinctrl_ncts2_default: ncts2_default {
891 pinctrl_ncts3_default: ncts3_default {
896 pinctrl_ncts4_default: ncts4_default {
901 pinctrl_ndcd1_default: ndcd1_default {
906 pinctrl_ndcd2_default: ndcd2_default {
911 pinctrl_ndcd3_default: ndcd3_default {
916 pinctrl_ndcd4_default: ndcd4_default {
921 pinctrl_ndsr1_default: ndsr1_default {
926 pinctrl_ndsr2_default: ndsr2_default {
931 pinctrl_ndsr3_default: ndsr3_default {
936 pinctrl_ndsr4_default: ndsr4_default {
941 pinctrl_ndtr1_default: ndtr1_default {
946 pinctrl_ndtr2_default: ndtr2_default {
951 pinctrl_ndtr3_default: ndtr3_default {
956 pinctrl_ndtr4_default: ndtr4_default {
961 pinctrl_nri1_default: nri1_default {
966 pinctrl_nri2_default: nri2_default {
971 pinctrl_nri3_default: nri3_default {
976 pinctrl_nri4_default: nri4_default {
981 pinctrl_nrts1_default: nrts1_default {
986 pinctrl_nrts2_default: nrts2_default {
991 pinctrl_nrts3_default: nrts3_default {
996 pinctrl_nrts4_default: nrts4_default {
1001 pinctrl_oscclk_default: oscclk_default {
1002 function = "OSCCLK";
1006 pinctrl_pewake_default: pewake_default {
1007 function = "PEWAKE";
1011 pinctrl_pnor_default: pnor_default {
1016 pinctrl_pwm0_default: pwm0_default {
1021 pinctrl_pwm1_default: pwm1_default {
1026 pinctrl_pwm2_default: pwm2_default {
1031 pinctrl_pwm3_default: pwm3_default {
1036 pinctrl_pwm4_default: pwm4_default {
1041 pinctrl_pwm5_default: pwm5_default {
1046 pinctrl_pwm6_default: pwm6_default {
1051 pinctrl_pwm7_default: pwm7_default {
1056 pinctrl_rgmii1_default: rgmii1_default {
1057 function = "RGMII1";
1061 pinctrl_rgmii2_default: rgmii2_default {
1062 function = "RGMII2";
1066 pinctrl_rmii1_default: rmii1_default {
1071 pinctrl_rmii2_default: rmii2_default {
1076 pinctrl_rxd1_default: rxd1_default {
1081 pinctrl_rxd2_default: rxd2_default {
1086 pinctrl_rxd3_default: rxd3_default {
1091 pinctrl_rxd4_default: rxd4_default {
1096 pinctrl_salt1_default: salt1_default {
1101 pinctrl_salt10_default: salt10_default {
1102 function = "SALT10";
1106 pinctrl_salt11_default: salt11_default {
1107 function = "SALT11";
1111 pinctrl_salt12_default: salt12_default {
1112 function = "SALT12";
1116 pinctrl_salt13_default: salt13_default {
1117 function = "SALT13";
1121 pinctrl_salt14_default: salt14_default {
1122 function = "SALT14";
1126 pinctrl_salt2_default: salt2_default {
1131 pinctrl_salt3_default: salt3_default {
1136 pinctrl_salt4_default: salt4_default {
1141 pinctrl_salt5_default: salt5_default {
1146 pinctrl_salt6_default: salt6_default {
1151 pinctrl_salt7_default: salt7_default {
1156 pinctrl_salt8_default: salt8_default {
1161 pinctrl_salt9_default: salt9_default {
1166 pinctrl_scl1_default: scl1_default {
1171 pinctrl_scl2_default: scl2_default {
1176 pinctrl_sd1_default: sd1_default {
1181 pinctrl_sd2_default: sd2_default {
1186 pinctrl_sda1_default: sda1_default {
1191 pinctrl_sda2_default: sda2_default {
1196 pinctrl_sgps1_default: sgps1_default {
1201 pinctrl_sgps2_default: sgps2_default {
1206 pinctrl_sioonctrl_default: sioonctrl_default {
1207 function = "SIOONCTRL";
1208 groups = "SIOONCTRL";
1211 pinctrl_siopbi_default: siopbi_default {
1212 function = "SIOPBI";
1216 pinctrl_siopbo_default: siopbo_default {
1217 function = "SIOPBO";
1221 pinctrl_siopwreq_default: siopwreq_default {
1222 function = "SIOPWREQ";
1223 groups = "SIOPWREQ";
1226 pinctrl_siopwrgd_default: siopwrgd_default {
1227 function = "SIOPWRGD";
1228 groups = "SIOPWRGD";
1231 pinctrl_sios3_default: sios3_default {
1236 pinctrl_sios5_default: sios5_default {
1241 pinctrl_siosci_default: siosci_default {
1242 function = "SIOSCI";
1246 pinctrl_spi1_default: spi1_default {
1251 pinctrl_spi1cs1_default: spi1cs1_default {
1252 function = "SPI1CS1";
1256 pinctrl_spi1debug_default: spi1debug_default {
1257 function = "SPI1DEBUG";
1258 groups = "SPI1DEBUG";
1261 pinctrl_spi1passthru_default: spi1passthru_default {
1262 function = "SPI1PASSTHRU";
1263 groups = "SPI1PASSTHRU";
1266 pinctrl_spi2ck_default: spi2ck_default {
1267 function = "SPI2CK";
1271 pinctrl_spi2cs0_default: spi2cs0_default {
1272 function = "SPI2CS0";
1276 pinctrl_spi2cs1_default: spi2cs1_default {
1277 function = "SPI2CS1";
1281 pinctrl_spi2miso_default: spi2miso_default {
1282 function = "SPI2MISO";
1283 groups = "SPI2MISO";
1286 pinctrl_spi2mosi_default: spi2mosi_default {
1287 function = "SPI2MOSI";
1288 groups = "SPI2MOSI";
1291 pinctrl_timer3_default: timer3_default {
1292 function = "TIMER3";
1296 pinctrl_timer4_default: timer4_default {
1297 function = "TIMER4";
1301 pinctrl_timer5_default: timer5_default {
1302 function = "TIMER5";
1306 pinctrl_timer6_default: timer6_default {
1307 function = "TIMER6";
1311 pinctrl_timer7_default: timer7_default {
1312 function = "TIMER7";
1316 pinctrl_timer8_default: timer8_default {
1317 function = "TIMER8";
1321 pinctrl_txd1_default: txd1_default {
1326 pinctrl_txd2_default: txd2_default {
1331 pinctrl_txd3_default: txd3_default {
1336 pinctrl_txd4_default: txd4_default {
1341 pinctrl_uart6_default: uart6_default {
1346 pinctrl_usbcki_default: usbcki_default {
1347 function = "USBCKI";
1351 pinctrl_vgabiosrom_default: vgabiosrom_default {
1352 function = "VGABIOSROM";
1353 groups = "VGABIOSROM";
1356 pinctrl_vgahs_default: vgahs_default {
1361 pinctrl_vgavs_default: vgavs_default {
1366 pinctrl_vpi24_default: vpi24_default {
1371 pinctrl_vpo_default: vpo_default {
1376 pinctrl_wdtrst1_default: wdtrst1_default {
1377 function = "WDTRST1";
1381 pinctrl_wdtrst2_default: wdtrst2_default {
1382 function = "WDTRST2";