1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
73 compatible = "jedec,spi-nor";
78 compatible = "jedec,spi-nor";
83 compatible = "jedec,spi-nor";
88 compatible = "jedec,spi-nor";
94 reg = < 0x1e630000 0x18
95 0x30000000 0x10000000 >;
98 compatible = "aspeed,ast2400-spi";
99 clocks = <&syscon ASPEED_CLK_AHB>;
103 compatible = "jedec,spi-nor";
104 spi-max-frequency = <50000000>;
109 vic: interrupt-controller@1e6c0080 {
110 compatible = "aspeed,ast2400-vic";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 valid-sources = <0xffffffff 0x0007ffff>;
114 reg = <0x1e6c0080 0x80>;
117 cvic: copro-interrupt-controller@1e6c2000 {
118 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
119 valid-sources = <0x7fffffff>;
120 reg = <0x1e6c2000 0x80>;
123 mac0: ethernet@1e660000 {
124 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
125 reg = <0x1e660000 0x180>;
127 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
131 mac1: ethernet@1e680000 {
132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
133 reg = <0x1e680000 0x180>;
135 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
139 ehci0: usb@1e6a1000 {
140 compatible = "aspeed,ast2400-ehci", "generic-ehci";
141 reg = <0x1e6a1000 0x100>;
143 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usb2h_default>;
150 compatible = "aspeed,ast2400-uhci", "generic-uhci";
151 reg = <0x1e6b0000 0x100>;
154 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
157 * No default pinmux, it will follow EHCI, use an explicit pinmux
158 * override if you don't enable EHCI
162 vhub: usb-vhub@1e6a0000 {
163 compatible = "aspeed,ast2400-usb-vhub";
164 reg = <0x1e6a0000 0x300>;
166 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
167 aspeed,vhub-downstream-ports = <5>;
168 aspeed,vhub-generic-endpoints = <15>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_usb2d_default>;
175 compatible = "simple-bus";
176 #address-cells = <1>;
180 syscon: syscon@1e6e2000 {
181 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
182 reg = <0x1e6e2000 0x1a8>;
183 #address-cells = <1>;
185 ranges = <0 0x1e6e2000 0x1000>;
189 p2a: p2a-control@2c {
191 compatible = "aspeed,ast2400-p2a-ctrl";
195 pinctrl: pinctrl@80 {
196 reg = <0x80 0x18>, <0xa0 0x10>;
197 compatible = "aspeed,ast2400-pinctrl";
201 rng: hwrng@1e6e2078 {
202 compatible = "timeriomem_rng";
203 reg = <0x1e6e2078 0x4>;
209 compatible = "aspeed,ast2400-adc";
210 reg = <0x1e6e9000 0xb0>;
211 clocks = <&syscon ASPEED_CLK_APB>;
212 resets = <&syscon ASPEED_RESET_ADC>;
213 #io-channel-cells = <1>;
217 sram: sram@1e720000 {
218 compatible = "mmio-sram";
219 reg = <0x1e720000 0x8000>; // 32K
222 sdmmc: sd-controller@1e740000 {
223 compatible = "aspeed,ast2400-sd-controller";
224 reg = <0x1e740000 0x100>;
225 #address-cells = <1>;
227 ranges = <0 0x1e740000 0x10000>;
228 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
232 compatible = "aspeed,ast2400-sdhci";
236 clocks = <&syscon ASPEED_CLK_SDIO>;
241 compatible = "aspeed,ast2400-sdhci";
245 clocks = <&syscon ASPEED_CLK_SDIO>;
250 gpio: gpio@1e780000 {
253 compatible = "aspeed,ast2400-gpio";
254 reg = <0x1e780000 0x1000>;
256 gpio-ranges = <&pinctrl 0 0 220>;
257 clocks = <&syscon ASPEED_CLK_APB>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
262 timer: timer@1e782000 {
263 /* This timer is a Faraday FTTMR010 derivative */
264 compatible = "aspeed,ast2400-timer";
265 reg = <0x1e782000 0x90>;
266 interrupts = <16 17 18 35 36 37 38 39>;
267 clocks = <&syscon ASPEED_CLK_APB>;
268 clock-names = "PCLK";
272 compatible = "aspeed,ast2400-rtc";
273 reg = <0x1e781000 0x18>;
277 uart1: serial@1e783000 {
278 compatible = "ns16550a";
279 reg = <0x1e783000 0x20>;
282 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
283 resets = <&lpc_reset 4>;
288 uart5: serial@1e784000 {
289 compatible = "ns16550a";
290 reg = <0x1e784000 0x20>;
293 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
298 wdt1: watchdog@1e785000 {
299 compatible = "aspeed,ast2400-wdt";
300 reg = <0x1e785000 0x1c>;
301 clocks = <&syscon ASPEED_CLK_APB>;
304 wdt2: watchdog@1e785020 {
305 compatible = "aspeed,ast2400-wdt";
306 reg = <0x1e785020 0x1c>;
307 clocks = <&syscon ASPEED_CLK_APB>;
310 pwm_tacho: pwm-tacho-controller@1e786000 {
311 compatible = "aspeed,ast2400-pwm-tacho";
312 #address-cells = <1>;
314 reg = <0x1e786000 0x1000>;
315 clocks = <&syscon ASPEED_CLK_24M>;
316 resets = <&syscon ASPEED_RESET_PWM>;
320 vuart: serial@1e787000 {
321 compatible = "aspeed,ast2400-vuart";
322 reg = <0x1e787000 0x40>;
325 clocks = <&syscon ASPEED_CLK_APB>;
331 compatible = "aspeed,ast2400-lpc", "simple-mfd";
332 reg = <0x1e789000 0x1000>;
334 #address-cells = <1>;
336 ranges = <0x0 0x1e789000 0x1000>;
339 compatible = "aspeed,ast2400-lpc-bmc";
343 lpc_host: lpc-host@80 {
344 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
348 #address-cells = <1>;
350 ranges = <0x0 0x80 0x1e0>;
352 lpc_ctrl: lpc-ctrl@0 {
353 compatible = "aspeed,ast2400-lpc-ctrl";
355 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
359 lpc_snoop: lpc-snoop@10 {
360 compatible = "aspeed,ast2400-lpc-snoop";
367 compatible = "aspeed,ast2400-lhc";
368 reg = <0x20 0x24 0x48 0x8>;
371 lpc_reset: reset-controller@18 {
372 compatible = "aspeed,ast2400-lpc-reset";
378 compatible = "aspeed,ast2400-ibt-bmc";
386 uart2: serial@1e78d000 {
387 compatible = "ns16550a";
388 reg = <0x1e78d000 0x20>;
391 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
392 resets = <&lpc_reset 5>;
397 uart3: serial@1e78e000 {
398 compatible = "ns16550a";
399 reg = <0x1e78e000 0x20>;
402 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
403 resets = <&lpc_reset 6>;
408 uart4: serial@1e78f000 {
409 compatible = "ns16550a";
410 reg = <0x1e78f000 0x20>;
413 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
414 resets = <&lpc_reset 7>;
420 compatible = "simple-bus";
421 #address-cells = <1>;
423 ranges = <0 0x1e78a000 0x1000>;
430 i2c_ic: interrupt-controller@0 {
431 #interrupt-cells = <1>;
432 compatible = "aspeed,ast2400-i2c-ic";
435 interrupt-controller;
439 #address-cells = <1>;
441 #interrupt-cells = <1>;
444 compatible = "aspeed,ast2400-i2c-bus";
445 clocks = <&syscon ASPEED_CLK_APB>;
446 resets = <&syscon ASPEED_RESET_I2C>;
447 bus-frequency = <100000>;
449 interrupt-parent = <&i2c_ic>;
451 /* Does not need pinctrl properties */
455 #address-cells = <1>;
457 #interrupt-cells = <1>;
460 compatible = "aspeed,ast2400-i2c-bus";
461 clocks = <&syscon ASPEED_CLK_APB>;
462 resets = <&syscon ASPEED_RESET_I2C>;
463 bus-frequency = <100000>;
465 interrupt-parent = <&i2c_ic>;
467 /* Does not need pinctrl properties */
471 #address-cells = <1>;
473 #interrupt-cells = <1>;
476 compatible = "aspeed,ast2400-i2c-bus";
477 clocks = <&syscon ASPEED_CLK_APB>;
478 resets = <&syscon ASPEED_RESET_I2C>;
479 bus-frequency = <100000>;
481 interrupt-parent = <&i2c_ic>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&pinctrl_i2c3_default>;
488 #address-cells = <1>;
490 #interrupt-cells = <1>;
493 compatible = "aspeed,ast2400-i2c-bus";
494 clocks = <&syscon ASPEED_CLK_APB>;
495 resets = <&syscon ASPEED_RESET_I2C>;
496 bus-frequency = <100000>;
498 interrupt-parent = <&i2c_ic>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_i2c4_default>;
505 #address-cells = <1>;
507 #interrupt-cells = <1>;
510 compatible = "aspeed,ast2400-i2c-bus";
511 clocks = <&syscon ASPEED_CLK_APB>;
512 resets = <&syscon ASPEED_RESET_I2C>;
513 bus-frequency = <100000>;
515 interrupt-parent = <&i2c_ic>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_i2c5_default>;
522 #address-cells = <1>;
524 #interrupt-cells = <1>;
527 compatible = "aspeed,ast2400-i2c-bus";
528 clocks = <&syscon ASPEED_CLK_APB>;
529 resets = <&syscon ASPEED_RESET_I2C>;
530 bus-frequency = <100000>;
532 interrupt-parent = <&i2c_ic>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_i2c6_default>;
539 #address-cells = <1>;
541 #interrupt-cells = <1>;
544 compatible = "aspeed,ast2400-i2c-bus";
545 clocks = <&syscon ASPEED_CLK_APB>;
546 resets = <&syscon ASPEED_RESET_I2C>;
547 bus-frequency = <100000>;
549 interrupt-parent = <&i2c_ic>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_i2c7_default>;
556 #address-cells = <1>;
558 #interrupt-cells = <1>;
561 compatible = "aspeed,ast2400-i2c-bus";
562 clocks = <&syscon ASPEED_CLK_APB>;
563 resets = <&syscon ASPEED_RESET_I2C>;
564 bus-frequency = <100000>;
566 interrupt-parent = <&i2c_ic>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_i2c8_default>;
573 #address-cells = <1>;
575 #interrupt-cells = <1>;
578 compatible = "aspeed,ast2400-i2c-bus";
579 clocks = <&syscon ASPEED_CLK_APB>;
580 resets = <&syscon ASPEED_RESET_I2C>;
581 bus-frequency = <100000>;
583 interrupt-parent = <&i2c_ic>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_i2c9_default>;
590 #address-cells = <1>;
592 #interrupt-cells = <1>;
595 compatible = "aspeed,ast2400-i2c-bus";
596 clocks = <&syscon ASPEED_CLK_APB>;
597 resets = <&syscon ASPEED_RESET_I2C>;
598 bus-frequency = <100000>;
600 interrupt-parent = <&i2c_ic>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_i2c10_default>;
607 #address-cells = <1>;
609 #interrupt-cells = <1>;
612 compatible = "aspeed,ast2400-i2c-bus";
613 clocks = <&syscon ASPEED_CLK_APB>;
614 resets = <&syscon ASPEED_RESET_I2C>;
615 bus-frequency = <100000>;
617 interrupt-parent = <&i2c_ic>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_i2c11_default>;
624 #address-cells = <1>;
626 #interrupt-cells = <1>;
629 compatible = "aspeed,ast2400-i2c-bus";
630 clocks = <&syscon ASPEED_CLK_APB>;
631 resets = <&syscon ASPEED_RESET_I2C>;
632 bus-frequency = <100000>;
634 interrupt-parent = <&i2c_ic>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_i2c12_default>;
641 #address-cells = <1>;
643 #interrupt-cells = <1>;
646 compatible = "aspeed,ast2400-i2c-bus";
647 clocks = <&syscon ASPEED_CLK_APB>;
648 resets = <&syscon ASPEED_RESET_I2C>;
649 bus-frequency = <100000>;
651 interrupt-parent = <&i2c_ic>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_i2c13_default>;
658 #address-cells = <1>;
660 #interrupt-cells = <1>;
663 compatible = "aspeed,ast2400-i2c-bus";
664 clocks = <&syscon ASPEED_CLK_APB>;
665 resets = <&syscon ASPEED_RESET_I2C>;
666 bus-frequency = <100000>;
668 interrupt-parent = <&i2c_ic>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&pinctrl_i2c14_default>;
676 pinctrl_acpi_default: acpi_default {
681 pinctrl_adc0_default: adc0_default {
686 pinctrl_adc1_default: adc1_default {
691 pinctrl_adc10_default: adc10_default {
696 pinctrl_adc11_default: adc11_default {
701 pinctrl_adc12_default: adc12_default {
706 pinctrl_adc13_default: adc13_default {
711 pinctrl_adc14_default: adc14_default {
716 pinctrl_adc15_default: adc15_default {
721 pinctrl_adc2_default: adc2_default {
726 pinctrl_adc3_default: adc3_default {
731 pinctrl_adc4_default: adc4_default {
736 pinctrl_adc5_default: adc5_default {
741 pinctrl_adc6_default: adc6_default {
746 pinctrl_adc7_default: adc7_default {
751 pinctrl_adc8_default: adc8_default {
756 pinctrl_adc9_default: adc9_default {
761 pinctrl_bmcint_default: bmcint_default {
766 pinctrl_ddcclk_default: ddcclk_default {
771 pinctrl_ddcdat_default: ddcdat_default {
776 pinctrl_extrst_default: extrst_default {
781 pinctrl_flack_default: flack_default {
786 pinctrl_flbusy_default: flbusy_default {
791 pinctrl_flwp_default: flwp_default {
796 pinctrl_gpid_default: gpid_default {
801 pinctrl_gpid0_default: gpid0_default {
806 pinctrl_gpid2_default: gpid2_default {
811 pinctrl_gpid4_default: gpid4_default {
816 pinctrl_gpid6_default: gpid6_default {
821 pinctrl_gpie0_default: gpie0_default {
826 pinctrl_gpie2_default: gpie2_default {
831 pinctrl_gpie4_default: gpie4_default {
836 pinctrl_gpie6_default: gpie6_default {
841 pinctrl_i2c10_default: i2c10_default {
846 pinctrl_i2c11_default: i2c11_default {
851 pinctrl_i2c12_default: i2c12_default {
856 pinctrl_i2c13_default: i2c13_default {
861 pinctrl_i2c14_default: i2c14_default {
866 pinctrl_i2c3_default: i2c3_default {
871 pinctrl_i2c4_default: i2c4_default {
876 pinctrl_i2c5_default: i2c5_default {
881 pinctrl_i2c6_default: i2c6_default {
886 pinctrl_i2c7_default: i2c7_default {
891 pinctrl_i2c8_default: i2c8_default {
896 pinctrl_i2c9_default: i2c9_default {
901 pinctrl_lpcpd_default: lpcpd_default {
906 pinctrl_lpcpme_default: lpcpme_default {
911 pinctrl_lpcrst_default: lpcrst_default {
916 pinctrl_lpcsmi_default: lpcsmi_default {
921 pinctrl_mac1link_default: mac1link_default {
922 function = "MAC1LINK";
926 pinctrl_mac2link_default: mac2link_default {
927 function = "MAC2LINK";
931 pinctrl_mdio1_default: mdio1_default {
936 pinctrl_mdio2_default: mdio2_default {
941 pinctrl_ncts1_default: ncts1_default {
946 pinctrl_ncts2_default: ncts2_default {
951 pinctrl_ncts3_default: ncts3_default {
956 pinctrl_ncts4_default: ncts4_default {
961 pinctrl_ndcd1_default: ndcd1_default {
966 pinctrl_ndcd2_default: ndcd2_default {
971 pinctrl_ndcd3_default: ndcd3_default {
976 pinctrl_ndcd4_default: ndcd4_default {
981 pinctrl_ndsr1_default: ndsr1_default {
986 pinctrl_ndsr2_default: ndsr2_default {
991 pinctrl_ndsr3_default: ndsr3_default {
996 pinctrl_ndsr4_default: ndsr4_default {
1001 pinctrl_ndtr1_default: ndtr1_default {
1006 pinctrl_ndtr2_default: ndtr2_default {
1011 pinctrl_ndtr3_default: ndtr3_default {
1016 pinctrl_ndtr4_default: ndtr4_default {
1021 pinctrl_ndts4_default: ndts4_default {
1026 pinctrl_nri1_default: nri1_default {
1031 pinctrl_nri2_default: nri2_default {
1036 pinctrl_nri3_default: nri3_default {
1041 pinctrl_nri4_default: nri4_default {
1046 pinctrl_nrts1_default: nrts1_default {
1051 pinctrl_nrts2_default: nrts2_default {
1056 pinctrl_nrts3_default: nrts3_default {
1061 pinctrl_oscclk_default: oscclk_default {
1062 function = "OSCCLK";
1066 pinctrl_pwm0_default: pwm0_default {
1071 pinctrl_pwm1_default: pwm1_default {
1076 pinctrl_pwm2_default: pwm2_default {
1081 pinctrl_pwm3_default: pwm3_default {
1086 pinctrl_pwm4_default: pwm4_default {
1091 pinctrl_pwm5_default: pwm5_default {
1096 pinctrl_pwm6_default: pwm6_default {
1101 pinctrl_pwm7_default: pwm7_default {
1106 pinctrl_rgmii1_default: rgmii1_default {
1107 function = "RGMII1";
1111 pinctrl_rgmii2_default: rgmii2_default {
1112 function = "RGMII2";
1116 pinctrl_rmii1_default: rmii1_default {
1121 pinctrl_rmii2_default: rmii2_default {
1126 pinctrl_rom16_default: rom16_default {
1131 pinctrl_rom8_default: rom8_default {
1136 pinctrl_romcs1_default: romcs1_default {
1137 function = "ROMCS1";
1141 pinctrl_romcs2_default: romcs2_default {
1142 function = "ROMCS2";
1146 pinctrl_romcs3_default: romcs3_default {
1147 function = "ROMCS3";
1151 pinctrl_romcs4_default: romcs4_default {
1152 function = "ROMCS4";
1156 pinctrl_rxd1_default: rxd1_default {
1161 pinctrl_rxd2_default: rxd2_default {
1166 pinctrl_rxd3_default: rxd3_default {
1171 pinctrl_rxd4_default: rxd4_default {
1176 pinctrl_salt1_default: salt1_default {
1181 pinctrl_salt2_default: salt2_default {
1186 pinctrl_salt3_default: salt3_default {
1191 pinctrl_salt4_default: salt4_default {
1196 pinctrl_sd1_default: sd1_default {
1201 pinctrl_sd2_default: sd2_default {
1206 pinctrl_sgpmck_default: sgpmck_default {
1207 function = "SGPMCK";
1211 pinctrl_sgpmi_default: sgpmi_default {
1216 pinctrl_sgpmld_default: sgpmld_default {
1217 function = "SGPMLD";
1221 pinctrl_sgpmo_default: sgpmo_default {
1226 pinctrl_sgpsck_default: sgpsck_default {
1227 function = "SGPSCK";
1231 pinctrl_sgpsi0_default: sgpsi0_default {
1232 function = "SGPSI0";
1236 pinctrl_sgpsi1_default: sgpsi1_default {
1237 function = "SGPSI1";
1241 pinctrl_sgpsld_default: sgpsld_default {
1242 function = "SGPSLD";
1246 pinctrl_sioonctrl_default: sioonctrl_default {
1247 function = "SIOONCTRL";
1248 groups = "SIOONCTRL";
1251 pinctrl_siopbi_default: siopbi_default {
1252 function = "SIOPBI";
1256 pinctrl_siopbo_default: siopbo_default {
1257 function = "SIOPBO";
1261 pinctrl_siopwreq_default: siopwreq_default {
1262 function = "SIOPWREQ";
1263 groups = "SIOPWREQ";
1266 pinctrl_siopwrgd_default: siopwrgd_default {
1267 function = "SIOPWRGD";
1268 groups = "SIOPWRGD";
1271 pinctrl_sios3_default: sios3_default {
1276 pinctrl_sios5_default: sios5_default {
1281 pinctrl_siosci_default: siosci_default {
1282 function = "SIOSCI";
1286 pinctrl_spi1_default: spi1_default {
1291 pinctrl_spi1debug_default: spi1debug_default {
1292 function = "SPI1DEBUG";
1293 groups = "SPI1DEBUG";
1296 pinctrl_spi1passthru_default: spi1passthru_default {
1297 function = "SPI1PASSTHRU";
1298 groups = "SPI1PASSTHRU";
1301 pinctrl_spics1_default: spics1_default {
1302 function = "SPICS1";
1306 pinctrl_timer3_default: timer3_default {
1307 function = "TIMER3";
1311 pinctrl_timer4_default: timer4_default {
1312 function = "TIMER4";
1316 pinctrl_timer5_default: timer5_default {
1317 function = "TIMER5";
1321 pinctrl_timer6_default: timer6_default {
1322 function = "TIMER6";
1326 pinctrl_timer7_default: timer7_default {
1327 function = "TIMER7";
1331 pinctrl_timer8_default: timer8_default {
1332 function = "TIMER8";
1336 pinctrl_txd1_default: txd1_default {
1341 pinctrl_txd2_default: txd2_default {
1346 pinctrl_txd3_default: txd3_default {
1351 pinctrl_txd4_default: txd4_default {
1356 pinctrl_uart6_default: uart6_default {
1361 pinctrl_usbcki_default: usbcki_default {
1362 function = "USBCKI";
1366 pinctrl_usb2h_default: usb2h_default {
1367 function = "USB2H1";
1371 pinctrl_usb2d_default: usb2d_default {
1372 function = "USB2D1";
1376 pinctrl_vgabios_rom_default: vgabios_rom_default {
1377 function = "VGABIOS_ROM";
1378 groups = "VGABIOS_ROM";
1381 pinctrl_vgahs_default: vgahs_default {
1386 pinctrl_vgavs_default: vgavs_default {
1391 pinctrl_vpi18_default: vpi18_default {
1396 pinctrl_vpi24_default: vpi24_default {
1401 pinctrl_vpi30_default: vpi30_default {
1406 pinctrl_vpo12_default: vpo12_default {
1411 pinctrl_vpo24_default: vpo24_default {
1416 pinctrl_wdtrst1_default: wdtrst1_default {
1417 function = "WDTRST1";
1421 pinctrl_wdtrst2_default: wdtrst2_default {
1422 function = "WDTRST2";