1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
73 compatible = "jedec,spi-nor";
78 compatible = "jedec,spi-nor";
83 compatible = "jedec,spi-nor";
88 compatible = "jedec,spi-nor";
94 reg = < 0x1e630000 0x18
95 0x30000000 0x10000000 >;
98 compatible = "aspeed,ast2400-spi";
99 clocks = <&syscon ASPEED_CLK_AHB>;
103 compatible = "jedec,spi-nor";
104 spi-max-frequency = <50000000>;
109 vic: interrupt-controller@1e6c0080 {
110 compatible = "aspeed,ast2400-vic";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 valid-sources = <0xffffffff 0x0007ffff>;
114 reg = <0x1e6c0080 0x80>;
117 cvic: copro-interrupt-controller@1e6c2000 {
118 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
119 valid-sources = <0x7fffffff>;
120 reg = <0x1e6c2000 0x80>;
123 mac0: ethernet@1e660000 {
124 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
125 reg = <0x1e660000 0x180>;
127 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
131 mac1: ethernet@1e680000 {
132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
133 reg = <0x1e680000 0x180>;
135 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
139 ehci0: usb@1e6a1000 {
140 compatible = "aspeed,ast2400-ehci", "generic-ehci";
141 reg = <0x1e6a1000 0x100>;
143 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usb2h_default>;
150 compatible = "aspeed,ast2400-uhci", "generic-uhci";
151 reg = <0x1e6b0000 0x100>;
154 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
157 * No default pinmux, it will follow EHCI, use an explicit pinmux
158 * override if you don't enable EHCI
162 vhub: usb-vhub@1e6a0000 {
163 compatible = "aspeed,ast2400-usb-vhub";
164 reg = <0x1e6a0000 0x300>;
166 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
167 aspeed,vhub-downstream-ports = <5>;
168 aspeed,vhub-generic-endpoints = <15>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_usb2d_default>;
175 compatible = "simple-bus";
176 #address-cells = <1>;
180 syscon: syscon@1e6e2000 {
181 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
182 reg = <0x1e6e2000 0x1a8>;
183 #address-cells = <1>;
185 ranges = <0 0x1e6e2000 0x1000>;
189 p2a: p2a-control@2c {
191 compatible = "aspeed,ast2400-p2a-ctrl";
195 pinctrl: pinctrl@80 {
196 reg = <0x80 0x18>, <0xa0 0x10>;
197 compatible = "aspeed,ast2400-pinctrl";
201 rng: hwrng@1e6e2078 {
202 compatible = "timeriomem_rng";
203 reg = <0x1e6e2078 0x4>;
209 compatible = "aspeed,ast2400-adc";
210 reg = <0x1e6e9000 0xb0>;
211 clocks = <&syscon ASPEED_CLK_APB>;
212 resets = <&syscon ASPEED_RESET_ADC>;
213 #io-channel-cells = <1>;
217 sram: sram@1e720000 {
218 compatible = "mmio-sram";
219 reg = <0x1e720000 0x8000>; // 32K
222 video: video@1e700000 {
223 compatible = "aspeed,ast2400-video-engine";
224 reg = <0x1e700000 0x1000>;
225 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
226 <&syscon ASPEED_CLK_GATE_ECLK>;
227 clock-names = "vclk", "eclk";
232 sdmmc: sd-controller@1e740000 {
233 compatible = "aspeed,ast2400-sd-controller";
234 reg = <0x1e740000 0x100>;
235 #address-cells = <1>;
237 ranges = <0 0x1e740000 0x10000>;
238 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
242 compatible = "aspeed,ast2400-sdhci";
246 clocks = <&syscon ASPEED_CLK_SDIO>;
251 compatible = "aspeed,ast2400-sdhci";
255 clocks = <&syscon ASPEED_CLK_SDIO>;
260 gpio: gpio@1e780000 {
263 compatible = "aspeed,ast2400-gpio";
264 reg = <0x1e780000 0x1000>;
266 gpio-ranges = <&pinctrl 0 0 220>;
267 clocks = <&syscon ASPEED_CLK_APB>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
272 timer: timer@1e782000 {
273 /* This timer is a Faraday FTTMR010 derivative */
274 compatible = "aspeed,ast2400-timer";
275 reg = <0x1e782000 0x90>;
276 interrupts = <16 17 18 35 36 37 38 39>;
277 clocks = <&syscon ASPEED_CLK_APB>;
278 clock-names = "PCLK";
282 compatible = "aspeed,ast2400-rtc";
283 reg = <0x1e781000 0x18>;
287 uart1: serial@1e783000 {
288 compatible = "ns16550a";
289 reg = <0x1e783000 0x20>;
292 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
293 resets = <&lpc_reset 4>;
298 uart5: serial@1e784000 {
299 compatible = "ns16550a";
300 reg = <0x1e784000 0x20>;
303 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
308 wdt1: watchdog@1e785000 {
309 compatible = "aspeed,ast2400-wdt";
310 reg = <0x1e785000 0x1c>;
311 clocks = <&syscon ASPEED_CLK_APB>;
314 wdt2: watchdog@1e785020 {
315 compatible = "aspeed,ast2400-wdt";
316 reg = <0x1e785020 0x1c>;
317 clocks = <&syscon ASPEED_CLK_APB>;
320 pwm_tacho: pwm-tacho-controller@1e786000 {
321 compatible = "aspeed,ast2400-pwm-tacho";
322 #address-cells = <1>;
324 reg = <0x1e786000 0x1000>;
325 clocks = <&syscon ASPEED_CLK_24M>;
326 resets = <&syscon ASPEED_RESET_PWM>;
330 vuart: serial@1e787000 {
331 compatible = "aspeed,ast2400-vuart";
332 reg = <0x1e787000 0x40>;
335 clocks = <&syscon ASPEED_CLK_APB>;
341 compatible = "aspeed,ast2400-lpc", "simple-mfd";
342 reg = <0x1e789000 0x1000>;
344 #address-cells = <1>;
346 ranges = <0x0 0x1e789000 0x1000>;
349 compatible = "aspeed,ast2400-lpc-bmc";
353 lpc_host: lpc-host@80 {
354 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
358 #address-cells = <1>;
360 ranges = <0x0 0x80 0x1e0>;
362 lpc_ctrl: lpc-ctrl@0 {
363 compatible = "aspeed,ast2400-lpc-ctrl";
365 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
369 lpc_snoop: lpc-snoop@10 {
370 compatible = "aspeed,ast2400-lpc-snoop";
377 compatible = "aspeed,ast2400-lhc";
378 reg = <0x20 0x24 0x48 0x8>;
381 lpc_reset: reset-controller@18 {
382 compatible = "aspeed,ast2400-lpc-reset";
388 compatible = "aspeed,ast2400-ibt-bmc";
396 uart2: serial@1e78d000 {
397 compatible = "ns16550a";
398 reg = <0x1e78d000 0x20>;
401 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
402 resets = <&lpc_reset 5>;
407 uart3: serial@1e78e000 {
408 compatible = "ns16550a";
409 reg = <0x1e78e000 0x20>;
412 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
413 resets = <&lpc_reset 6>;
418 uart4: serial@1e78f000 {
419 compatible = "ns16550a";
420 reg = <0x1e78f000 0x20>;
423 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
424 resets = <&lpc_reset 7>;
430 compatible = "simple-bus";
431 #address-cells = <1>;
433 ranges = <0 0x1e78a000 0x1000>;
440 i2c_ic: interrupt-controller@0 {
441 #interrupt-cells = <1>;
442 compatible = "aspeed,ast2400-i2c-ic";
445 interrupt-controller;
449 #address-cells = <1>;
451 #interrupt-cells = <1>;
454 compatible = "aspeed,ast2400-i2c-bus";
455 clocks = <&syscon ASPEED_CLK_APB>;
456 resets = <&syscon ASPEED_RESET_I2C>;
457 bus-frequency = <100000>;
459 interrupt-parent = <&i2c_ic>;
461 /* Does not need pinctrl properties */
465 #address-cells = <1>;
467 #interrupt-cells = <1>;
470 compatible = "aspeed,ast2400-i2c-bus";
471 clocks = <&syscon ASPEED_CLK_APB>;
472 resets = <&syscon ASPEED_RESET_I2C>;
473 bus-frequency = <100000>;
475 interrupt-parent = <&i2c_ic>;
477 /* Does not need pinctrl properties */
481 #address-cells = <1>;
483 #interrupt-cells = <1>;
486 compatible = "aspeed,ast2400-i2c-bus";
487 clocks = <&syscon ASPEED_CLK_APB>;
488 resets = <&syscon ASPEED_RESET_I2C>;
489 bus-frequency = <100000>;
491 interrupt-parent = <&i2c_ic>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_i2c3_default>;
498 #address-cells = <1>;
500 #interrupt-cells = <1>;
503 compatible = "aspeed,ast2400-i2c-bus";
504 clocks = <&syscon ASPEED_CLK_APB>;
505 resets = <&syscon ASPEED_RESET_I2C>;
506 bus-frequency = <100000>;
508 interrupt-parent = <&i2c_ic>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_i2c4_default>;
515 #address-cells = <1>;
517 #interrupt-cells = <1>;
520 compatible = "aspeed,ast2400-i2c-bus";
521 clocks = <&syscon ASPEED_CLK_APB>;
522 resets = <&syscon ASPEED_RESET_I2C>;
523 bus-frequency = <100000>;
525 interrupt-parent = <&i2c_ic>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_i2c5_default>;
532 #address-cells = <1>;
534 #interrupt-cells = <1>;
537 compatible = "aspeed,ast2400-i2c-bus";
538 clocks = <&syscon ASPEED_CLK_APB>;
539 resets = <&syscon ASPEED_RESET_I2C>;
540 bus-frequency = <100000>;
542 interrupt-parent = <&i2c_ic>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_i2c6_default>;
549 #address-cells = <1>;
551 #interrupt-cells = <1>;
554 compatible = "aspeed,ast2400-i2c-bus";
555 clocks = <&syscon ASPEED_CLK_APB>;
556 resets = <&syscon ASPEED_RESET_I2C>;
557 bus-frequency = <100000>;
559 interrupt-parent = <&i2c_ic>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_i2c7_default>;
566 #address-cells = <1>;
568 #interrupt-cells = <1>;
571 compatible = "aspeed,ast2400-i2c-bus";
572 clocks = <&syscon ASPEED_CLK_APB>;
573 resets = <&syscon ASPEED_RESET_I2C>;
574 bus-frequency = <100000>;
576 interrupt-parent = <&i2c_ic>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_i2c8_default>;
583 #address-cells = <1>;
585 #interrupt-cells = <1>;
588 compatible = "aspeed,ast2400-i2c-bus";
589 clocks = <&syscon ASPEED_CLK_APB>;
590 resets = <&syscon ASPEED_RESET_I2C>;
591 bus-frequency = <100000>;
593 interrupt-parent = <&i2c_ic>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_i2c9_default>;
600 #address-cells = <1>;
602 #interrupt-cells = <1>;
605 compatible = "aspeed,ast2400-i2c-bus";
606 clocks = <&syscon ASPEED_CLK_APB>;
607 resets = <&syscon ASPEED_RESET_I2C>;
608 bus-frequency = <100000>;
610 interrupt-parent = <&i2c_ic>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_i2c10_default>;
617 #address-cells = <1>;
619 #interrupt-cells = <1>;
622 compatible = "aspeed,ast2400-i2c-bus";
623 clocks = <&syscon ASPEED_CLK_APB>;
624 resets = <&syscon ASPEED_RESET_I2C>;
625 bus-frequency = <100000>;
627 interrupt-parent = <&i2c_ic>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_i2c11_default>;
634 #address-cells = <1>;
636 #interrupt-cells = <1>;
639 compatible = "aspeed,ast2400-i2c-bus";
640 clocks = <&syscon ASPEED_CLK_APB>;
641 resets = <&syscon ASPEED_RESET_I2C>;
642 bus-frequency = <100000>;
644 interrupt-parent = <&i2c_ic>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_i2c12_default>;
651 #address-cells = <1>;
653 #interrupt-cells = <1>;
656 compatible = "aspeed,ast2400-i2c-bus";
657 clocks = <&syscon ASPEED_CLK_APB>;
658 resets = <&syscon ASPEED_RESET_I2C>;
659 bus-frequency = <100000>;
661 interrupt-parent = <&i2c_ic>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&pinctrl_i2c13_default>;
668 #address-cells = <1>;
670 #interrupt-cells = <1>;
673 compatible = "aspeed,ast2400-i2c-bus";
674 clocks = <&syscon ASPEED_CLK_APB>;
675 resets = <&syscon ASPEED_RESET_I2C>;
676 bus-frequency = <100000>;
678 interrupt-parent = <&i2c_ic>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_i2c14_default>;
686 pinctrl_acpi_default: acpi_default {
691 pinctrl_adc0_default: adc0_default {
696 pinctrl_adc1_default: adc1_default {
701 pinctrl_adc10_default: adc10_default {
706 pinctrl_adc11_default: adc11_default {
711 pinctrl_adc12_default: adc12_default {
716 pinctrl_adc13_default: adc13_default {
721 pinctrl_adc14_default: adc14_default {
726 pinctrl_adc15_default: adc15_default {
731 pinctrl_adc2_default: adc2_default {
736 pinctrl_adc3_default: adc3_default {
741 pinctrl_adc4_default: adc4_default {
746 pinctrl_adc5_default: adc5_default {
751 pinctrl_adc6_default: adc6_default {
756 pinctrl_adc7_default: adc7_default {
761 pinctrl_adc8_default: adc8_default {
766 pinctrl_adc9_default: adc9_default {
771 pinctrl_bmcint_default: bmcint_default {
776 pinctrl_ddcclk_default: ddcclk_default {
781 pinctrl_ddcdat_default: ddcdat_default {
786 pinctrl_extrst_default: extrst_default {
791 pinctrl_flack_default: flack_default {
796 pinctrl_flbusy_default: flbusy_default {
801 pinctrl_flwp_default: flwp_default {
806 pinctrl_gpid_default: gpid_default {
811 pinctrl_gpid0_default: gpid0_default {
816 pinctrl_gpid2_default: gpid2_default {
821 pinctrl_gpid4_default: gpid4_default {
826 pinctrl_gpid6_default: gpid6_default {
831 pinctrl_gpie0_default: gpie0_default {
836 pinctrl_gpie2_default: gpie2_default {
841 pinctrl_gpie4_default: gpie4_default {
846 pinctrl_gpie6_default: gpie6_default {
851 pinctrl_i2c10_default: i2c10_default {
856 pinctrl_i2c11_default: i2c11_default {
861 pinctrl_i2c12_default: i2c12_default {
866 pinctrl_i2c13_default: i2c13_default {
871 pinctrl_i2c14_default: i2c14_default {
876 pinctrl_i2c3_default: i2c3_default {
881 pinctrl_i2c4_default: i2c4_default {
886 pinctrl_i2c5_default: i2c5_default {
891 pinctrl_i2c6_default: i2c6_default {
896 pinctrl_i2c7_default: i2c7_default {
901 pinctrl_i2c8_default: i2c8_default {
906 pinctrl_i2c9_default: i2c9_default {
911 pinctrl_lpcpd_default: lpcpd_default {
916 pinctrl_lpcpme_default: lpcpme_default {
921 pinctrl_lpcrst_default: lpcrst_default {
926 pinctrl_lpcsmi_default: lpcsmi_default {
931 pinctrl_mac1link_default: mac1link_default {
932 function = "MAC1LINK";
936 pinctrl_mac2link_default: mac2link_default {
937 function = "MAC2LINK";
941 pinctrl_mdio1_default: mdio1_default {
946 pinctrl_mdio2_default: mdio2_default {
951 pinctrl_ncts1_default: ncts1_default {
956 pinctrl_ncts2_default: ncts2_default {
961 pinctrl_ncts3_default: ncts3_default {
966 pinctrl_ncts4_default: ncts4_default {
971 pinctrl_ndcd1_default: ndcd1_default {
976 pinctrl_ndcd2_default: ndcd2_default {
981 pinctrl_ndcd3_default: ndcd3_default {
986 pinctrl_ndcd4_default: ndcd4_default {
991 pinctrl_ndsr1_default: ndsr1_default {
996 pinctrl_ndsr2_default: ndsr2_default {
1001 pinctrl_ndsr3_default: ndsr3_default {
1006 pinctrl_ndsr4_default: ndsr4_default {
1011 pinctrl_ndtr1_default: ndtr1_default {
1016 pinctrl_ndtr2_default: ndtr2_default {
1021 pinctrl_ndtr3_default: ndtr3_default {
1026 pinctrl_ndtr4_default: ndtr4_default {
1031 pinctrl_ndts4_default: ndts4_default {
1036 pinctrl_nri1_default: nri1_default {
1041 pinctrl_nri2_default: nri2_default {
1046 pinctrl_nri3_default: nri3_default {
1051 pinctrl_nri4_default: nri4_default {
1056 pinctrl_nrts1_default: nrts1_default {
1061 pinctrl_nrts2_default: nrts2_default {
1066 pinctrl_nrts3_default: nrts3_default {
1071 pinctrl_oscclk_default: oscclk_default {
1072 function = "OSCCLK";
1076 pinctrl_pwm0_default: pwm0_default {
1081 pinctrl_pwm1_default: pwm1_default {
1086 pinctrl_pwm2_default: pwm2_default {
1091 pinctrl_pwm3_default: pwm3_default {
1096 pinctrl_pwm4_default: pwm4_default {
1101 pinctrl_pwm5_default: pwm5_default {
1106 pinctrl_pwm6_default: pwm6_default {
1111 pinctrl_pwm7_default: pwm7_default {
1116 pinctrl_rgmii1_default: rgmii1_default {
1117 function = "RGMII1";
1121 pinctrl_rgmii2_default: rgmii2_default {
1122 function = "RGMII2";
1126 pinctrl_rmii1_default: rmii1_default {
1131 pinctrl_rmii2_default: rmii2_default {
1136 pinctrl_rom16_default: rom16_default {
1141 pinctrl_rom8_default: rom8_default {
1146 pinctrl_romcs1_default: romcs1_default {
1147 function = "ROMCS1";
1151 pinctrl_romcs2_default: romcs2_default {
1152 function = "ROMCS2";
1156 pinctrl_romcs3_default: romcs3_default {
1157 function = "ROMCS3";
1161 pinctrl_romcs4_default: romcs4_default {
1162 function = "ROMCS4";
1166 pinctrl_rxd1_default: rxd1_default {
1171 pinctrl_rxd2_default: rxd2_default {
1176 pinctrl_rxd3_default: rxd3_default {
1181 pinctrl_rxd4_default: rxd4_default {
1186 pinctrl_salt1_default: salt1_default {
1191 pinctrl_salt2_default: salt2_default {
1196 pinctrl_salt3_default: salt3_default {
1201 pinctrl_salt4_default: salt4_default {
1206 pinctrl_sd1_default: sd1_default {
1211 pinctrl_sd2_default: sd2_default {
1216 pinctrl_sgpmck_default: sgpmck_default {
1217 function = "SGPMCK";
1221 pinctrl_sgpmi_default: sgpmi_default {
1226 pinctrl_sgpmld_default: sgpmld_default {
1227 function = "SGPMLD";
1231 pinctrl_sgpmo_default: sgpmo_default {
1236 pinctrl_sgpsck_default: sgpsck_default {
1237 function = "SGPSCK";
1241 pinctrl_sgpsi0_default: sgpsi0_default {
1242 function = "SGPSI0";
1246 pinctrl_sgpsi1_default: sgpsi1_default {
1247 function = "SGPSI1";
1251 pinctrl_sgpsld_default: sgpsld_default {
1252 function = "SGPSLD";
1256 pinctrl_sioonctrl_default: sioonctrl_default {
1257 function = "SIOONCTRL";
1258 groups = "SIOONCTRL";
1261 pinctrl_siopbi_default: siopbi_default {
1262 function = "SIOPBI";
1266 pinctrl_siopbo_default: siopbo_default {
1267 function = "SIOPBO";
1271 pinctrl_siopwreq_default: siopwreq_default {
1272 function = "SIOPWREQ";
1273 groups = "SIOPWREQ";
1276 pinctrl_siopwrgd_default: siopwrgd_default {
1277 function = "SIOPWRGD";
1278 groups = "SIOPWRGD";
1281 pinctrl_sios3_default: sios3_default {
1286 pinctrl_sios5_default: sios5_default {
1291 pinctrl_siosci_default: siosci_default {
1292 function = "SIOSCI";
1296 pinctrl_spi1_default: spi1_default {
1301 pinctrl_spi1debug_default: spi1debug_default {
1302 function = "SPI1DEBUG";
1303 groups = "SPI1DEBUG";
1306 pinctrl_spi1passthru_default: spi1passthru_default {
1307 function = "SPI1PASSTHRU";
1308 groups = "SPI1PASSTHRU";
1311 pinctrl_spics1_default: spics1_default {
1312 function = "SPICS1";
1316 pinctrl_timer3_default: timer3_default {
1317 function = "TIMER3";
1321 pinctrl_timer4_default: timer4_default {
1322 function = "TIMER4";
1326 pinctrl_timer5_default: timer5_default {
1327 function = "TIMER5";
1331 pinctrl_timer6_default: timer6_default {
1332 function = "TIMER6";
1336 pinctrl_timer7_default: timer7_default {
1337 function = "TIMER7";
1341 pinctrl_timer8_default: timer8_default {
1342 function = "TIMER8";
1346 pinctrl_txd1_default: txd1_default {
1351 pinctrl_txd2_default: txd2_default {
1356 pinctrl_txd3_default: txd3_default {
1361 pinctrl_txd4_default: txd4_default {
1366 pinctrl_uart6_default: uart6_default {
1371 pinctrl_usbcki_default: usbcki_default {
1372 function = "USBCKI";
1376 pinctrl_usb2h_default: usb2h_default {
1377 function = "USB2H1";
1381 pinctrl_usb2d_default: usb2d_default {
1382 function = "USB2D1";
1386 pinctrl_vgabios_rom_default: vgabios_rom_default {
1387 function = "VGABIOS_ROM";
1388 groups = "VGABIOS_ROM";
1391 pinctrl_vgahs_default: vgahs_default {
1396 pinctrl_vgavs_default: vgavs_default {
1401 pinctrl_vpi18_default: vpi18_default {
1406 pinctrl_vpi24_default: vpi24_default {
1411 pinctrl_vpi30_default: vpi30_default {
1416 pinctrl_vpo12_default: vpo12_default {
1421 pinctrl_vpo24_default: vpo24_default {
1426 pinctrl_wdtrst1_default: wdtrst1_default {
1427 function = "WDTRST1";
1431 pinctrl_wdtrst2_default: wdtrst2_default {
1432 function = "WDTRST2";