1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 spi: flash-controller@1e630000 {
73 reg = < 0x1e630000 0x18
74 0x30000000 0x10000000 >;
77 compatible = "aspeed,ast2400-spi";
78 clocks = <&syscon ASPEED_CLK_AHB>;
82 compatible = "jedec,spi-nor";
87 vic: interrupt-controller@1e6c0080 {
88 compatible = "aspeed,ast2400-vic";
90 #interrupt-cells = <1>;
91 valid-sources = <0xffffffff 0x0007ffff>;
92 reg = <0x1e6c0080 0x80>;
95 mac0: ethernet@1e660000 {
96 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
97 reg = <0x1e660000 0x180>;
99 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
103 mac1: ethernet@1e680000 {
104 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
105 reg = <0x1e680000 0x180>;
107 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
112 compatible = "simple-bus";
113 #address-cells = <1>;
117 syscon: syscon@1e6e2000 {
118 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
119 reg = <0x1e6e2000 0x1a8>;
120 #address-cells = <1>;
126 compatible = "aspeed,g4-pinctrl";
131 compatible = "aspeed,ast2400-adc";
132 reg = <0x1e6e9000 0xb0>;
133 clocks = <&syscon ASPEED_CLK_APB>;
134 resets = <&syscon ASPEED_RESET_ADC>;
135 #io-channel-cells = <1>;
140 compatible = "mmio-sram";
141 reg = <0x1e720000 0x8000>; // 32K
144 gpio: gpio@1e780000 {
147 compatible = "aspeed,ast2400-gpio";
148 reg = <0x1e780000 0x1000>;
150 gpio-ranges = <&pinctrl 0 0 220>;
151 clocks = <&syscon ASPEED_CLK_APB>;
152 interrupt-controller;
155 timer: timer@1e782000 {
156 /* This timer is a Faraday FTTMR010 derivative */
157 compatible = "aspeed,ast2400-timer";
158 reg = <0x1e782000 0x90>;
159 interrupts = <16 17 18 35 36 37 38 39>;
160 clocks = <&syscon ASPEED_CLK_APB>;
161 clock-names = "PCLK";
164 uart1: serial@1e783000 {
165 compatible = "ns16550a";
166 reg = <0x1e783000 0x20>;
169 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
170 resets = <&lpc_reset 4>;
175 uart5: serial@1e784000 {
176 compatible = "ns16550a";
177 reg = <0x1e784000 0x20>;
180 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
185 wdt1: watchdog@1e785000 {
186 compatible = "aspeed,ast2400-wdt";
187 reg = <0x1e785000 0x1c>;
188 clocks = <&syscon ASPEED_CLK_APB>;
191 wdt2: watchdog@1e785020 {
192 compatible = "aspeed,ast2400-wdt";
193 reg = <0x1e785020 0x1c>;
194 clocks = <&syscon ASPEED_CLK_APB>;
197 pwm_tacho: pwm-tacho-controller@1e786000 {
198 compatible = "aspeed,ast2400-pwm-tacho";
199 #address-cells = <1>;
201 reg = <0x1e786000 0x1000>;
202 clocks = <&syscon ASPEED_CLK_APB>;
203 resets = <&syscon ASPEED_RESET_PWM>;
207 vuart: serial@1e787000 {
208 compatible = "aspeed,ast2400-vuart";
209 reg = <0x1e787000 0x40>;
212 clocks = <&syscon ASPEED_CLK_APB>;
218 compatible = "aspeed,ast2400-lpc", "simple-mfd";
219 reg = <0x1e789000 0x1000>;
221 #address-cells = <1>;
223 ranges = <0x0 0x1e789000 0x1000>;
226 compatible = "aspeed,ast2400-lpc-bmc";
230 lpc_host: lpc-host@80 {
231 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
235 #address-cells = <1>;
237 ranges = <0x0 0x80 0x1e0>;
239 lpc_ctrl: lpc-ctrl@0 {
240 compatible = "aspeed,ast2400-lpc-ctrl";
242 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
246 lpc_snoop: lpc-snoop@0 {
247 compatible = "aspeed,ast2400-lpc-snoop";
254 compatible = "aspeed,ast2400-lhc";
255 reg = <0x20 0x24 0x48 0x8>;
258 lpc_reset: reset-controller@18 {
259 compatible = "aspeed,ast2400-lpc-reset";
265 compatible = "aspeed,ast2400-ibt-bmc";
273 uart2: serial@1e78d000 {
274 compatible = "ns16550a";
275 reg = <0x1e78d000 0x20>;
278 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
279 resets = <&lpc_reset 5>;
284 uart3: serial@1e78e000 {
285 compatible = "ns16550a";
286 reg = <0x1e78e000 0x20>;
289 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
290 resets = <&lpc_reset 6>;
295 uart4: serial@1e78f000 {
296 compatible = "ns16550a";
297 reg = <0x1e78f000 0x20>;
300 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
301 resets = <&lpc_reset 7>;
307 compatible = "simple-bus";
308 #address-cells = <1>;
310 ranges = <0 0x1e78a000 0x1000>;
317 i2c_ic: interrupt-controller@0 {
318 #interrupt-cells = <1>;
319 compatible = "aspeed,ast2400-i2c-ic";
322 interrupt-controller;
326 #address-cells = <1>;
328 #interrupt-cells = <1>;
331 compatible = "aspeed,ast2400-i2c-bus";
332 clocks = <&syscon ASPEED_CLK_APB>;
333 resets = <&syscon ASPEED_RESET_I2C>;
334 bus-frequency = <100000>;
336 interrupt-parent = <&i2c_ic>;
338 /* Does not need pinctrl properties */
342 #address-cells = <1>;
344 #interrupt-cells = <1>;
347 compatible = "aspeed,ast2400-i2c-bus";
348 clocks = <&syscon ASPEED_CLK_APB>;
349 resets = <&syscon ASPEED_RESET_I2C>;
350 bus-frequency = <100000>;
352 interrupt-parent = <&i2c_ic>;
354 /* Does not need pinctrl properties */
358 #address-cells = <1>;
360 #interrupt-cells = <1>;
363 compatible = "aspeed,ast2400-i2c-bus";
364 clocks = <&syscon ASPEED_CLK_APB>;
365 resets = <&syscon ASPEED_RESET_I2C>;
366 bus-frequency = <100000>;
368 interrupt-parent = <&i2c_ic>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_i2c3_default>;
375 #address-cells = <1>;
377 #interrupt-cells = <1>;
380 compatible = "aspeed,ast2400-i2c-bus";
381 clocks = <&syscon ASPEED_CLK_APB>;
382 resets = <&syscon ASPEED_RESET_I2C>;
383 bus-frequency = <100000>;
385 interrupt-parent = <&i2c_ic>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_i2c4_default>;
392 #address-cells = <1>;
394 #interrupt-cells = <1>;
397 compatible = "aspeed,ast2400-i2c-bus";
398 clocks = <&syscon ASPEED_CLK_APB>;
399 resets = <&syscon ASPEED_RESET_I2C>;
400 bus-frequency = <100000>;
402 interrupt-parent = <&i2c_ic>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_i2c5_default>;
409 #address-cells = <1>;
411 #interrupt-cells = <1>;
414 compatible = "aspeed,ast2400-i2c-bus";
415 clocks = <&syscon ASPEED_CLK_APB>;
416 resets = <&syscon ASPEED_RESET_I2C>;
417 bus-frequency = <100000>;
419 interrupt-parent = <&i2c_ic>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_i2c6_default>;
426 #address-cells = <1>;
428 #interrupt-cells = <1>;
431 compatible = "aspeed,ast2400-i2c-bus";
432 clocks = <&syscon ASPEED_CLK_APB>;
433 resets = <&syscon ASPEED_RESET_I2C>;
434 bus-frequency = <100000>;
436 interrupt-parent = <&i2c_ic>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_i2c7_default>;
443 #address-cells = <1>;
445 #interrupt-cells = <1>;
448 compatible = "aspeed,ast2400-i2c-bus";
449 clocks = <&syscon ASPEED_CLK_APB>;
450 resets = <&syscon ASPEED_RESET_I2C>;
451 bus-frequency = <100000>;
453 interrupt-parent = <&i2c_ic>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_i2c8_default>;
460 #address-cells = <1>;
462 #interrupt-cells = <1>;
465 compatible = "aspeed,ast2400-i2c-bus";
466 clocks = <&syscon ASPEED_CLK_APB>;
467 resets = <&syscon ASPEED_RESET_I2C>;
468 bus-frequency = <100000>;
470 interrupt-parent = <&i2c_ic>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_i2c9_default>;
477 #address-cells = <1>;
479 #interrupt-cells = <1>;
482 compatible = "aspeed,ast2400-i2c-bus";
483 clocks = <&syscon ASPEED_CLK_APB>;
484 resets = <&syscon ASPEED_RESET_I2C>;
485 bus-frequency = <100000>;
487 interrupt-parent = <&i2c_ic>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_i2c10_default>;
494 #address-cells = <1>;
496 #interrupt-cells = <1>;
499 compatible = "aspeed,ast2400-i2c-bus";
500 clocks = <&syscon ASPEED_CLK_APB>;
501 resets = <&syscon ASPEED_RESET_I2C>;
502 bus-frequency = <100000>;
504 interrupt-parent = <&i2c_ic>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_i2c11_default>;
511 #address-cells = <1>;
513 #interrupt-cells = <1>;
516 compatible = "aspeed,ast2400-i2c-bus";
517 clocks = <&syscon ASPEED_CLK_APB>;
518 resets = <&syscon ASPEED_RESET_I2C>;
519 bus-frequency = <100000>;
521 interrupt-parent = <&i2c_ic>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_i2c12_default>;
528 #address-cells = <1>;
530 #interrupt-cells = <1>;
533 compatible = "aspeed,ast2400-i2c-bus";
534 clocks = <&syscon ASPEED_CLK_APB>;
535 resets = <&syscon ASPEED_RESET_I2C>;
536 bus-frequency = <100000>;
538 interrupt-parent = <&i2c_ic>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_i2c13_default>;
545 #address-cells = <1>;
547 #interrupt-cells = <1>;
550 compatible = "aspeed,ast2400-i2c-bus";
551 clocks = <&syscon ASPEED_CLK_APB>;
552 resets = <&syscon ASPEED_RESET_I2C>;
553 bus-frequency = <100000>;
555 interrupt-parent = <&i2c_ic>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_i2c14_default>;
563 pinctrl_acpi_default: acpi_default {
568 pinctrl_adc0_default: adc0_default {
573 pinctrl_adc1_default: adc1_default {
578 pinctrl_adc10_default: adc10_default {
583 pinctrl_adc11_default: adc11_default {
588 pinctrl_adc12_default: adc12_default {
593 pinctrl_adc13_default: adc13_default {
598 pinctrl_adc14_default: adc14_default {
603 pinctrl_adc15_default: adc15_default {
608 pinctrl_adc2_default: adc2_default {
613 pinctrl_adc3_default: adc3_default {
618 pinctrl_adc4_default: adc4_default {
623 pinctrl_adc5_default: adc5_default {
628 pinctrl_adc6_default: adc6_default {
633 pinctrl_adc7_default: adc7_default {
638 pinctrl_adc8_default: adc8_default {
643 pinctrl_adc9_default: adc9_default {
648 pinctrl_bmcint_default: bmcint_default {
653 pinctrl_ddcclk_default: ddcclk_default {
658 pinctrl_ddcdat_default: ddcdat_default {
663 pinctrl_extrst_default: extrst_default {
668 pinctrl_flack_default: flack_default {
673 pinctrl_flbusy_default: flbusy_default {
678 pinctrl_flwp_default: flwp_default {
683 pinctrl_gpid_default: gpid_default {
688 pinctrl_gpid0_default: gpid0_default {
693 pinctrl_gpid2_default: gpid2_default {
698 pinctrl_gpid4_default: gpid4_default {
703 pinctrl_gpid6_default: gpid6_default {
708 pinctrl_gpie0_default: gpie0_default {
713 pinctrl_gpie2_default: gpie2_default {
718 pinctrl_gpie4_default: gpie4_default {
723 pinctrl_gpie6_default: gpie6_default {
728 pinctrl_i2c10_default: i2c10_default {
733 pinctrl_i2c11_default: i2c11_default {
738 pinctrl_i2c12_default: i2c12_default {
743 pinctrl_i2c13_default: i2c13_default {
748 pinctrl_i2c14_default: i2c14_default {
753 pinctrl_i2c3_default: i2c3_default {
758 pinctrl_i2c4_default: i2c4_default {
763 pinctrl_i2c5_default: i2c5_default {
768 pinctrl_i2c6_default: i2c6_default {
773 pinctrl_i2c7_default: i2c7_default {
778 pinctrl_i2c8_default: i2c8_default {
783 pinctrl_i2c9_default: i2c9_default {
788 pinctrl_lpcpd_default: lpcpd_default {
793 pinctrl_lpcpme_default: lpcpme_default {
798 pinctrl_lpcrst_default: lpcrst_default {
803 pinctrl_lpcsmi_default: lpcsmi_default {
808 pinctrl_mac1link_default: mac1link_default {
809 function = "MAC1LINK";
813 pinctrl_mac2link_default: mac2link_default {
814 function = "MAC2LINK";
818 pinctrl_mdio1_default: mdio1_default {
823 pinctrl_mdio2_default: mdio2_default {
828 pinctrl_ncts1_default: ncts1_default {
833 pinctrl_ncts2_default: ncts2_default {
838 pinctrl_ncts3_default: ncts3_default {
843 pinctrl_ncts4_default: ncts4_default {
848 pinctrl_ndcd1_default: ndcd1_default {
853 pinctrl_ndcd2_default: ndcd2_default {
858 pinctrl_ndcd3_default: ndcd3_default {
863 pinctrl_ndcd4_default: ndcd4_default {
868 pinctrl_ndsr1_default: ndsr1_default {
873 pinctrl_ndsr2_default: ndsr2_default {
878 pinctrl_ndsr3_default: ndsr3_default {
883 pinctrl_ndsr4_default: ndsr4_default {
888 pinctrl_ndtr1_default: ndtr1_default {
893 pinctrl_ndtr2_default: ndtr2_default {
898 pinctrl_ndtr3_default: ndtr3_default {
903 pinctrl_ndtr4_default: ndtr4_default {
908 pinctrl_ndts4_default: ndts4_default {
913 pinctrl_nri1_default: nri1_default {
918 pinctrl_nri2_default: nri2_default {
923 pinctrl_nri3_default: nri3_default {
928 pinctrl_nri4_default: nri4_default {
933 pinctrl_nrts1_default: nrts1_default {
938 pinctrl_nrts2_default: nrts2_default {
943 pinctrl_nrts3_default: nrts3_default {
948 pinctrl_oscclk_default: oscclk_default {
953 pinctrl_pwm0_default: pwm0_default {
958 pinctrl_pwm1_default: pwm1_default {
963 pinctrl_pwm2_default: pwm2_default {
968 pinctrl_pwm3_default: pwm3_default {
973 pinctrl_pwm4_default: pwm4_default {
978 pinctrl_pwm5_default: pwm5_default {
983 pinctrl_pwm6_default: pwm6_default {
988 pinctrl_pwm7_default: pwm7_default {
993 pinctrl_rgmii1_default: rgmii1_default {
998 pinctrl_rgmii2_default: rgmii2_default {
1003 pinctrl_rmii1_default: rmii1_default {
1008 pinctrl_rmii2_default: rmii2_default {
1013 pinctrl_rom16_default: rom16_default {
1018 pinctrl_rom8_default: rom8_default {
1023 pinctrl_romcs1_default: romcs1_default {
1024 function = "ROMCS1";
1028 pinctrl_romcs2_default: romcs2_default {
1029 function = "ROMCS2";
1033 pinctrl_romcs3_default: romcs3_default {
1034 function = "ROMCS3";
1038 pinctrl_romcs4_default: romcs4_default {
1039 function = "ROMCS4";
1043 pinctrl_rxd1_default: rxd1_default {
1048 pinctrl_rxd2_default: rxd2_default {
1053 pinctrl_rxd3_default: rxd3_default {
1058 pinctrl_rxd4_default: rxd4_default {
1063 pinctrl_salt1_default: salt1_default {
1068 pinctrl_salt2_default: salt2_default {
1073 pinctrl_salt3_default: salt3_default {
1078 pinctrl_salt4_default: salt4_default {
1083 pinctrl_sd1_default: sd1_default {
1088 pinctrl_sd2_default: sd2_default {
1093 pinctrl_sgpmck_default: sgpmck_default {
1094 function = "SGPMCK";
1098 pinctrl_sgpmi_default: sgpmi_default {
1103 pinctrl_sgpmld_default: sgpmld_default {
1104 function = "SGPMLD";
1108 pinctrl_sgpmo_default: sgpmo_default {
1113 pinctrl_sgpsck_default: sgpsck_default {
1114 function = "SGPSCK";
1118 pinctrl_sgpsi0_default: sgpsi0_default {
1119 function = "SGPSI0";
1123 pinctrl_sgpsi1_default: sgpsi1_default {
1124 function = "SGPSI1";
1128 pinctrl_sgpsld_default: sgpsld_default {
1129 function = "SGPSLD";
1133 pinctrl_sioonctrl_default: sioonctrl_default {
1134 function = "SIOONCTRL";
1135 groups = "SIOONCTRL";
1138 pinctrl_siopbi_default: siopbi_default {
1139 function = "SIOPBI";
1143 pinctrl_siopbo_default: siopbo_default {
1144 function = "SIOPBO";
1148 pinctrl_siopwreq_default: siopwreq_default {
1149 function = "SIOPWREQ";
1150 groups = "SIOPWREQ";
1153 pinctrl_siopwrgd_default: siopwrgd_default {
1154 function = "SIOPWRGD";
1155 groups = "SIOPWRGD";
1158 pinctrl_sios3_default: sios3_default {
1163 pinctrl_sios5_default: sios5_default {
1168 pinctrl_siosci_default: siosci_default {
1169 function = "SIOSCI";
1173 pinctrl_spi1_default: spi1_default {
1178 pinctrl_spi1debug_default: spi1debug_default {
1179 function = "SPI1DEBUG";
1180 groups = "SPI1DEBUG";
1183 pinctrl_spi1passthru_default: spi1passthru_default {
1184 function = "SPI1PASSTHRU";
1185 groups = "SPI1PASSTHRU";
1188 pinctrl_spics1_default: spics1_default {
1189 function = "SPICS1";
1193 pinctrl_timer3_default: timer3_default {
1194 function = "TIMER3";
1198 pinctrl_timer4_default: timer4_default {
1199 function = "TIMER4";
1203 pinctrl_timer5_default: timer5_default {
1204 function = "TIMER5";
1208 pinctrl_timer6_default: timer6_default {
1209 function = "TIMER6";
1213 pinctrl_timer7_default: timer7_default {
1214 function = "TIMER7";
1218 pinctrl_timer8_default: timer8_default {
1219 function = "TIMER8";
1223 pinctrl_txd1_default: txd1_default {
1228 pinctrl_txd2_default: txd2_default {
1233 pinctrl_txd3_default: txd3_default {
1238 pinctrl_txd4_default: txd4_default {
1243 pinctrl_uart6_default: uart6_default {
1248 pinctrl_usbcki_default: usbcki_default {
1249 function = "USBCKI";
1253 pinctrl_vgabios_rom_default: vgabios_rom_default {
1254 function = "VGABIOS_ROM";
1255 groups = "VGABIOS_ROM";
1258 pinctrl_vgahs_default: vgahs_default {
1263 pinctrl_vgavs_default: vgavs_default {
1268 pinctrl_vpi18_default: vpi18_default {
1273 pinctrl_vpi24_default: vpi24_default {
1278 pinctrl_vpi30_default: vpi30_default {
1283 pinctrl_vpo12_default: vpo12_default {
1288 pinctrl_vpo24_default: vpo24_default {
1293 pinctrl_wdtrst1_default: wdtrst1_default {
1294 function = "WDTRST1";
1298 pinctrl_wdtrst2_default: wdtrst2_default {
1299 function = "WDTRST2";