1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
6 #include "aspeed-g6.dtsi"
9 model = "Nuvia DC-SCM BMC";
10 compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
18 bootargs = "console=ttyS4,115200n8";
22 device_type = "memory";
23 reg = <0x80000000 0x40000000>;
30 ethphy3: ethernet-phy@1 {
31 compatible = "ethernet-phy-ieee802.3-c22";
39 /* Bootloader sets up the MAC to insert delay */
41 phy-handle = <ðphy3>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_rgmii3_default>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_rmii4_default>;
67 spi-max-frequency = <133000000>;
68 #include "openbmc-flash-layout-64.dtsi"
75 spi-max-frequency = <133000000>;
76 #include "openbmc-flash-layout-64-alt.dtsi"
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_spi1_default>;
89 spi-max-frequency = <133000000>;
95 /*A0-A7*/ "","","","","","","","",
96 /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
97 /*C0-C7*/ "","","","","","","","",
98 /*D0-D7*/ "","","","","","","","",
99 /*E0-E7*/ "","","","","","","","",
100 /*F0-F7*/ "","","","","","","","",
101 /*G0-G7*/ "","","","","","","","",
102 /*H0-H7*/ "","","","","","","","",
103 /*I0-I7*/ "","","","","","","","",
104 /*J0-J7*/ "","","","","","","","",
105 /*K0-K7*/ "","","","","","","","",
106 /*L0-L7*/ "","","","","","","","",
107 /*M0-M7*/ "","","","","","","","",
108 /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
109 /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
110 /*P0-P7*/ "","","","","","","","",
111 /*Q0-Q7*/ "","","","","","","","",
112 /*R0-R7*/ "","","","","","","","",
113 /*S0-S7*/ "","","","","","","","",
114 /*T0-T7*/ "","","","","","","","",
115 /*U0-U7*/ "","","","","","","","",
116 /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
117 "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
118 "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
119 /*W0-W7*/ "","","","","","","","",
120 /*X0-X7*/ "","","","","","","","",
121 /*Y0-Y7*/ "","","","","","","","",
122 /*Z0-Z7*/ "","","","","","","","",
123 /*AA0-AA7*/ "","","","","","","","",
124 /*AB0-AB7*/ "","","","","","","","",
125 /*AC0-AC7*/ "","","","","","","","";
130 /*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
131 "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
132 /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
133 "SCMFPGA_SPARE_GPIO5_1V8","","","","","",
134 /*C0-C7*/ "","","","","","","","",
135 /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
136 "","TPM2_PIRQ_N","TPM2_RST_N","",
137 /*E0-E7*/ "","","","","","","","";