arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /dts-v1/;
   3 #include "aspeed-g5.dtsi"
   4 #include <dt-bindings/gpio/aspeed-gpio.h>
   5
   6 / {
   7         model = "Ampere Mt. Jade BMC";
   8         compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
   9
  10         chosen {
  11                 stdout-path = &uart5;
  12                 bootargs = "console=ttyS4,115200 earlyprintk";
  13         };
  14
  15         memory@80000000 {
  16                 reg = <0x80000000 0x20000000>;
  17         };
  18
  19         reserved-memory {
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges;
  23
  24                 vga_memory: framebuffer@9f000000 {
  25                         no-map;
  26                         reg = <0x9f000000 0x01000000>; /* 16M */
  27                 };
  28
  29                 gfx_memory: framebuffer {
  30                         size = <0x01000000>;
  31                         alignment = <0x01000000>;
  32                         compatible = "shared-dma-pool";
  33                         reusable;
  34                 };
  35
  36                 video_engine_memory: jpegbuffer {
  37                         size = <0x02000000>;    /* 32M */
  38                         alignment = <0x01000000>;
  39                         compatible = "shared-dma-pool";
  40                         reusable;
  41                 };
  42         };
  43
  44         leds {
  45                 compatible = "gpio-leds";
  46
  47                 fault {
  48                         gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
  49                 };
  50
  51                 identify {
  52                         gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         gpio-keys {
  57                 compatible = "gpio-keys";
  58
  59                 shutdown_ack {
  60                         label = "SHUTDOWN_ACK";
  61                         gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
  62                         linux,code = <ASPEED_GPIO(G, 2)>;
  63                 };
  64
  65                 reboot_ack {
  66                         label = "REBOOT_ACK";
  67                         gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
  68                         linux,code = <ASPEED_GPIO(J, 3)>;
  69                 };
  70
  71                 S0_overtemp {
  72                         label = "S0_OVERTEMP";
  73                         gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
  74                         linux,code = <ASPEED_GPIO(G, 3)>;
  75                 };
  76
  77                 S0_hightemp {
  78                         label = "S0_HIGHTEMP";
  79                         gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
  80                         linux,code = <ASPEED_GPIO(J, 0)>;
  81                 };
  82
  83                 S0_cpu_fault {
  84                         label = "S0_CPU_FAULT";
  85                         gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
  86                         linux,code = <ASPEED_GPIO(J, 1)>;
  87                 };
  88
  89                 S1_overtemp {
  90                         label = "S1_OVERTEMP";
  91                         gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
  92                         linux,code = <ASPEED_GPIO(Z, 6)>;
  93                 };
  94
  95                 S1_hightemp {
  96                         label = "S1_HIGHTEMP";
  97                         gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
  98                         linux,code = <ASPEED_GPIO(AB, 0)>;
  99                 };
 100
 101                 S1_cpu_fault {
 102                         label = "S1_CPU_FAULT";
 103                         gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
 104                         linux,code = <ASPEED_GPIO(Z, 1)>;
 105                 };
 106
 107                 id_button {
 108                         label = "ID_BUTTON";
 109                         gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
 110                         linux,code = <ASPEED_GPIO(Q, 5)>;
 111                 };
 112
 113         };
 114
 115         gpioA0mux: mux-controller {
 116                 compatible = "gpio-mux";
 117                 #mux-control-cells = <0>;
 118                 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
 119         };
 120
 121         adc0mux: adc0mux {
 122                 compatible = "io-channel-mux";
 123                 io-channels = <&adc 0>;
 124                 #io-channel-cells = <1>;
 125                 io-channel-names = "parent";
 126                 mux-controls = <&gpioA0mux>;
 127                 channels = "s0", "s1";
 128         };
 129
 130         adc1mux: adc1mux {
 131                 compatible = "io-channel-mux";
 132                 io-channels = <&adc 1>;
 133                 #io-channel-cells = <1>;
 134                 io-channel-names = "parent";
 135                 mux-controls = <&gpioA0mux>;
 136                 channels = "s0", "s1";
 137         };
 138
 139         adc2mux: adc2mux {
 140                 compatible = "io-channel-mux";
 141                 io-channels = <&adc 2>;
 142                 #io-channel-cells = <1>;
 143                 io-channel-names = "parent";
 144                 mux-controls = <&gpioA0mux>;
 145                 channels = "s0", "s1";
 146         };
 147
 148         adc3mux: adc3mux {
 149                 compatible = "io-channel-mux";
 150                 io-channels = <&adc 3>;
 151                 #io-channel-cells = <1>;
 152                 io-channel-names = "parent";
 153                 mux-controls = <&gpioA0mux>;
 154                 channels = "s0", "s1";
 155         };
 156
 157         adc4mux: adc4mux {
 158                 compatible = "io-channel-mux";
 159                 io-channels = <&adc 4>;
 160                 #io-channel-cells = <1>;
 161                 io-channel-names = "parent";
 162                 mux-controls = <&gpioA0mux>;
 163                 channels = "s0", "s1";
 164         };
 165
 166         adc5mux: adc5mux {
 167                 compatible = "io-channel-mux";
 168                 io-channels = <&adc 5>;
 169                 #io-channel-cells = <1>;
 170                 io-channel-names = "parent";
 171                 mux-controls = <&gpioA0mux>;
 172                 channels = "s0", "s1";
 173         };
 174
 175         adc6mux: adc6mux {
 176                 compatible = "io-channel-mux";
 177                 io-channels = <&adc 6>;
 178                 #io-channel-cells = <1>;
 179                 io-channel-names = "parent";
 180                 mux-controls = <&gpioA0mux>;
 181                 channels = "s0", "s1";
 182         };
 183
 184         adc7mux: adc7mux {
 185                 compatible = "io-channel-mux";
 186                 io-channels = <&adc 7>;
 187                 #io-channel-cells = <1>;
 188                 io-channel-names = "parent";
 189                 mux-controls = <&gpioA0mux>;
 190                 channels = "s0", "s1";
 191         };
 192
 193         adc8mux: adc8mux {
 194                 compatible = "io-channel-mux";
 195                 io-channels = <&adc 8>;
 196                 #io-channel-cells = <1>;
 197                 io-channel-names = "parent";
 198                 mux-controls = <&gpioA0mux>;
 199                 channels = "s0", "s1";
 200         };
 201
 202         adc9mux: adc9mux {
 203                 compatible = "io-channel-mux";
 204                 io-channels = <&adc 9>;
 205                 #io-channel-cells = <1>;
 206                 io-channel-names = "parent";
 207                 mux-controls = <&gpioA0mux>;
 208                 channels = "s0", "s1";
 209         };
 210
 211         adc10mux: adc10mux {
 212                 compatible = "io-channel-mux";
 213                 io-channels = <&adc 10>;
 214                 #io-channel-cells = <1>;
 215                 io-channel-names = "parent";
 216                 mux-controls = <&gpioA0mux>;
 217                 channels = "s0", "s1";
 218         };
 219
 220         adc11mux: adc11mux {
 221                 compatible = "io-channel-mux";
 222                 io-channels = <&adc 11>;
 223                 #io-channel-cells = <1>;
 224                 io-channel-names = "parent";
 225                 mux-controls = <&gpioA0mux>;
 226                 channels = "s0", "s1";
 227         };
 228
 229         adc12mux: adc12mux {
 230                 compatible = "io-channel-mux";
 231                 io-channels = <&adc 12>;
 232                 #io-channel-cells = <1>;
 233                 io-channel-names = "parent";
 234                 mux-controls = <&gpioA0mux>;
 235                 channels = "s0", "s1";
 236         };
 237
 238         adc13mux: adc13mux {
 239                 compatible = "io-channel-mux";
 240                 io-channels = <&adc 13>;
 241                 #io-channel-cells = <1>;
 242                 io-channel-names = "parent";
 243                 mux-controls = <&gpioA0mux>;
 244                 channels = "s0", "s1";
 245         };
 246
 247         iio-hwmon {
 248                 compatible = "iio-hwmon";
 249                 io-channels = <&adc0mux 0>, <&adc0mux 1>,
 250                         <&adc1mux 0>, <&adc1mux 1>,
 251                         <&adc2mux 0>, <&adc2mux 1>,
 252                         <&adc3mux 0>, <&adc3mux 1>,
 253                         <&adc4mux 0>, <&adc4mux 1>,
 254                         <&adc5mux 0>, <&adc5mux 1>,
 255                         <&adc6mux 0>, <&adc6mux 1>,
 256                         <&adc7mux 0>, <&adc7mux 1>,
 257                         <&adc8mux 0>, <&adc8mux 1>,
 258                         <&adc9mux 0>, <&adc9mux 1>,
 259                         <&adc10mux 0>, <&adc10mux 1>,
 260                         <&adc11mux 0>, <&adc11mux 1>,
 261                         <&adc12mux 0>, <&adc12mux 1>,
 262                         <&adc13mux 0>, <&adc13mux 1>;
 263         };
 264
 265         iio-hwmon-adc14 {
 266                 compatible = "iio-hwmon";
 267                 io-channels = <&adc 14>;
 268         };
 269
 270         iio-hwmon-battery {
 271                 compatible = "iio-hwmon";
 272                 io-channels = <&adc 15>;
 273         };
 274 };
 275
 276 &fmc {
 277         status = "okay";
 278         flash@0 {
 279                 status = "okay";
 280                 m25p,fast-read;
 281                 label = "bmc";
 282                 /* spi-max-frequency = <50000000>; */
 283 #include "openbmc-flash-layout.dtsi"
 284         };
 285 };
 286
 287 &spi1 {
 288         status = "okay";
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_spi1_default>;
 291
 292         flash@0 {
 293                 status = "okay";
 294                 m25p,fast-read;
 295                 label = "pnor";
 296                 /* spi-max-frequency = <100000000>; */
 297         };
 298 };
 299
 300 &uart1 {
 301         status = "okay";
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_txd1_default
 304                          &pinctrl_rxd1_default
 305                          &pinctrl_ncts1_default
 306                          &pinctrl_nrts1_default>;
 307 };
 308
 309 &uart2 {
 310         status = "okay";
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_txd2_default
 313                          &pinctrl_rxd2_default>;
 314 };
 315
 316 &uart3 {
 317         status = "okay";
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_txd3_default
 320                          &pinctrl_rxd3_default>;
 321 };
 322
 323 &uart4 {
 324         status = "okay";
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_txd4_default
 327                          &pinctrl_rxd4_default>;
 328 };
 329
 330 /* The BMC's uart */
 331 &uart5 {
 332         status = "okay";
 333 };
 334
 335 &mac1 {
 336         status = "okay";
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
 339 };
 340
 341 &i2c0 {
 342         status = "okay";
 343 };
 344
 345 &i2c1 {
 346         status = "okay";
 347 };
 348
 349 &i2c2 {
 350         status = "okay";
 351 };
 352
 353 &i2c3 {
 354         status = "okay";
 355         eeprom@50 {
 356                 compatible = "microchip,24c64", "atmel,24c64";
 357                 reg = <0x50>;
 358                 pagesize = <32>;
 359         };
 360
 361         inlet_mem2: tmp175@28 {
 362                 compatible = "ti,tmp175";
 363                 reg = <0x28>;
 364         };
 365
 366         inlet_cpu: tmp175@29 {
 367                 compatible = "ti,tmp175";
 368                 reg = <0x29>;
 369         };
 370
 371         inlet_mem1: tmp175@2a {
 372                 compatible = "ti,tmp175";
 373                 reg = <0x2a>;
 374         };
 375
 376         outlet_cpu: tmp175@2b {
 377                 compatible = "ti,tmp175";
 378                 reg = <0x2b>;
 379         };
 380
 381         outlet1: tmp175@2c {
 382                 compatible = "ti,tmp175";
 383                 reg = <0x2c>;
 384         };
 385
 386         outlet2: tmp175@2d {
 387                 compatible = "ti,tmp175";
 388                 reg = <0x2d>;
 389         };
 390 };
 391
 392 &i2c4 {
 393         status = "okay";
 394         rtc@51 {
 395                 compatible = "nxp,pcf85063a";
 396                 reg = <0x51>;
 397         };
 398 };
 399
 400 &i2c5 {
 401         status = "okay";
 402 };
 403
 404 &i2c6 {
 405         status = "okay";
 406         psu@58 {
 407                 compatible = "pmbus";
 408                 reg = <0x58>;
 409         };
 410
 411         psu@59 {
 412                 compatible = "pmbus";
 413                 reg = <0x59>;
 414         };
 415 };
 416
 417 &i2c7 {
 418         status = "okay";
 419 };
 420
 421 &i2c8 {
 422         status = "okay";
 423 };
 424
 425 &i2c9 {
 426         status = "okay";
 427 };
 428
 429 &gfx {
 430         status = "okay";
 431         memory-region = <&gfx_memory>;
 432 };
 433
 434 &pinctrl {
 435         aspeed,external-nodes = <&gfx &lhc>;
 436 };
 437
 438 &pwm_tacho {
 439         status = "okay";
 440         pinctrl-names = "default";
 441         pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
 442                         &pinctrl_pwm4_default &pinctrl_pwm5_default
 443                         &pinctrl_pwm6_default &pinctrl_pwm7_default>;
 444
 445         fan@0 {
 446                 reg = <0x02>;
 447                 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 448         };
 449
 450         fan@1 {
 451                 reg = <0x02>;
 452                 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 453         };
 454
 455         fan@2 {
 456                 reg = <0x03>;
 457                 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 458         };
 459
 460         fan@3 {
 461                 reg = <0x03>;
 462                 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 463         };
 464
 465         fan@4 {
 466                 reg = <0x04>;
 467                 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
 468         };
 469
 470         fan@5 {
 471                 reg = <0x04>;
 472                 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
 473         };
 474
 475         fan@6 {
 476                 reg = <0x05>;
 477                 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
 478         };
 479
 480         fan@7 {
 481                 reg = <0x05>;
 482                 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
 483         };
 484
 485         fan@8 {
 486                 reg = <0x06>;
 487                 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
 488         };
 489
 490         fan@9 {
 491                 reg = <0x06>;
 492                 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
 493         };
 494
 495         fan@10 {
 496                 reg = <0x07>;
 497                 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
 498         };
 499
 500         fan@11 {
 501                 reg = <0x07>;
 502                 aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
 503         };
 504
 505 };
 506
 507 &vhub {
 508         status = "okay";
 509 };
 510
 511 &adc {
 512         status = "okay";
 513 };
 514
 515 &video {
 516         status = "okay";
 517         memory-region = <&video_engine_memory>;
 518 };
 519
 520 &gpio {
 521         gpio-line-names =
 522         /*A0-A7*/       "","","","S0_BMC_SPECIAL_BOOT","","","","",
 523         /*B0-B7*/       "BMC_SELECT_EEPROM","","","",
 524                         "POWER_BUTTON","","","",
 525         /*C0-C7*/       "","","","","","","","",
 526         /*D0-D7*/       "","","","","","","","",
 527         /*E0-E7*/       "","","","","","","","",
 528         /*F0-F7*/       "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
 529                         "S1_DDR_SAVE","","",
 530         /*G0-G7*/       "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
 531                         "","",
 532         /*H0-H7*/       "","","","","","","","",
 533         /*I0-I7*/       "","","S1_BMC_SPECIAL_BOOT","","","","","",
 534         /*J0-J7*/       "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
 535                         "","","","",
 536         /*K0-K7*/       "","","","","","","","",
 537         /*L0-L7*/       "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
 538         /*M0-M7*/       "","","","","","","","",
 539         /*N0-N7*/       "","","","","","","","",
 540         /*O0-O7*/       "","","","","","","","",
 541         /*P0-P7*/       "","","","","","","","",
 542         /*Q0-Q7*/       "","","","","","UID_BUTTON","","",
 543         /*R0-R7*/       "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
 544         /*S0-S7*/       "","","","","","","","",
 545         /*T0-T7*/       "","","","","","","","",
 546         /*U0-U7*/       "","","","","","","","",
 547         /*V0-V7*/       "","","","","","","","",
 548         /*W0-W7*/       "","","","","","","","",
 549         /*X0-X7*/       "","","","","","","","",
 550         /*Y0-Y7*/       "","","","","","","","",
 551         /*Z0-Z7*/       "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
 552                         "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
 553         /*AA0-AA7*/     "","","","","","","","",
 554         /*AB0-AB7*/     "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
 555                         "S1_BMC_DDR_ADR","","","","",
 556         /*AC0-AC7*/     "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
 557                         "BMC_OCP_PG";
 558 };