1 // SPDX-License-Identifier: GPL-2.0+
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
7 model = "Ampere Mt. Jade BMC";
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 bootargs = "console=ttyS4,115200 earlycon";
16 reg = <0x80000000 0x20000000>;
24 vga_memory: framebuffer@9f000000 {
26 reg = <0x9f000000 0x01000000>; /* 16M */
29 gfx_memory: framebuffer {
31 alignment = <0x01000000>;
32 compatible = "shared-dma-pool";
36 video_engine_memory: jpegbuffer {
37 size = <0x02000000>; /* 32M */
38 alignment = <0x01000000>;
39 compatible = "shared-dma-pool";
45 compatible = "gpio-leds";
48 gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
52 gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
57 compatible = "gpio-keys";
60 label = "SHUTDOWN_ACK";
61 gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
62 linux,code = <ASPEED_GPIO(G, 2)>;
67 gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
68 linux,code = <ASPEED_GPIO(J, 3)>;
72 label = "S0_OVERTEMP";
73 gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
74 linux,code = <ASPEED_GPIO(G, 3)>;
78 label = "S0_HIGHTEMP";
79 gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
80 linux,code = <ASPEED_GPIO(J, 0)>;
84 label = "S0_CPU_FAULT";
85 gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
86 linux,code = <ASPEED_GPIO(J, 1)>;
90 label = "S1_OVERTEMP";
91 gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
92 linux,code = <ASPEED_GPIO(Z, 6)>;
96 label = "S1_HIGHTEMP";
97 gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
98 linux,code = <ASPEED_GPIO(AB, 0)>;
102 label = "S1_CPU_FAULT";
103 gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
104 linux,code = <ASPEED_GPIO(Z, 1)>;
109 gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
110 linux,code = <ASPEED_GPIO(Q, 5)>;
114 label = "PSU1_VIN_GOOD";
115 gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
116 linux,code = <ASPEED_GPIO(H, 4)>;
120 label = "PSU2_VIN_GOOD";
121 gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
122 linux,code = <ASPEED_GPIO(H, 5)>;
126 label = "PSU1_PRESENT";
127 gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
128 linux,code = <ASPEED_GPIO(I, 0)>;
132 label = "PSU2_PRESENT";
133 gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
134 linux,code = <ASPEED_GPIO(I, 1)>;
139 gpioA0mux: mux-controller {
140 compatible = "gpio-mux";
141 #mux-control-cells = <0>;
142 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
146 compatible = "io-channel-mux";
147 io-channels = <&adc 0>;
148 #io-channel-cells = <1>;
149 io-channel-names = "parent";
150 mux-controls = <&gpioA0mux>;
151 channels = "s0", "s1";
155 compatible = "io-channel-mux";
156 io-channels = <&adc 1>;
157 #io-channel-cells = <1>;
158 io-channel-names = "parent";
159 mux-controls = <&gpioA0mux>;
160 channels = "s0", "s1";
164 compatible = "io-channel-mux";
165 io-channels = <&adc 2>;
166 #io-channel-cells = <1>;
167 io-channel-names = "parent";
168 mux-controls = <&gpioA0mux>;
169 channels = "s0", "s1";
173 compatible = "io-channel-mux";
174 io-channels = <&adc 3>;
175 #io-channel-cells = <1>;
176 io-channel-names = "parent";
177 mux-controls = <&gpioA0mux>;
178 channels = "s0", "s1";
182 compatible = "io-channel-mux";
183 io-channels = <&adc 4>;
184 #io-channel-cells = <1>;
185 io-channel-names = "parent";
186 mux-controls = <&gpioA0mux>;
187 channels = "s0", "s1";
191 compatible = "io-channel-mux";
192 io-channels = <&adc 5>;
193 #io-channel-cells = <1>;
194 io-channel-names = "parent";
195 mux-controls = <&gpioA0mux>;
196 channels = "s0", "s1";
200 compatible = "io-channel-mux";
201 io-channels = <&adc 6>;
202 #io-channel-cells = <1>;
203 io-channel-names = "parent";
204 mux-controls = <&gpioA0mux>;
205 channels = "s0", "s1";
209 compatible = "io-channel-mux";
210 io-channels = <&adc 7>;
211 #io-channel-cells = <1>;
212 io-channel-names = "parent";
213 mux-controls = <&gpioA0mux>;
214 channels = "s0", "s1";
218 compatible = "io-channel-mux";
219 io-channels = <&adc 8>;
220 #io-channel-cells = <1>;
221 io-channel-names = "parent";
222 mux-controls = <&gpioA0mux>;
223 channels = "s0", "s1";
227 compatible = "io-channel-mux";
228 io-channels = <&adc 9>;
229 #io-channel-cells = <1>;
230 io-channel-names = "parent";
231 mux-controls = <&gpioA0mux>;
232 channels = "s0", "s1";
236 compatible = "io-channel-mux";
237 io-channels = <&adc 10>;
238 #io-channel-cells = <1>;
239 io-channel-names = "parent";
240 mux-controls = <&gpioA0mux>;
241 channels = "s0", "s1";
245 compatible = "io-channel-mux";
246 io-channels = <&adc 11>;
247 #io-channel-cells = <1>;
248 io-channel-names = "parent";
249 mux-controls = <&gpioA0mux>;
250 channels = "s0", "s1";
254 compatible = "io-channel-mux";
255 io-channels = <&adc 12>;
256 #io-channel-cells = <1>;
257 io-channel-names = "parent";
258 mux-controls = <&gpioA0mux>;
259 channels = "s0", "s1";
263 compatible = "io-channel-mux";
264 io-channels = <&adc 13>;
265 #io-channel-cells = <1>;
266 io-channel-names = "parent";
267 mux-controls = <&gpioA0mux>;
268 channels = "s0", "s1";
272 compatible = "iio-hwmon";
273 io-channels = <&adc0mux 0>, <&adc0mux 1>,
274 <&adc1mux 0>, <&adc1mux 1>,
275 <&adc2mux 0>, <&adc2mux 1>,
276 <&adc3mux 0>, <&adc3mux 1>,
277 <&adc4mux 0>, <&adc4mux 1>,
278 <&adc5mux 0>, <&adc5mux 1>,
279 <&adc6mux 0>, <&adc6mux 1>,
280 <&adc7mux 0>, <&adc7mux 1>,
281 <&adc8mux 0>, <&adc8mux 1>,
282 <&adc9mux 0>, <&adc9mux 1>,
283 <&adc10mux 0>, <&adc10mux 1>,
284 <&adc11mux 0>, <&adc11mux 1>,
285 <&adc12mux 0>, <&adc12mux 1>,
286 <&adc13mux 0>, <&adc13mux 1>;
290 compatible = "iio-hwmon";
291 io-channels = <&adc 14>;
295 compatible = "iio-hwmon";
296 io-channels = <&adc 15>;
306 /* spi-max-frequency = <50000000>; */
307 #include "openbmc-flash-layout-64.dtsi"
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_spi1_default>;
320 /* spi-max-frequency = <100000000>; */
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_txd1_default
328 &pinctrl_rxd1_default
329 &pinctrl_ncts1_default
330 &pinctrl_nrts1_default>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_txd2_default
337 &pinctrl_rxd2_default>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_txd3_default
344 &pinctrl_rxd3_default>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_txd4_default
351 &pinctrl_rxd4_default>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_rmii1_default>;
363 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
364 <&syscon ASPEED_CLK_MAC1RCLK>;
365 clock-names = "MACCLK", "RCLK";
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
390 compatible = "microchip,24c64", "atmel,24c64";
395 inlet_mem2: tmp175@28 {
396 compatible = "ti,tmp175";
400 inlet_cpu: tmp175@29 {
401 compatible = "ti,tmp175";
405 inlet_mem1: tmp175@2a {
406 compatible = "ti,tmp175";
410 outlet_cpu: tmp175@2b {
411 compatible = "ti,tmp175";
416 compatible = "ti,tmp175";
421 compatible = "ti,tmp175";
429 compatible = "nxp,pcf85063a";
441 compatible = "pmbus";
446 compatible = "pmbus";
466 compatible = "adi,adm1278";
471 compatible = "adi,adm1278";
478 memory-region = <&gfx_memory>;
482 aspeed,external-nodes = <&gfx &lhc>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
489 &pinctrl_pwm4_default &pinctrl_pwm5_default
490 &pinctrl_pwm6_default &pinctrl_pwm7_default>;
494 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
499 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
504 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
509 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
514 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
519 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
524 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
529 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
534 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
539 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
544 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
549 aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
564 memory-region = <&video_engine_memory>;
569 /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","",
570 /*B0-B7*/ "BMC_SELECT_EEPROM","","","",
571 "POWER_BUTTON","","","",
572 /*C0-C7*/ "","","","","","","","",
573 /*D0-D7*/ "","","","","","","","",
574 /*E0-E7*/ "","","","","","","","",
575 /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
577 /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
579 /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
580 /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
582 /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
584 /*K0-K7*/ "","","","","","","","",
585 /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
586 /*M0-M7*/ "","","","","","","","",
587 /*N0-N7*/ "","","","","","","","",
588 /*O0-O7*/ "","","","","","","","",
589 /*P0-P7*/ "","","","","","","","",
590 /*Q0-Q7*/ "","","","","","UID_BUTTON","","",
591 /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
592 "OCP_MAIN_PWREN","RESET_BUTTON","","",
593 /*S0-S7*/ "","","","","","","","",
594 /*T0-T7*/ "","","","","","","","",
595 /*U0-U7*/ "","","","","","","","",
596 /*V0-V7*/ "","","","","","","","",
597 /*W0-W7*/ "","","","","","","","",
598 /*X0-X7*/ "","","","","","","","",
599 /*Y0-Y7*/ "","","","","","","","",
600 /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
601 "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
602 /*AA0-AA7*/ "","","","","","","","",
603 /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
604 "S1_BMC_DDR_ADR","","","","",
605 /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",