2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
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14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
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43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
46 #include "skeleton.dtsi"
49 compatible = "axis,artpec6";
50 interrupt-parent = <&intc>;
58 compatible = "arm,cortex-a9";
60 next-level-cache = <&pl310>;
65 compatible = "arm,cortex-a9";
67 next-level-cache = <&pl310>;
71 syscon: syscon@f8000000 {
72 compatible = "axis,artpec6-syscon", "syscon";
73 reg = <0xf8000000 0x48>;
77 compatible = "arm,psci-0.2", "arm,psci";
79 psci_version = <0x84000000>;
80 cpu_on = <0x84000003>;
81 system_reset = <0x84000009>;
85 compatible = "arm,cortex-a9-scu";
86 reg = <0xfaf00000 0x58>;
89 /* Main external clock driving CPU and peripherals */
92 compatible = "fixed-clock";
93 clock-frequency = <50000000>;
96 eth_phy_ref_clk: eth_phy_ref_clk {
98 compatible = "fixed-clock";
99 clock-frequency = <125000000>;
102 clkctrl: clkctrl@f8000000 {
104 compatible = "axis,artpec6-clkctrl";
105 reg = <0xf8000000 0x48>;
107 clock-names = "sys_refclk";
111 compatible = "arm,cortex-a9-global-timer";
112 reg = <0xfaf00200 0x20>;
113 interrupts = <GIC_PPI 11 0xf01>;
114 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0xfaf00600 0x20>;
120 interrupts = <GIC_PPI 13 0xf04>;
121 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
125 intc: interrupt-controller@faf01000 {
126 interrupt-controller;
127 compatible = "arm,cortex-a9-gic";
128 #interrupt-cells = <3>;
129 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
132 pl310: cache-controller@faf10000 {
133 compatible = "arm,pl310-cache";
136 reg = <0xfaf10000 0x1000>;
137 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
138 arm,data-latency = <1 1 1>;
139 arm,tag-latency = <1 1 1>;
140 arm,filter-ranges = <0x0 0x80000000>;
141 arm,double-linefill = <1>;
142 arm,double-linefill-incr = <0>;
143 arm,double-linefill-wrap = <0>;
145 prefetch-instr = <1>;
146 arm,prefetch-offset = <0>;
147 arm,prefetch-drop = <1>;
151 compatible = "arm,cortex-a9-pmu";
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
154 interrupt-affinity = <&cpu0>, <&cpu1>;
158 * Both pci nodes cannot be enabled at the same time,
159 * leave the unwanted node as disabled.
161 pcie: pcie@f8050000 {
162 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
163 reg = <0xf8050000 0x2000
166 reg-names = "dbi", "phy", "config";
167 #address-cells = <3>;
171 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
172 /* non-prefetchable memory */
173 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
175 bus-range = <0x00 0xff>;
176 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "msi";
178 #interrupt-cells = <1>;
179 interrupt-map-mask = <0 0 0 0x7>;
180 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
181 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
184 axis,syscon-pcie = <&syscon>;
188 pcie_ep: pcie_ep@f8050000 {
189 compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
190 reg = <0xf8050000 0x2000
193 0xc0000000 0x20000000>;
194 reg-names = "dbi", "dbi2", "phy", "addr_space";
195 num-ib-windows = <6>;
196 num-ob-windows = <2>;
198 axis,syscon-pcie = <&syscon>;
202 pinctrl: pinctrl@f801d000 {
203 compatible = "axis,artpec6-pinctrl";
204 reg = <0xf801d000 0x400>;
206 pinctrl_uart0: uart0grp {
208 groups = "uart0grp2";
211 pinctrl_uart1: uart1grp {
213 groups = "uart1grp0";
216 pinctrl_uart2: uart2grp {
218 groups = "uart2grp1";
221 pinctrl_uart3: uart3grp {
223 groups = "uart3grp0";
229 compatible = "simple-bus";
230 #address-cells = <0x1>;
236 compatible = "renesas,nbpfaxi64dmac8b16";
237 reg = <0xf8019000 0x400>;
238 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
239 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
247 interrupt-names = "error",
248 "ch0", "ch1", "ch2", "ch3",
249 "ch4", "ch5", "ch6", "ch7",
250 "ch8", "ch9", "ch10", "ch12",
251 "ch12", "ch13", "ch14", "ch15";
252 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
258 compatible = "renesas,nbpfaxi64dmac8b16";
259 reg = <0xf8019400 0x400>;
260 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
261 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "error",
270 "ch0", "ch1", "ch2", "ch3",
271 "ch4", "ch5", "ch6", "ch7",
272 "ch8", "ch9", "ch10", "ch12",
273 "ch12", "ch13", "ch14", "ch15";
274 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
280 ethernet: ethernet@f8010000 {
281 clock-names = "stmmaceth", "ptp_ref";
282 clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
283 <&clkctrl ARTPEC6_CLK_PTP_REF>;
284 compatible = "snps,dwmac-4.10a", "snps,dwmac";
285 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-names = "macirq", "eth_lpi";
288 reg = <0xf8010000 0x4000>;
290 snps,axi-config = <&stmmac_axi_setup>;
291 snps,mtl-rx-config = <&mtl_rx_setup>;
292 snps,mtl-tx-config = <&mtl_tx_setup>;
301 stmmac_axi_setup: stmmac-axi-config {
302 snps,wr_osr_lmt = <1>;
303 snps,rd_osr_lmt = <15>;
304 /* If FB is disabled, the AXI master chooses
305 * a burst length of any value less than the
306 * maximum enabled burst length
307 * (all lesser burst length enables are redundant).
309 snps,blen = <0 0 0 0 16 0 0>;
312 mtl_rx_setup: rx-queues-config {
313 snps,rx-queues-to-use = <1>;
317 mtl_tx_setup: tx-queues-config {
318 snps,tx-queues-to-use = <2>;
324 uart0: serial@f8036000 {
325 compatible = "arm,pl011", "arm,primecell";
326 reg = <0xf8036000 0x1000>;
327 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
329 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
330 clock-names = "uart_clk", "apb_pclk";
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_uart0>;
333 dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
334 <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
335 dma-names = "rx", "tx";
338 uart1: serial@f8037000 {
339 compatible = "arm,pl011", "arm,primecell";
340 reg = <0xf8037000 0x1000>;
341 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
343 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
344 clock-names = "uart_clk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_uart1>;
347 dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
348 <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
349 dma-names = "rx", "tx";
352 uart2: serial@f8038000 {
353 compatible = "arm,pl011", "arm,primecell";
354 reg = <0xf8038000 0x1000>;
355 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
357 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
358 clock-names = "uart_clk", "apb_pclk";
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_uart2>;
361 dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
362 <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
363 dma-names = "rx", "tx";
366 uart3: serial@f8039000 {
367 compatible = "arm,pl011", "arm,primecell";
368 reg = <0xf8039000 0x1000>;
369 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
371 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
372 clock-names = "uart_clk", "apb_pclk";
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_uart3>;
375 dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
376 <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
377 dma-names = "rx", "tx";