2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
35 compatible = "marvell,sheeva-v7";
42 compatible = "marvell,sheeva-v7";
50 * MV78260 has 3 PCIe units Gen2.0: Two units can be
51 * configured as x4 or quad x1 lanes. One unit is
55 compatible = "marvell,armada-xp-pcie";
63 bus-range = <0x00 0xff>;
66 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
67 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
68 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
69 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
70 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
71 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
72 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
73 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
74 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
75 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
76 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
77 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
78 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
79 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
80 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
81 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
82 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
84 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
85 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
86 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
87 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
88 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
89 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
90 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
91 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
93 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
94 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
98 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
99 reg = <0x0800 0 0 0 0>;
100 #address-cells = <3>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
104 0x81000000 0 0 0x81000000 0x1 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 58>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
109 clocks = <&gateclk 5>;
115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
116 reg = <0x1000 0 0 0 0>;
117 #address-cells = <3>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
121 0x81000000 0 0 0x81000000 0x2 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 59>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <1>;
126 clocks = <&gateclk 6>;
132 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
133 reg = <0x1800 0 0 0 0>;
134 #address-cells = <3>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
138 0x81000000 0 0 0x81000000 0x3 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 60>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <2>;
143 clocks = <&gateclk 7>;
149 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
150 reg = <0x2000 0 0 0 0>;
151 #address-cells = <3>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
155 0x81000000 0 0 0x81000000 0x4 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 61>;
158 marvell,pcie-port = <0>;
159 marvell,pcie-lane = <3>;
160 clocks = <&gateclk 8>;
166 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
167 reg = <0x2800 0 0 0 0>;
168 #address-cells = <3>;
170 #interrupt-cells = <1>;
171 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
172 0x81000000 0 0 0x81000000 0x5 0 1 0>;
173 interrupt-map-mask = <0 0 0 0>;
174 interrupt-map = <0 0 0 0 &mpic 62>;
175 marvell,pcie-port = <1>;
176 marvell,pcie-lane = <0>;
177 clocks = <&gateclk 9>;
183 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
184 reg = <0x3000 0 0 0 0>;
185 #address-cells = <3>;
187 #interrupt-cells = <1>;
188 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
189 0x81000000 0 0 0x81000000 0x6 0 1 0>;
190 interrupt-map-mask = <0 0 0 0>;
191 interrupt-map = <0 0 0 0 &mpic 63>;
192 marvell,pcie-port = <1>;
193 marvell,pcie-lane = <1>;
194 clocks = <&gateclk 10>;
200 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
201 reg = <0x3800 0 0 0 0>;
202 #address-cells = <3>;
204 #interrupt-cells = <1>;
205 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
206 0x81000000 0 0 0x81000000 0x7 0 1 0>;
207 interrupt-map-mask = <0 0 0 0>;
208 interrupt-map = <0 0 0 0 &mpic 64>;
209 marvell,pcie-port = <1>;
210 marvell,pcie-lane = <2>;
211 clocks = <&gateclk 11>;
217 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
218 reg = <0x4000 0 0 0 0>;
219 #address-cells = <3>;
221 #interrupt-cells = <1>;
222 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
223 0x81000000 0 0 0x81000000 0x8 0 1 0>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &mpic 65>;
226 marvell,pcie-port = <1>;
227 marvell,pcie-lane = <3>;
228 clocks = <&gateclk 12>;
234 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
235 reg = <0x4800 0 0 0 0>;
236 #address-cells = <3>;
238 #interrupt-cells = <1>;
239 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
240 0x81000000 0 0 0x81000000 0x9 0 1 0>;
241 interrupt-map-mask = <0 0 0 0>;
242 interrupt-map = <0 0 0 0 &mpic 99>;
243 marvell,pcie-port = <2>;
244 marvell,pcie-lane = <0>;
245 clocks = <&gateclk 26>;
252 compatible = "marvell,mv78260-pinctrl";
253 reg = <0x18000 0x38>;
255 sdio_pins: sdio-pins {
256 marvell,pins = "mpp30", "mpp31", "mpp32",
257 "mpp33", "mpp34", "mpp35";
258 marvell,function = "sd0";
263 compatible = "marvell,orion-gpio";
264 reg = <0x18100 0x40>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 interrupts = <82>, <83>, <84>, <85>;
274 compatible = "marvell,orion-gpio";
275 reg = <0x18140 0x40>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 interrupts = <87>, <88>, <89>, <90>;
285 compatible = "marvell,orion-gpio";
286 reg = <0x18180 0x40>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
295 eth3: ethernet@34000 {
296 compatible = "marvell,armada-370-neta";
297 reg = <0x34000 0x4000>;
299 clocks = <&gateclk 1>;