2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
4 * Copyright (C) 2015 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
47 #include "skeleton.dtsi"
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/interrupt-controller/irq.h>
51 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
69 enable-method = "marvell,armada-390-smp";
73 compatible = "arm,cortex-a9";
78 compatible = "arm,cortex-a9";
84 compatible = "arm,cortex-a9-pmu";
85 interrupts-extended = <&mpic 3>;
89 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
93 controller = <&mbusc>;
94 interrupt-parent = <&gic>;
95 pcie-mem-aperture = <0xe0000000 0x8000000>;
96 pcie-io-aperture = <0xe8000000 0x100000>;
99 compatible = "marvell,bootrom";
100 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
104 compatible = "simple-bus";
105 #address-cells = <1>;
107 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
109 L2: cache-controller@8000 {
110 compatible = "arm,pl310-cache";
111 reg = <0x8000 0x1000>;
114 arm,double-linefill-incr = <1>;
115 arm,double-linefill-wrap = <0>;
116 arm,double-linefill = <1>;
121 compatible = "arm,cortex-a9-scu";
122 reg = <0xc000 0x100>;
126 compatible = "arm,cortex-a9-twd-timer";
128 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
129 clocks = <&coreclk 2>;
132 gic: interrupt-controller@d000 {
133 compatible = "arm,cortex-a9-gic";
134 #interrupt-cells = <3>;
136 interrupt-controller;
137 reg = <0xd000 0x1000>,
142 compatible = "marvell,mv64xxx-i2c";
143 reg = <0x11000 0x20>;
144 #address-cells = <1>;
146 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&coreclk 0>;
153 compatible = "marvell,mv64xxx-i2c";
154 reg = <0x11100 0x20>;
155 #address-cells = <1>;
157 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&coreclk 0>;
164 compatible = "marvell,mv64xxx-i2c";
165 reg = <0x11200 0x20>;
166 #address-cells = <1>;
168 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&coreclk 0>;
175 compatible = "marvell,mv64xxx-i2c";
176 reg = <0x11300 0x20>;
177 #address-cells = <1>;
179 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&coreclk 0>;
185 uart0: serial@12000 {
186 compatible = "snps,dw-apb-uart";
187 reg = <0x12000 0x100>;
189 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&coreclk 0>;
195 uart1: serial@12100 {
196 compatible = "snps,dw-apb-uart";
197 reg = <0x12100 0x100>;
199 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&coreclk 0>;
205 uart2: serial@12200 {
206 compatible = "snps,dw-apb-uart";
207 reg = <0x12200 0x100>;
209 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&coreclk 0>;
215 uart3: serial@12300 {
216 compatible = "snps,dw-apb-uart";
217 reg = <0x12300 0x100>;
219 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&coreclk 0>;
226 i2c0_pins: i2c0-pins {
227 marvell,pins = "mpp2", "mpp3";
228 marvell,function = "i2c0";
231 uart0_pins: uart0-pins {
232 marvell,pins = "mpp0", "mpp1";
233 marvell,function = "ua0";
236 uart1_pins: uart1-pins {
237 marvell,pins = "mpp19", "mpp20";
238 marvell,function = "ua1";
241 spi1_pins: spi1-pins {
242 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
243 marvell,function = "spi1";
246 nand_pins: nand-pins {
247 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
248 "mpp38", "mpp28", "mpp40", "mpp42",
249 "mpp35", "mpp36", "mpp25", "mpp30",
251 marvell,function = "dev";
256 compatible = "marvell,orion-gpio";
257 reg = <0x18100 0x40>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
270 compatible = "marvell,orion-gpio";
271 reg = <0x18140 0x40>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
283 system-controller@18200 {
284 compatible = "marvell,armada-390-system-controller",
285 "marvell,armada-370-xp-system-controller";
286 reg = <0x18200 0x100>;
289 gateclk: clock-gating-control@18220 {
290 compatible = "marvell,armada-390-gating-clock";
292 clocks = <&coreclk 0>;
296 coreclk: mvebu-sar@18600 {
297 compatible = "marvell,armada-390-core-clock";
298 reg = <0x18600 0x04>;
302 mbusc: mbus-controller@20000 {
303 compatible = "marvell,mbus-controller";
304 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
307 mpic: interrupt-controller@20a00 {
308 compatible = "marvell,mpic";
309 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
310 #interrupt-cells = <1>;
312 interrupt-controller;
314 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 compatible = "marvell,armada-380-timer",
319 "marvell,armada-xp-timer";
320 reg = <0x20300 0x30>, <0x21040 0x30>;
321 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
322 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
323 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
324 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
327 clocks = <&coreclk 2>, <&coreclk 5>;
328 clock-names = "nbclk", "fixed";
332 compatible = "marvell,armada-380-wdt";
333 reg = <0x20300 0x34>, <0x20704 0x4>,
335 clocks = <&coreclk 2>, <&refclk>;
336 clock-names = "nbclk", "fixed";
340 compatible = "marvell,armada-370-cpu-reset";
341 reg = <0x20800 0x10>;
344 mpcore-soc-ctrl@20d20 {
345 compatible = "marvell,armada-380-mpcore-soc-ctrl";
346 reg = <0x20d20 0x6c>;
349 coherency-fabric@21010 {
350 compatible = "marvell,armada-380-coherency-fabric";
351 reg = <0x21010 0x1c>;
355 compatible = "marvell,armada-390-pmsu",
356 "marvell,armada-380-pmsu";
357 reg = <0x22000 0x1000>;
361 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
364 clocks = <&gateclk 22>;
368 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
373 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
381 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
384 clocks = <&gateclk 28>;
388 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
401 compatible = "marvell,armada-380-rtc";
402 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
403 reg-names = "rtc", "rtc-soc";
404 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
408 compatible = "marvell,armada370-nand";
409 reg = <0xd0000 0x54>;
410 #address-cells = <1>;
412 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&coredivclk 0>;
418 compatible = "marvell,armada-380-sdhci";
419 reg-names = "sdhci", "mbus", "conf-sdio3";
420 reg = <0xd8000 0x1000>,
423 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&gateclk 17>;
425 mrvl,clk-delay-cycles = <0x1F>;
429 coredivclk: clock@e4250 {
430 compatible = "marvell,armada-390-corediv-clock",
431 "marvell,armada-380-corediv-clock";
435 clock-output-names = "nand";
439 compatible = "marvell,armada380-thermal";
440 reg = <0xe4078 0x4>, <0xe4074 0x4>;
446 compatible = "marvell,armada-370-pcie";
450 #address-cells = <3>;
453 msi-parent = <&mpic>;
454 bus-range = <0x00 0xff>;
457 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
458 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
459 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
460 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
461 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
462 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
463 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
464 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
465 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
466 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
467 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
468 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
471 * This port can be either x4 or x1. When
472 * configured in x4 by the bootloader, then
473 * pcie@4,0 is not available.
477 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
478 reg = <0x0800 0 0 0 0>;
479 #address-cells = <3>;
481 #interrupt-cells = <1>;
482 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
483 0x81000000 0 0 0x81000000 0x1 0 1 0>;
484 bus-range = <0x00 0xff>;
485 interrupt-map-mask = <0 0 0 0>;
486 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
487 marvell,pcie-port = <0>;
488 marvell,pcie-lane = <0>;
489 clocks = <&gateclk 8>;
496 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
497 reg = <0x1000 0 0 0 0>;
498 #address-cells = <3>;
500 #interrupt-cells = <1>;
501 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
502 0x81000000 0 0 0x81000000 0x2 0 1 0>;
503 bus-range = <0x00 0xff>;
504 interrupt-map-mask = <0 0 0 0>;
505 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
506 marvell,pcie-port = <1>;
507 marvell,pcie-lane = <0>;
508 clocks = <&gateclk 5>;
515 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
516 reg = <0x1800 0 0 0 0>;
517 #address-cells = <3>;
519 #interrupt-cells = <1>;
520 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
521 0x81000000 0 0 0x81000000 0x3 0 1 0>;
522 bus-range = <0x00 0xff>;
523 interrupt-map-mask = <0 0 0 0>;
524 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
525 marvell,pcie-port = <2>;
526 marvell,pcie-lane = <0>;
527 clocks = <&gateclk 6>;
532 * x1 port only available when pcie@1,0 is
533 * configured as a x1 port
537 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
538 reg = <0x2000 0 0 0 0>;
539 #address-cells = <3>;
541 #interrupt-cells = <1>;
542 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
543 0x81000000 0 0 0x81000000 0x4 0 1 0>;
544 bus-range = <0x00 0xff>;
545 interrupt-map-mask = <0 0 0 0>;
546 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
547 marvell,pcie-port = <3>;
548 marvell,pcie-lane = <0>;
549 clocks = <&gateclk 7>;
555 compatible = "marvell,armada-390-spi",
557 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
558 #address-cells = <1>;
561 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&coreclk 0>;
567 compatible = "marvell,armada-390-spi",
569 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
570 #address-cells = <1>;
573 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&coreclk 0>;
580 /* 1 GHz fixed main PLL */
582 compatible = "fixed-clock";
584 clock-frequency = <1000000000>;
587 /* 25 MHz reference crystal */
589 compatible = "fixed-clock";
591 clock-frequency = <25000000>;