arch/arm/boot/dts/armada-39x.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 39x family of SoCs.
   3  *
   4  * Copyright (C) 2015 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This file is distributed in the hope that it will be useful
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include "skeleton.dtsi"
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/interrupt-controller/irq.h>
  50
  51 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  52
  53 / {
  54         model = "Marvell Armada 39x family SoC";
  55         compatible = "marvell,armada390";
  56
  57         aliases {
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60                 serial2 = &uart2;
  61                 serial3 = &uart3;
  62         };
  63
  64         cpus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67                 enable-method = "marvell,armada-390-smp";
  68
  69                 cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a9";
  72                         reg = <0>;
  73                 };
  74                 cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a9";
  77                         reg = <1>;
  78                 };
  79         };
  80
  81         pmu {
  82                 compatible = "arm,cortex-a9-pmu";
  83                 interrupts-extended = <&mpic 3>;
  84         };
  85
  86         soc {
  87                 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
  88                              "simple-bus";
  89                 #address-cells = <2>;
  90                 #size-cells = <1>;
  91                 controller = <&mbusc>;
  92                 interrupt-parent = <&gic>;
  93                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  94                 pcie-io-aperture  = <0xe8000000 0x100000>;
  95
  96                 bootrom {
  97                         compatible = "marvell,bootrom";
  98                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  99                 };
 100
 101                 internal-regs {
 102                         compatible = "simple-bus";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 106
 107                         L2: cache-controller@8000 {
 108                                 compatible = "arm,pl310-cache";
 109                                 reg = <0x8000 0x1000>;
 110                                 cache-unified;
 111                                 cache-level = <2>;
 112                                 arm,double-linefill-incr = <1>;
 113                                 arm,double-linefill-wrap = <0>;
 114                                 arm,double-linefill = <1>;
 115                                 prefetch-data = <1>;
 116                         };
 117
 118                         scu@c000 {
 119                                 compatible = "arm,cortex-a9-scu";
 120                                 reg = <0xc000 0x100>;
 121                         };
 122
 123                         timer@c600 {
 124                                 compatible = "arm,cortex-a9-twd-timer";
 125                                 reg = <0xc600 0x20>;
 126                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 127                                 clocks = <&coreclk 2>;
 128                         };
 129
 130                         gic: interrupt-controller@d000 {
 131                                 compatible = "arm,cortex-a9-gic";
 132                                 #interrupt-cells = <3>;
 133                                 #size-cells = <0>;
 134                                 interrupt-controller;
 135                                 reg = <0xd000 0x1000>,
 136                                       <0xc100 0x100>;
 137                         };
 138
 139                         i2c0: i2c@11000 {
 140                                 compatible = "marvell,mv64xxx-i2c";
 141                                 reg = <0x11000 0x20>;
 142                                 #address-cells = <1>;
 143                                 #size-cells = <0>;
 144                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 145                                 timeout-ms = <1000>;
 146                                 clocks = <&coreclk 0>;
 147                                 status = "disabled";
 148                         };
 149
 150                         i2c1: i2c@11100 {
 151                                 compatible = "marvell,mv64xxx-i2c";
 152                                 reg = <0x11100 0x20>;
 153                                 #address-cells = <1>;
 154                                 #size-cells = <0>;
 155                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 156                                 timeout-ms = <1000>;
 157                                 clocks = <&coreclk 0>;
 158                                 status = "disabled";
 159                         };
 160
 161                         i2c2: i2c@11200 {
 162                                 compatible = "marvell,mv64xxx-i2c";
 163                                 reg = <0x11200 0x20>;
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 167                                 timeout-ms = <1000>;
 168                                 clocks = <&coreclk 0>;
 169                                 status = "disabled";
 170                         };
 171
 172                         i2c3: i2c@11300 {
 173                                 compatible = "marvell,mv64xxx-i2c";
 174                                 reg = <0x11300 0x20>;
 175                                 #address-cells = <1>;
 176                                 #size-cells = <0>;
 177                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 178                                 timeout-ms = <1000>;
 179                                 clocks = <&coreclk 0>;
 180                                 status = "disabled";
 181                         };
 182
 183                         uart0: serial@12000 {
 184                                 compatible = "snps,dw-apb-uart";
 185                                 reg = <0x12000 0x100>;
 186                                 reg-shift = <2>;
 187                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 188                                 reg-io-width = <1>;
 189                                 clocks = <&coreclk 0>;
 190                                 status = "disabled";
 191                         };
 192
 193                         uart1: serial@12100 {
 194                                 compatible = "snps,dw-apb-uart";
 195                                 reg = <0x12100 0x100>;
 196                                 reg-shift = <2>;
 197                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 198                                 reg-io-width = <1>;
 199                                 clocks = <&coreclk 0>;
 200                                 status = "disabled";
 201                         };
 202
 203                         uart2: serial@12200 {
 204                                 compatible = "snps,dw-apb-uart";
 205                                 reg = <0x12200 0x100>;
 206                                 reg-shift = <2>;
 207                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 208                                 reg-io-width = <1>;
 209                                 clocks = <&coreclk 0>;
 210                                 status = "disabled";
 211                         };
 212
 213                         uart3: serial@12300 {
 214                                 compatible = "snps,dw-apb-uart";
 215                                 reg = <0x12300 0x100>;
 216                                 reg-shift = <2>;
 217                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 218                                 reg-io-width = <1>;
 219                                 clocks = <&coreclk 0>;
 220                                 status = "disabled";
 221                         };
 222
 223                         pinctrl@18000 {
 224                                 i2c0_pins: i2c0-pins {
 225                                         marvell,pins = "mpp2", "mpp3";
 226                                         marvell,function = "i2c0";
 227                                 };
 228
 229                                 uart0_pins: uart0-pins {
 230                                         marvell,pins = "mpp0", "mpp1";
 231                                         marvell,function = "ua0";
 232                                 };
 233
 234                                 uart1_pins: uart1-pins {
 235                                         marvell,pins = "mpp19", "mpp20";
 236                                         marvell,function = "ua1";
 237                                 };
 238
 239                                 spi1_pins: spi1-pins {
 240                                         marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
 241                                         marvell,function = "spi1";
 242                                 };
 243
 244                                 nand_pins: nand-pins {
 245                                         marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
 246                                                        "mpp38", "mpp28", "mpp40", "mpp42",
 247                                                        "mpp35", "mpp36", "mpp25", "mpp30",
 248                                                        "mpp32";
 249                                         marvell,function = "dev";
 250                                 };
 251                         };
 252
 253                         system-controller@18200 {
 254                                 compatible = "marvell,armada-390-system-controller",
 255                                              "marvell,armada-370-xp-system-controller";
 256                                 reg = <0x18200 0x100>;
 257                         };
 258
 259                         gateclk: clock-gating-control@18220 {
 260                                 compatible = "marvell,armada-390-gating-clock";
 261                                 reg = <0x18220 0x4>;
 262                                 clocks = <&coreclk 0>;
 263                                 #clock-cells = <1>;
 264                         };
 265
 266                         coreclk: mvebu-sar@18600 {
 267                                 compatible = "marvell,armada-390-core-clock";
 268                                 reg = <0x18600 0x04>;
 269                                 #clock-cells = <1>;
 270                         };
 271
 272                         mbusc: mbus-controller@20000 {
 273                                 compatible = "marvell,mbus-controller";
 274                                 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
 275                         };
 276
 277                         mpic: interrupt-controller@20a00 {
 278                                 compatible = "marvell,mpic";
 279                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 280                                 #interrupt-cells = <1>;
 281                                 #size-cells = <1>;
 282                                 interrupt-controller;
 283                                 msi-controller;
 284                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 285                         };
 286
 287                         timer@20300 {
 288                                 compatible = "marvell,armada-380-timer",
 289                                              "marvell,armada-xp-timer";
 290                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 291                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 292                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 293                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 294                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 295                                                       <&mpic 5>,
 296                                                       <&mpic 6>;
 297                                 clocks = <&coreclk 2>, <&coreclk 5>;
 298                                 clock-names = "nbclk", "fixed";
 299                         };
 300
 301                         watchdog@20300 {
 302                                 compatible = "marvell,armada-380-wdt";
 303                                 reg = <0x20300 0x34>, <0x20704 0x4>,
 304                                       <0x18260 0x4>;
 305                                 clocks = <&coreclk 2>, <&refclk>;
 306                                 clock-names = "nbclk", "fixed";
 307                         };
 308
 309                         cpurst@20800 {
 310                                 compatible = "marvell,armada-370-cpu-reset";
 311                                 reg = <0x20800 0x10>;
 312                         };
 313
 314                         mpcore-soc-ctrl@20d20 {
 315                                 compatible = "marvell,armada-380-mpcore-soc-ctrl";
 316                                 reg = <0x20d20 0x6c>;
 317                         };
 318
 319                         coherency-fabric@21010 {
 320                                 compatible = "marvell,armada-380-coherency-fabric";
 321                                 reg = <0x21010 0x1c>;
 322                         };
 323
 324                         pmsu@22000 {
 325                                 compatible = "marvell,armada-390-pmsu",
 326                                              "marvell,armada-380-pmsu";
 327                                 reg = <0x22000 0x1000>;
 328                         };
 329
 330                         xor@60800 {
 331                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
 332                                 reg = <0x60800 0x100
 333                                        0x60a00 0x100>;
 334                                 clocks = <&gateclk 22>;
 335                                 status = "okay";
 336
 337                                 xor00 {
 338                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 339                                         dmacap,memcpy;
 340                                         dmacap,xor;
 341                                 };
 342                                 xor01 {
 343                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 344                                         dmacap,memcpy;
 345                                         dmacap,xor;
 346                                         dmacap,memset;
 347                                 };
 348                         };
 349
 350                         xor@60900 {
 351                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
 352                                 reg = <0x60900 0x100
 353                                        0x60b00 0x100>;
 354                                 clocks = <&gateclk 28>;
 355                                 status = "okay";
 356
 357                                 xor10 {
 358                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 359                                         dmacap,memcpy;
 360                                         dmacap,xor;
 361                                 };
 362                                 xor11 {
 363                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 364                                         dmacap,memcpy;
 365                                         dmacap,xor;
 366                                         dmacap,memset;
 367                                 };
 368                         };
 369
 370                         flash@d0000 {
 371                                 compatible = "marvell,armada370-nand";
 372                                 reg = <0xd0000 0x54>;
 373                                 #address-cells = <1>;
 374                                 #size-cells = <1>;
 375                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&coredivclk 0>;
 377                                 status = "disabled";
 378                         };
 379
 380                         sdhci@d8000 {
 381                                 compatible = "marvell,armada-380-sdhci";
 382                                 reg-names = "sdhci", "mbus", "conf-sdio3";
 383                                 reg = <0xd8000 0x1000>,
 384                                         <0xdc000 0x100>,
 385                                         <0x18454 0x4>;
 386                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&gateclk 17>;
 388                                 mrvl,clk-delay-cycles = <0x1F>;
 389                                 status = "disabled";
 390                         };
 391
 392                         coredivclk: clock@e4250 {
 393                                 compatible = "marvell,armada-390-corediv-clock",
 394                                              "marvell,armada-380-corediv-clock";
 395                                 reg = <0xe4250 0xc>;
 396                                 #clock-cells = <1>;
 397                                 clocks = <&mainpll>;
 398                                 clock-output-names = "nand";
 399                         };
 400
 401                         thermal@e8078 {
 402                                 compatible = "marvell,armada380-thermal";
 403                                 reg = <0xe4078 0x4>, <0xe4074 0x4>;
 404                                 status = "okay";
 405                         };
 406                 };
 407
 408                 pcie-controller {
 409                         compatible = "marvell,armada-370-pcie";
 410                         status = "disabled";
 411                         device_type = "pci";
 412
 413                         #address-cells = <3>;
 414                         #size-cells = <2>;
 415
 416                         msi-parent = <&mpic>;
 417                         bus-range = <0x00 0xff>;
 418
 419                         ranges =
 420                                <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
 421                                 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 422                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 423                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
 424                                 0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
 425                                 0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
 426                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
 427                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
 428                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
 429                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
 430                                 0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
 431                                 0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
 432
 433                         /*
 434                          * This port can be either x4 or x1. When
 435                          * configured in x4 by the bootloader, then
 436                          * pcie@4,0 is not available.
 437                          */
 438                         pcie@1,0 {
 439                                 device_type = "pci";
 440                                 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 441                                 reg = <0x0800 0 0 0 0>;
 442                                 #address-cells = <3>;
 443                                 #size-cells = <2>;
 444                                 #interrupt-cells = <1>;
 445                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 446                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 447                                 interrupt-map-mask = <0 0 0 0>;
 448                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 449                                 marvell,pcie-port = <0>;
 450                                 marvell,pcie-lane = <0>;
 451                                 clocks = <&gateclk 8>;
 452                                 status = "disabled";
 453                         };
 454
 455                         /* x1 port */
 456                         pcie@2,0 {
 457                                 device_type = "pci";
 458                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 459                                 reg = <0x1000 0 0 0 0>;
 460                                 #address-cells = <3>;
 461                                 #size-cells = <2>;
 462                                 #interrupt-cells = <1>;
 463                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 464                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 465                                 interrupt-map-mask = <0 0 0 0>;
 466                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 467                                 marvell,pcie-port = <1>;
 468                                 marvell,pcie-lane = <0>;
 469                                 clocks = <&gateclk 5>;
 470                                 status = "disabled";
 471                         };
 472
 473                         /* x1 port */
 474                         pcie@3,0 {
 475                                 device_type = "pci";
 476                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 477                                 reg = <0x1800 0 0 0 0>;
 478                                 #address-cells = <3>;
 479                                 #size-cells = <2>;
 480                                 #interrupt-cells = <1>;
 481                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 482                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 483                                 interrupt-map-mask = <0 0 0 0>;
 484                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 485                                 marvell,pcie-port = <2>;
 486                                 marvell,pcie-lane = <0>;
 487                                 clocks = <&gateclk 6>;
 488                                 status = "disabled";
 489                         };
 490
 491                         /*
 492                          * x1 port only available when pcie@1,0 is
 493                          * configured as a x1 port
 494                          */
 495                         pcie@4,0 {
 496                                 device_type = "pci";
 497                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 498                                 reg = <0x2000 0 0 0 0>;
 499                                 #address-cells = <3>;
 500                                 #size-cells = <2>;
 501                                 #interrupt-cells = <1>;
 502                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 503                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 504                                 interrupt-map-mask = <0 0 0 0>;
 505                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 506                                 marvell,pcie-port = <3>;
 507                                 marvell,pcie-lane = <0>;
 508                                 clocks = <&gateclk 7>;
 509                                 status = "disabled";
 510                         };
 511                 };
 512
 513                 spi0: spi@10600 {
 514                         compatible = "marvell,armada-390-spi",
 515                                         "marvell,orion-spi";
 516                         reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         cell-index = <0>;
 520                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&coreclk 0>;
 522                         status = "disabled";
 523                 };
 524
 525                 spi1: spi@10680 {
 526                         compatible = "marvell,armada-390-spi",
 527                                         "marvell,orion-spi";
 528                         reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         cell-index = <1>;
 532                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&coreclk 0>;
 534                         status = "disabled";
 535                 };
 536         };
 537
 538         clocks {
 539                 /* 2 GHz fixed main PLL */
 540                 mainpll: mainpll {
 541                         compatible = "fixed-clock";
 542                         #clock-cells = <0>;
 543                         clock-frequency = <1000000000>;
 544                 };
 545
 546                 /* 25 MHz reference crystal */
 547                 refclk: oscillator {
 548                         compatible = "fixed-clock";
 549                         #clock-cells = <0>;
 550                         clock-frequency = <25000000>;
 551                 };
 552         };
 553 };