1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
5 * Copyright (C) 2014 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 38x family SoC";
22 compatible = "marvell,armada380";
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
46 compatible = "marvell,bootrom";
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
101 compatible = "simple-bus";
102 #address-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
106 sdramc: sdramc@1400 {
107 compatible = "marvell,armada-xp-sdram-controller";
108 reg = <0x1400 0x500>;
111 L2: cache-controller@8000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x8000 0x1000>;
116 arm,double-linefill-incr = <0>;
117 arm,double-linefill-wrap = <0>;
118 arm,double-linefill = <0>;
123 compatible = "arm,cortex-a9-scu";
128 compatible = "arm,cortex-a9-global-timer";
130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
131 clocks = <&coreclk 2>;
135 compatible = "arm,cortex-a9-twd-timer";
137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
138 clocks = <&coreclk 2>;
141 gic: interrupt-controller@d000 {
142 compatible = "arm,cortex-a9-gic";
143 #interrupt-cells = <3>;
145 interrupt-controller;
146 reg = <0xd000 0x1000>,
151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
152 reg = <0x11000 0x20>;
153 #address-cells = <1>;
155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&coreclk 0>;
162 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
163 reg = <0x11100 0x20>;
164 #address-cells = <1>;
166 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&coreclk 0>;
172 uart0: serial@12000 {
173 compatible = "marvell,armada-38x-uart";
174 reg = <0x12000 0x100>;
176 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&coreclk 0>;
182 uart1: serial@12100 {
183 compatible = "marvell,armada-38x-uart";
184 reg = <0x12100 0x100>;
186 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&coreclk 0>;
192 pinctrl: pinctrl@18000 {
193 reg = <0x18000 0x20>;
195 ge0_rgmii_pins: ge-rgmii-pins-0 {
196 marvell,pins = "mpp6", "mpp7", "mpp8",
197 "mpp9", "mpp10", "mpp11",
198 "mpp12", "mpp13", "mpp14",
199 "mpp15", "mpp16", "mpp17";
200 marvell,function = "ge0";
203 ge1_rgmii_pins: ge-rgmii-pins-1 {
204 marvell,pins = "mpp21", "mpp27", "mpp28",
205 "mpp29", "mpp30", "mpp31",
206 "mpp32", "mpp37", "mpp38",
207 "mpp39", "mpp40", "mpp41";
208 marvell,function = "ge1";
211 i2c0_pins: i2c-pins-0 {
212 marvell,pins = "mpp2", "mpp3";
213 marvell,function = "i2c0";
216 mdio_pins: mdio-pins {
217 marvell,pins = "mpp4", "mpp5";
218 marvell,function = "ge";
221 ref_clk0_pins: ref-clk-pins-0 {
222 marvell,pins = "mpp45";
223 marvell,function = "ref";
226 ref_clk1_pins: ref-clk-pins-1 {
227 marvell,pins = "mpp46";
228 marvell,function = "ref";
231 spi0_pins: spi-pins-0 {
232 marvell,pins = "mpp22", "mpp23", "mpp24",
234 marvell,function = "spi0";
237 spi1_pins: spi-pins-1 {
238 marvell,pins = "mpp56", "mpp57", "mpp58",
240 marvell,function = "spi1";
243 nand_pins: nand-pins {
244 marvell,pins = "mpp22", "mpp34", "mpp23",
245 "mpp33", "mpp38", "mpp28",
246 "mpp40", "mpp42", "mpp35",
247 "mpp36", "mpp25", "mpp30",
249 marvell,function = "dev";
253 marvell,pins = "mpp41";
254 marvell,function = "nand";
257 uart0_pins: uart-pins-0 {
258 marvell,pins = "mpp0", "mpp1";
259 marvell,function = "ua0";
262 uart1_pins: uart-pins-1 {
263 marvell,pins = "mpp19", "mpp20";
264 marvell,function = "ua1";
267 sdhci_pins: sdhci-pins {
268 marvell,pins = "mpp48", "mpp49", "mpp50",
269 "mpp52", "mpp53", "mpp54",
270 "mpp55", "mpp57", "mpp58",
272 marvell,function = "sd0";
275 sata0_pins: sata-pins-0 {
276 marvell,pins = "mpp20";
277 marvell,function = "sata0";
280 sata1_pins: sata-pins-1 {
281 marvell,pins = "mpp19";
282 marvell,function = "sata1";
285 sata2_pins: sata-pins-2 {
286 marvell,pins = "mpp47";
287 marvell,function = "sata2";
290 sata3_pins: sata-pins-3 {
291 marvell,pins = "mpp44";
292 marvell,function = "sata3";
297 compatible = "marvell,armada-370-gpio",
298 "marvell,orion-gpio";
299 reg = <0x18100 0x40>, <0x181c0 0x08>;
300 reg-names = "gpio", "pwm";
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&coreclk 0>;
315 compatible = "marvell,armada-370-gpio",
316 "marvell,orion-gpio";
317 reg = <0x18140 0x40>, <0x181c8 0x08>;
318 reg-names = "gpio", "pwm";
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&coreclk 0>;
332 systemc: system-controller@18200 {
333 compatible = "marvell,armada-380-system-controller",
334 "marvell,armada-370-xp-system-controller";
335 reg = <0x18200 0x100>;
338 gateclk: clock-gating-control@18220 {
339 compatible = "marvell,armada-380-gating-clock";
341 clocks = <&coreclk 0>;
346 compatible = "marvell,armada-380-comphy";
347 reg = <0x18300 0x100>;
348 #address-cells = <1>;
382 coreclk: mvebu-sar@18600 {
383 compatible = "marvell,armada-380-core-clock";
384 reg = <0x18600 0x04>;
388 mbusc: mbus-controller@20000 {
389 compatible = "marvell,mbus-controller";
390 reg = <0x20000 0x100>, <0x20180 0x20>,
394 mpic: interrupt-controller@20a00 {
395 compatible = "marvell,mpic";
396 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
397 #interrupt-cells = <1>;
399 interrupt-controller;
401 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
405 compatible = "marvell,armada-380-timer",
406 "marvell,armada-xp-timer";
407 reg = <0x20300 0x30>, <0x21040 0x30>;
408 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
409 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
410 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
411 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
414 clocks = <&coreclk 2>, <&refclk>;
415 clock-names = "nbclk", "fixed";
418 watchdog: watchdog@20300 {
419 compatible = "marvell,armada-380-wdt";
420 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
421 clocks = <&coreclk 2>, <&refclk>;
422 clock-names = "nbclk", "fixed";
423 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
424 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
427 cpurst: cpurst@20800 {
428 compatible = "marvell,armada-370-cpu-reset";
429 reg = <0x20800 0x10>;
432 mpcore-soc-ctrl@20d20 {
433 compatible = "marvell,armada-380-mpcore-soc-ctrl";
434 reg = <0x20d20 0x6c>;
437 coherencyfab: coherency-fabric@21010 {
438 compatible = "marvell,armada-380-coherency-fabric";
439 reg = <0x21010 0x1c>;
443 compatible = "marvell,armada-380-pmsu";
444 reg = <0x22000 0x1000>;
448 * As a special exception to the "order by
449 * register address" rule, the eth0 node is
450 * placed here to ensure that it gets
451 * registered as the first interface, since
452 * the network subsystem doesn't allow naming
453 * interfaces using DT aliases. Without this,
454 * the ordering of interfaces is different
455 * from the one used in U-Boot and the
456 * labeling of interfaces on the boards, which
457 * is very confusing for users.
459 eth0: ethernet@70000 {
460 compatible = "marvell,armada-370-neta";
461 reg = <0x70000 0x4000>;
462 interrupts-extended = <&mpic 8>;
463 clocks = <&gateclk 4>;
464 tx-csum-limit = <9800>;
468 eth1: ethernet@30000 {
469 compatible = "marvell,armada-370-neta";
470 reg = <0x30000 0x4000>;
471 interrupts-extended = <&mpic 10>;
472 clocks = <&gateclk 3>;
476 eth2: ethernet@34000 {
477 compatible = "marvell,armada-370-neta";
478 reg = <0x34000 0x4000>;
479 interrupts-extended = <&mpic 12>;
480 clocks = <&gateclk 2>;
485 compatible = "marvell,orion-ehci";
486 reg = <0x58000 0x500>;
487 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&gateclk 18>;
493 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
496 clocks = <&gateclk 22>;
500 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
505 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
513 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
516 clocks = <&gateclk 28>;
520 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
525 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
535 compatible = "marvell,orion-mdio";
537 clocks = <&gateclk 4>;
541 compatible = "marvell,armada-38x-crypto";
542 reg = <0x90000 0x10000>;
544 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&gateclk 23>, <&gateclk 21>,
547 <&gateclk 14>, <&gateclk 16>;
548 clock-names = "cesa0", "cesa1",
550 marvell,crypto-srams = <&crypto_sram0>,
552 marvell,crypto-sram-size = <0x800>;
556 compatible = "marvell,armada-380-rtc";
557 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
558 reg-names = "rtc", "rtc-soc";
559 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
563 compatible = "marvell,armada-380-ahci";
564 reg = <0xa8000 0x2000>;
565 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&gateclk 15>;
571 compatible = "marvell,armada-380-neta-bm";
572 reg = <0xc8000 0xac>;
573 clocks = <&gateclk 13>;
574 internal-mem = <&bm_bppi>;
579 compatible = "marvell,armada-380-ahci";
580 reg = <0xe0000 0x2000>;
581 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&gateclk 30>;
586 coredivclk: clock@e4250 {
587 compatible = "marvell,armada-380-corediv-clock";
591 clock-output-names = "nand";
594 thermal: thermal@e8078 {
595 compatible = "marvell,armada380-thermal";
596 reg = <0xe4078 0x4>, <0xe4070 0x8>;
600 nand_controller: nand-controller@d0000 {
601 compatible = "marvell,armada370-nand-controller";
602 reg = <0xd0000 0x54>;
603 #address-cells = <1>;
605 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&coredivclk 0>;
611 compatible = "marvell,armada-380-sdhci";
612 reg-names = "sdhci", "mbus", "conf-sdio3";
613 reg = <0xd8000 0x1000>,
616 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&gateclk 17>;
618 mrvl,clk-delay-cycles = <0x1F>;
623 compatible = "marvell,armada-380-xhci";
624 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
625 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&gateclk 9>;
631 compatible = "marvell,armada-380-xhci";
632 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
633 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gateclk 10>;
639 crypto_sram0: sa-sram0 {
640 compatible = "mmio-sram";
641 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
642 clocks = <&gateclk 23>;
643 #address-cells = <1>;
645 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
648 crypto_sram1: sa-sram1 {
649 compatible = "mmio-sram";
650 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
651 clocks = <&gateclk 21>;
652 #address-cells = <1>;
654 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
658 compatible = "mmio-sram";
659 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
660 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
661 #address-cells = <1>;
663 clocks = <&gateclk 13>;
669 compatible = "marvell,armada-380-spi",
671 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
672 #address-cells = <1>;
675 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&coreclk 0>;
681 compatible = "marvell,armada-380-spi",
683 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
684 #address-cells = <1>;
687 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&coreclk 0>;
694 /* 1 GHz fixed main PLL */
696 compatible = "fixed-clock";
698 clock-frequency = <1000000000>;
701 /* 25 MHz reference crystal */
703 compatible = "fixed-clock";
705 clock-frequency = <25000000>;