1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
5 * Copyright (C) 2014 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 38x family SoC";
22 compatible = "marvell,armada380";
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
46 compatible = "marvell,bootrom";
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
101 compatible = "simple-bus";
102 #address-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
106 L2: cache-controller@8000 {
107 compatible = "arm,pl310-cache";
108 reg = <0x8000 0x1000>;
111 arm,double-linefill-incr = <0>;
112 arm,double-linefill-wrap = <0>;
113 arm,double-linefill = <0>;
118 compatible = "arm,cortex-a9-scu";
123 compatible = "arm,cortex-a9-global-timer";
125 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
126 clocks = <&coreclk 2>;
130 compatible = "arm,cortex-a9-twd-timer";
132 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
133 clocks = <&coreclk 2>;
136 gic: interrupt-controller@d000 {
137 compatible = "arm,cortex-a9-gic";
138 #interrupt-cells = <3>;
140 interrupt-controller;
141 reg = <0xd000 0x1000>,
146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
147 reg = <0x11000 0x20>;
148 #address-cells = <1>;
150 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&coreclk 0>;
157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
158 reg = <0x11100 0x20>;
159 #address-cells = <1>;
161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&coreclk 0>;
167 uart0: serial@12000 {
168 compatible = "marvell,armada-38x-uart";
169 reg = <0x12000 0x100>;
171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&coreclk 0>;
177 uart1: serial@12100 {
178 compatible = "marvell,armada-38x-uart";
179 reg = <0x12100 0x100>;
181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&coreclk 0>;
187 pinctrl: pinctrl@18000 {
188 reg = <0x18000 0x20>;
190 ge0_rgmii_pins: ge-rgmii-pins-0 {
191 marvell,pins = "mpp6", "mpp7", "mpp8",
192 "mpp9", "mpp10", "mpp11",
193 "mpp12", "mpp13", "mpp14",
194 "mpp15", "mpp16", "mpp17";
195 marvell,function = "ge0";
198 ge1_rgmii_pins: ge-rgmii-pins-1 {
199 marvell,pins = "mpp21", "mpp27", "mpp28",
200 "mpp29", "mpp30", "mpp31",
201 "mpp32", "mpp37", "mpp38",
202 "mpp39", "mpp40", "mpp41";
203 marvell,function = "ge1";
206 i2c0_pins: i2c-pins-0 {
207 marvell,pins = "mpp2", "mpp3";
208 marvell,function = "i2c0";
211 mdio_pins: mdio-pins {
212 marvell,pins = "mpp4", "mpp5";
213 marvell,function = "ge";
216 ref_clk0_pins: ref-clk-pins-0 {
217 marvell,pins = "mpp45";
218 marvell,function = "ref";
221 ref_clk1_pins: ref-clk-pins-1 {
222 marvell,pins = "mpp46";
223 marvell,function = "ref";
226 spi0_pins: spi-pins-0 {
227 marvell,pins = "mpp22", "mpp23", "mpp24",
229 marvell,function = "spi0";
232 spi1_pins: spi-pins-1 {
233 marvell,pins = "mpp56", "mpp57", "mpp58",
235 marvell,function = "spi1";
238 nand_pins: nand-pins {
239 marvell,pins = "mpp22", "mpp34", "mpp23",
240 "mpp33", "mpp38", "mpp28",
241 "mpp40", "mpp42", "mpp35",
242 "mpp36", "mpp25", "mpp30",
244 marvell,function = "dev";
248 marvell,pins = "mpp41";
249 marvell,function = "nand";
252 uart0_pins: uart-pins-0 {
253 marvell,pins = "mpp0", "mpp1";
254 marvell,function = "ua0";
257 uart1_pins: uart-pins-1 {
258 marvell,pins = "mpp19", "mpp20";
259 marvell,function = "ua1";
262 sdhci_pins: sdhci-pins {
263 marvell,pins = "mpp48", "mpp49", "mpp50",
264 "mpp52", "mpp53", "mpp54",
265 "mpp55", "mpp57", "mpp58",
267 marvell,function = "sd0";
270 sata0_pins: sata-pins-0 {
271 marvell,pins = "mpp20";
272 marvell,function = "sata0";
275 sata1_pins: sata-pins-1 {
276 marvell,pins = "mpp19";
277 marvell,function = "sata1";
280 sata2_pins: sata-pins-2 {
281 marvell,pins = "mpp47";
282 marvell,function = "sata2";
285 sata3_pins: sata-pins-3 {
286 marvell,pins = "mpp44";
287 marvell,function = "sata3";
292 compatible = "marvell,armada-370-gpio",
293 "marvell,orion-gpio";
294 reg = <0x18100 0x40>, <0x181c0 0x08>;
295 reg-names = "gpio", "pwm";
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&coreclk 0>;
310 compatible = "marvell,armada-370-gpio",
311 "marvell,orion-gpio";
312 reg = <0x18140 0x40>, <0x181c8 0x08>;
313 reg-names = "gpio", "pwm";
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&coreclk 0>;
327 systemc: system-controller@18200 {
328 compatible = "marvell,armada-380-system-controller",
329 "marvell,armada-370-xp-system-controller";
330 reg = <0x18200 0x100>;
333 gateclk: clock-gating-control@18220 {
334 compatible = "marvell,armada-380-gating-clock";
336 clocks = <&coreclk 0>;
341 compatible = "marvell,armada-380-comphy";
342 reg = <0x18300 0x100>;
343 #address-cells = <1>;
377 coreclk: mvebu-sar@18600 {
378 compatible = "marvell,armada-380-core-clock";
379 reg = <0x18600 0x04>;
383 mbusc: mbus-controller@20000 {
384 compatible = "marvell,mbus-controller";
385 reg = <0x20000 0x100>, <0x20180 0x20>,
389 mpic: interrupt-controller@20a00 {
390 compatible = "marvell,mpic";
391 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
392 #interrupt-cells = <1>;
394 interrupt-controller;
396 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
400 compatible = "marvell,armada-380-timer",
401 "marvell,armada-xp-timer";
402 reg = <0x20300 0x30>, <0x21040 0x30>;
403 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
404 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
405 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
406 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
409 clocks = <&coreclk 2>, <&refclk>;
410 clock-names = "nbclk", "fixed";
413 watchdog: watchdog@20300 {
414 compatible = "marvell,armada-380-wdt";
415 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
416 clocks = <&coreclk 2>, <&refclk>;
417 clock-names = "nbclk", "fixed";
418 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
419 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
422 cpurst: cpurst@20800 {
423 compatible = "marvell,armada-370-cpu-reset";
424 reg = <0x20800 0x10>;
427 mpcore-soc-ctrl@20d20 {
428 compatible = "marvell,armada-380-mpcore-soc-ctrl";
429 reg = <0x20d20 0x6c>;
432 coherencyfab: coherency-fabric@21010 {
433 compatible = "marvell,armada-380-coherency-fabric";
434 reg = <0x21010 0x1c>;
438 compatible = "marvell,armada-380-pmsu";
439 reg = <0x22000 0x1000>;
443 * As a special exception to the "order by
444 * register address" rule, the eth0 node is
445 * placed here to ensure that it gets
446 * registered as the first interface, since
447 * the network subsystem doesn't allow naming
448 * interfaces using DT aliases. Without this,
449 * the ordering of interfaces is different
450 * from the one used in U-Boot and the
451 * labeling of interfaces on the boards, which
452 * is very confusing for users.
454 eth0: ethernet@70000 {
455 compatible = "marvell,armada-370-neta";
456 reg = <0x70000 0x4000>;
457 interrupts-extended = <&mpic 8>;
458 clocks = <&gateclk 4>;
459 tx-csum-limit = <9800>;
463 eth1: ethernet@30000 {
464 compatible = "marvell,armada-370-neta";
465 reg = <0x30000 0x4000>;
466 interrupts-extended = <&mpic 10>;
467 clocks = <&gateclk 3>;
471 eth2: ethernet@34000 {
472 compatible = "marvell,armada-370-neta";
473 reg = <0x34000 0x4000>;
474 interrupts-extended = <&mpic 12>;
475 clocks = <&gateclk 2>;
480 compatible = "marvell,orion-ehci";
481 reg = <0x58000 0x500>;
482 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&gateclk 18>;
488 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
491 clocks = <&gateclk 22>;
495 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
500 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
508 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
511 clocks = <&gateclk 28>;
515 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
520 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
528 #address-cells = <1>;
530 compatible = "marvell,orion-mdio";
532 clocks = <&gateclk 4>;
536 compatible = "marvell,armada-38x-crypto";
537 reg = <0x90000 0x10000>;
539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&gateclk 23>, <&gateclk 21>,
542 <&gateclk 14>, <&gateclk 16>;
543 clock-names = "cesa0", "cesa1",
545 marvell,crypto-srams = <&crypto_sram0>,
547 marvell,crypto-sram-size = <0x800>;
551 compatible = "marvell,armada-380-rtc";
552 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
553 reg-names = "rtc", "rtc-soc";
554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
558 compatible = "marvell,armada-380-ahci";
559 reg = <0xa8000 0x2000>;
560 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gateclk 15>;
566 compatible = "marvell,armada-380-neta-bm";
567 reg = <0xc8000 0xac>;
568 clocks = <&gateclk 13>;
569 internal-mem = <&bm_bppi>;
574 compatible = "marvell,armada-380-ahci";
575 reg = <0xe0000 0x2000>;
576 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gateclk 30>;
581 coredivclk: clock@e4250 {
582 compatible = "marvell,armada-380-corediv-clock";
586 clock-output-names = "nand";
589 thermal: thermal@e8078 {
590 compatible = "marvell,armada380-thermal";
591 reg = <0xe4078 0x4>, <0xe4070 0x8>;
595 nand_controller: nand-controller@d0000 {
596 compatible = "marvell,armada370-nand-controller";
597 reg = <0xd0000 0x54>;
598 #address-cells = <1>;
600 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&coredivclk 0>;
606 compatible = "marvell,armada-380-sdhci";
607 reg-names = "sdhci", "mbus", "conf-sdio3";
608 reg = <0xd8000 0x1000>,
611 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&gateclk 17>;
613 mrvl,clk-delay-cycles = <0x1F>;
618 compatible = "marvell,armada-380-xhci";
619 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
620 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&gateclk 9>;
626 compatible = "marvell,armada-380-xhci";
627 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
628 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&gateclk 10>;
634 crypto_sram0: sa-sram0 {
635 compatible = "mmio-sram";
636 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
637 clocks = <&gateclk 23>;
638 #address-cells = <1>;
640 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
643 crypto_sram1: sa-sram1 {
644 compatible = "mmio-sram";
645 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
646 clocks = <&gateclk 21>;
647 #address-cells = <1>;
649 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
653 compatible = "mmio-sram";
654 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
655 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
656 #address-cells = <1>;
658 clocks = <&gateclk 13>;
664 compatible = "marvell,armada-380-spi",
666 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
667 #address-cells = <1>;
670 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&coreclk 0>;
676 compatible = "marvell,armada-380-spi",
678 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
679 #address-cells = <1>;
682 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&coreclk 0>;
689 /* 1 GHz fixed main PLL */
691 compatible = "fixed-clock";
693 clock-frequency = <1000000000>;
696 /* 25 MHz reference crystal */
698 compatible = "fixed-clock";
700 clock-frequency = <25000000>;