1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree file for the Turris Omnia
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include "armada-385.dtsi"
19 model = "Turris Omnia";
20 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
27 device_type = "memory";
28 reg = <0x00000000 0x40000000>; /* 1024 MB */
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
34 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
35 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
36 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
40 /* USB part of the PCIe2/USB 2.0 port */
50 pinctrl-names = "default";
51 pinctrl-0 = <&sdhci_pins>;
89 compatible = "sff,sfp";
91 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
92 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
93 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
94 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
95 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
96 maximum-power-milliwatt = <3000>;
99 * For now this has to be enabled at boot time by U-Boot when
100 * a SFP module is present. Read more in the comment in the
115 /* Connected to 88E6176 switch, port 6 */
117 pinctrl-names = "default";
118 pinctrl-0 = <&ge0_rgmii_pins>;
121 buffer-manager = <&bm>;
131 /* Connected to 88E6176 switch, port 5 */
133 pinctrl-names = "default";
134 pinctrl-0 = <&ge1_rgmii_pins>;
137 buffer-manager = <&bm>;
150 * eth2 is connected via a multiplexor to both the SFP cage and to
151 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
152 * a SFP module is present, as determined by the mode-def0 GPIO.
154 * Until kernel supports this configuration properly, in case SFP module
155 * is present, U-Boot has to enable the sfp node above, remove phy
156 * handle and add managed = "in-band-status" property.
160 phy-handle = <&phy1>;
163 buffer-manager = <&bm>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c0_pins>;
174 compatible = "nxp,pca9547";
175 #address-cells = <1>;
180 #address-cells = <1>;
184 /* STM32F0 command interface at address 0x2a */
187 compatible = "cznic,turris-omnia-leds";
189 #address-cells = <1>;
193 * LEDs are controlled by MCU (STM32F0) at
196 * The driver does not support HW control mode
197 * for the LEDs yet. Disable the LEDs for now.
199 * Also LED functions are not stable yet:
200 * - there are 3 LEDs connected via MCU to PCIe
201 * ports. One of these ports supports mSATA.
202 * There is no mSATA nor PCIe function.
203 * For now we use LED_FUNCTION_WLAN, since
204 * in most cases users have wifi cards in
206 * - there are 2 LEDs dedicated for user: A and
207 * B. Again there is no such function defined.
208 * For now we use LED_FUNCTION_INDICATOR
214 color = <LED_COLOR_ID_RGB>;
215 function = LED_FUNCTION_INDICATOR;
216 function-enumerator = <2>;
221 color = <LED_COLOR_ID_RGB>;
222 function = LED_FUNCTION_INDICATOR;
223 function-enumerator = <1>;
228 color = <LED_COLOR_ID_RGB>;
229 function = LED_FUNCTION_WLAN;
230 function-enumerator = <3>;
235 color = <LED_COLOR_ID_RGB>;
236 function = LED_FUNCTION_WLAN;
237 function-enumerator = <2>;
242 color = <LED_COLOR_ID_RGB>;
243 function = LED_FUNCTION_WLAN;
244 function-enumerator = <1>;
249 color = <LED_COLOR_ID_RGB>;
250 function = LED_FUNCTION_WAN;
255 color = <LED_COLOR_ID_RGB>;
256 function = LED_FUNCTION_LAN;
257 function-enumerator = <4>;
262 color = <LED_COLOR_ID_RGB>;
263 function = LED_FUNCTION_LAN;
264 function-enumerator = <3>;
269 color = <LED_COLOR_ID_RGB>;
270 function = LED_FUNCTION_LAN;
271 function-enumerator = <2>;
276 color = <LED_COLOR_ID_RGB>;
277 function = LED_FUNCTION_LAN;
278 function-enumerator = <1>;
283 color = <LED_COLOR_ID_RGB>;
284 function = LED_FUNCTION_LAN;
285 function-enumerator = <0>;
290 color = <LED_COLOR_ID_RGB>;
291 function = LED_FUNCTION_POWER;
296 compatible = "atmel,24c64";
299 /* The EEPROM contains data for bootloader.
301 * struct omnia_eeprom {
302 * u32 magic; (=0x0341a034 in LE)
303 * u32 ramsize; (in GiB)
312 #address-cells = <1>;
316 /* routed to PCIe0/mSATA connector (CN7A) */
320 #address-cells = <1>;
324 /* routed to PCIe1/USB2 connector (CN61A) */
328 #address-cells = <1>;
332 /* routed to PCIe2 connector (CN62A) */
336 #address-cells = <1>;
344 #address-cells = <1>;
348 /* ATSHA204A at address 0x64 */
352 #address-cells = <1>;
356 /* exposed on pin header */
360 #address-cells = <1>;
366 * GPIO expander for SFP+ signals and
369 compatible = "nxp,pca9538";
372 pinctrl-names = "default";
373 pinctrl-0 = <&pcawan_pins>;
375 interrupt-parent = <&gpio1>;
376 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&mdio_pins>;
390 phy1: ethernet-phy@1 {
391 compatible = "ethernet-phy-ieee802.3-c22";
393 marvell,reg-init = <3 18 0 0x4985>;
395 /* irq is connected to &pcawan pin 7 */
398 /* Switch MV88E6176 at address 0x10 */
400 pinctrl-names = "default";
401 pinctrl-0 = <&swint_pins>;
402 compatible = "marvell,mv88e6085";
403 #address-cells = <1>;
409 interrupt-parent = <&gpio1>;
410 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
413 #address-cells = <1>;
445 phy-mode = "rgmii-id";
453 /* port 6 is connected to eth0 */
459 pcawan_pins: pcawan-pins {
460 marvell,pins = "mpp46";
461 marvell,function = "gpio";
464 swint_pins: swint-pins {
465 marvell,pins = "mpp45";
466 marvell,function = "gpio";
469 spi0cs0_pins: spi0cs0-pins {
470 marvell,pins = "mpp25";
471 marvell,function = "spi0";
474 spi0cs1_pins: spi0cs1-pins {
475 marvell,pins = "mpp26";
476 marvell,function = "spi0";
481 pinctrl-names = "default";
482 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
486 compatible = "spansion,s25fl164k", "jedec,spi-nor";
487 #address-cells = <1>;
490 spi-max-frequency = <40000000>;
493 compatible = "fixed-partitions";
494 #address-cells = <1>;
498 reg = <0x0 0x00100000>;
503 reg = <0x00100000 0x00700000>;
504 label = "Rescue system";
509 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
513 /* Pin header CN10 */
514 pinctrl-names = "default";
515 pinctrl-0 = <&uart0_pins>;
520 /* Pin header CN11 */
521 pinctrl-names = "default";
522 pinctrl-0 = <&uart1_pins>;