1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board.
6 Copyright (C) 2020 Allied Telesis Labs
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
16 compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
19 stdout-path = "serial1:115200n8";
23 device_type = "memory";
24 reg = <0x00000000 0x40000000>; /* 1GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&uart0_pins>;
54 reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
55 reset-delay-us = <400000>;
63 compatible = "marvell,mvebu-devbus";
66 devbus,bus-width = <8>;
67 devbus,turn-off-ps = <60000>;
68 devbus,badr-skew-ps = <0>;
69 devbus,acc-first-ps = <124000>;
70 devbus,acc-next-ps = <248000>;
71 devbus,rd-setup-ps = <0>;
72 devbus,rd-hold-ps = <0>;
74 /* Write parameters */
75 devbus,sync-enable = <0>;
76 devbus,wr-high-ps = <60000>;
77 devbus,wr-low-ps = <60000>;
78 devbus,ale-wr-ps = <60000>;
83 compatible = "mtd-ram";
91 i2c0_gpio_pins: i2c-gpio-pins-0 {
92 marvell,pins = "mpp2", "mpp3";
93 marvell,function = "gpio";
98 clock-frequency = <100000>;
101 pinctrl-names = "default", "gpio";
102 pinctrl-0 = <&i2c0_pins>;
103 pinctrl-1 = <&i2c0_gpio_pins>;
104 scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
105 sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
108 #address-cells = <1>;
110 compatible = "nxp,pca9544";
112 i2c-mux-idle-disconnect;
114 i2c@0 { /* POE devices MUX */
115 #address-cells = <1>;
121 #address-cells = <1>;
125 adt7476_2e: hwmon@2e {
126 compatible = "adi,adt7476";
130 adt7476_2d: hwmon@2d {
131 compatible = "adi,adt7476";
137 #address-cells = <1>;
142 compatible = "dallas,ds1340";
148 #address-cells = <1>;
153 compatible = "nxp,pca9554";
167 pinctrl-names = "default";
168 pinctrl-0 = <&spi1_pins>;
172 #address-cells = <1>;
174 compatible = "jedec,spi-nor";
175 reg = <1>; /* Chip select 1 */
176 spi-max-frequency = <54000000>;
179 compatible = "fixed-partitions";
180 #address-cells = <1>;
183 reg = <0x00000000 0x00100000>;
186 partition@u-boot-env {
187 reg = <0x00100000 0x00040000>;
188 label = "u-boot-env";
191 reg = <0x00140000 0x00e80000>;
195 reg = <0x00fc0000 0x00040000>;
207 label = "pxa3xx_nand-0";
210 nand-ecc-strength = <4>;
211 nand-ecc-step-size = <512>;
213 marvell,nand-enable-arbiter;
216 compatible = "fixed-partitions";
217 #address-cells = <1>;
220 reg = <0x00000000 0x0f000000>;
224 /* Maximum mtdoops size is 8MB, so set to that. */
225 reg = <0x0f000000 0x00800000>;
229 reg = <0x0f800000 0x00800000>;