2 * Copyright 2016 Linaro Ltd
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
29 compatible = "arm,realview-pbx";
43 device_type = "memory";
44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
48 /* The voltage to the MMC card is hardwired at 3.3V */
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
57 veth: regulator-veth {
58 compatible = "regulator-fixed";
59 regulator-name = "veth";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
65 xtal24mhz: xtal24mhz@24M {
67 compatible = "fixed-clock";
68 clock-frequency = <24000000>;
71 refclk32khz: refclk32khz {
73 compatible = "fixed-clock";
74 clock-frequency = <32768>;
79 compatible = "fixed-factor-clock";
82 clocks = <&xtal24mhz>;
87 compatible = "fixed-factor-clock";
90 clocks = <&xtal24mhz>;
95 compatible = "fixed-factor-clock";
98 clocks = <&xtal24mhz>;
103 compatible = "fixed-factor-clock";
106 clocks = <&xtal24mhz>;
109 uartclk: uartclk@24M {
111 compatible = "fixed-factor-clock";
114 clocks = <&xtal24mhz>;
117 wdogclk: wdogclk@24M {
119 compatible = "fixed-factor-clock";
122 clocks = <&xtal24mhz>;
125 /* FIXME: this actually hangs off the PLL clocks */
128 compatible = "fixed-clock";
129 clock-frequency = <0>;
133 /* 2 * 32MiB NOR Flash memory */
134 compatible = "arm,versatile-flash", "cfi-flash";
135 reg = <0x40000000 0x04000000>;
138 compatible = "arm,arm-firmware-suite";
143 /* 2 * 32MiB NOR Flash memory */
144 compatible = "arm,versatile-flash", "cfi-flash";
145 reg = <0x44000000 0x04000000>;
148 compatible = "arm,arm-firmware-suite";
152 /* SMSC 9118 ethernet with PHY and EEPROM */
153 ethernet: ethernet@4e000000 {
154 compatible = "smsc,lan9118", "smsc,lan9115";
155 reg = <0x4e000000 0x10000>;
158 smsc,irq-active-high;
160 vdd33a-supply = <&veth>;
161 vddvario-supply = <&veth>;
165 compatible = "nxp,usb-isp1761";
166 reg = <0x4f000000 0x20000>;
167 dr_mode = "peripheral";
171 compatible = "ti,ths8134a", "ti,ths8134";
172 #address-cells = <1>;
176 #address-cells = <1>;
182 vga_bridge_in: endpoint {
183 remote-endpoint = <&clcd_pads>;
190 vga_bridge_out: endpoint {
191 remote-endpoint = <&vga_con_in>;
199 * This DDC I2C is connected directly to the DVI portions
200 * of the connector, so it's not really working when the
201 * monitor is connected to the VGA connector.
203 compatible = "vga-connector";
204 ddc-i2c-bus = <&i2c1>;
207 vga_con_in: endpoint {
208 remote-endpoint = <&vga_bridge_out>;
214 compatible = "arm,realview-pbx-soc", "simple-bus";
215 #address-cells = <1>;
220 syscon: syscon@10000000 {
221 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
222 reg = <0x10000000 0x1000>;
223 ranges = <0x0 0x10000000 0x1000>;
224 #address-cells = <1>;
228 compatible = "register-bit-led";
232 label = "versatile:0";
233 linux,default-trigger = "heartbeat";
234 default-state = "on";
237 compatible = "register-bit-led";
241 label = "versatile:1";
242 linux,default-trigger = "mmc0";
243 default-state = "off";
246 compatible = "register-bit-led";
250 label = "versatile:2";
251 linux,default-trigger = "cpu0";
252 default-state = "off";
255 compatible = "register-bit-led";
259 label = "versatile:3";
260 default-state = "off";
263 compatible = "register-bit-led";
267 label = "versatile:4";
268 default-state = "off";
271 compatible = "register-bit-led";
275 label = "versatile:5";
276 default-state = "off";
279 compatible = "register-bit-led";
283 label = "versatile:6";
284 default-state = "off";
287 compatible = "register-bit-led";
291 label = "versatile:7";
292 default-state = "off";
294 oscclk0: clock-controller@c {
295 compatible = "arm,syscon-icst307";
298 lock-offset = <0x20>;
300 clocks = <&xtal24mhz>;
302 oscclk1: clock-controller@10 {
303 compatible = "arm,syscon-icst307";
306 lock-offset = <0x20>;
308 clocks = <&xtal24mhz>;
310 oscclk2: clock-controller@14 {
311 compatible = "arm,syscon-icst307";
314 lock-offset = <0x20>;
316 clocks = <&xtal24mhz>;
318 oscclk3: clock-controller@18 {
319 compatible = "arm,syscon-icst307";
322 lock-offset = <0x20>;
324 clocks = <&xtal24mhz>;
326 oscclk4: clock-controller@1c {
327 compatible = "arm,syscon-icst307";
330 lock-offset = <0x20>;
332 clocks = <&xtal24mhz>;
336 sp810_syscon0: sysctl@10001000 {
337 compatible = "arm,sp810", "arm,primecell";
338 reg = <0x10001000 0x1000>;
339 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
340 clock-names = "refclk", "timclk", "apb_pclk";
342 clock-output-names = "timerclk0",
346 assigned-clocks = <&sp810_syscon0 0>,
350 assigned-clock-parents = <&timclk>,
357 #address-cells = <1>;
359 compatible = "arm,versatile-i2c";
360 reg = <0x10002000 0x1000>;
363 compatible = "dallas,ds1338";
368 serial0: serial@10009000 {
369 compatible = "arm,pl011", "arm,primecell";
370 reg = <0x10009000 0x1000>;
371 clocks = <&uartclk>, <&pclk>;
372 clock-names = "uartclk", "apb_pclk";
375 serial1: serial@1000a000 {
376 compatible = "arm,pl011", "arm,primecell";
377 reg = <0x1000a000 0x1000>;
378 clocks = <&uartclk>, <&pclk>;
379 clock-names = "uartclk", "apb_pclk";
382 serial2: serial@1000b000 {
383 compatible = "arm,pl011", "arm,primecell";
384 reg = <0x1000b000 0x1000>;
385 clocks = <&uartclk>, <&pclk>;
386 clock-names = "uartclk", "apb_pclk";
390 compatible = "arm,pl022", "arm,primecell";
391 reg = <0x1000d000 0x1000>;
392 clocks = <&sspclk>, <&pclk>;
393 clock-names = "SSPCLK", "apb_pclk";
396 wdog0: watchdog@1000f000 {
397 compatible = "arm,sp805", "arm,primecell";
398 reg = <0x1000f000 0x1000>;
399 clocks = <&wdogclk>, <&pclk>;
400 clock-names = "wdog_clk", "apb_pclk";
404 wdog1: watchdog@10010000 {
405 compatible = "arm,sp805", "arm,primecell";
406 reg = <0x10010000 0x1000>;
407 clocks = <&wdogclk>, <&pclk>;
408 clock-names = "wdog_clk", "apb_pclk";
412 timer01: timer@10011000 {
413 compatible = "arm,sp804", "arm,primecell";
414 reg = <0x10011000 0x1000>;
415 clocks = <&sp810_syscon0 0>,
418 clock-names = "timerclk0",
423 timer23: timer@10012000 {
424 compatible = "arm,sp804", "arm,primecell";
425 reg = <0x10012000 0x1000>;
426 clocks = <&sp810_syscon0 2>,
429 clock-names = "timerclk2",
434 gpio0: gpio@10013000 {
435 compatible = "arm,pl061", "arm,primecell";
436 reg = <0x10013000 0x1000>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
442 clock-names = "apb_pclk";
445 gpio1: gpio@10014000 {
446 compatible = "arm,pl061", "arm,primecell";
447 reg = <0x10014000 0x1000>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
453 clock-names = "apb_pclk";
456 gpio2: gpio@10015000 {
457 compatible = "arm,pl061", "arm,primecell";
458 reg = <0x10015000 0x1000>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
464 clock-names = "apb_pclk";
468 #address-cells = <1>;
470 compatible = "arm,versatile-i2c";
471 reg = <0x10016000 0x1000>;
475 compatible = "arm,pl031", "arm,primecell";
476 reg = <0x10017000 0x1000>;
478 clock-names = "apb_pclk";
481 timer45: timer@10018000 {
482 compatible = "arm,sp804", "arm,primecell";
483 reg = <0x10018000 0x1000>;
484 clocks = <&timclk>, <&timclk>, <&pclk>;
485 clock-names = "timerclk4", "timerclk5", "apb_pclk";
488 timer67: timer@10019000 {
489 compatible = "arm,sp804", "arm,primecell";
490 reg = <0x10019000 0x1000>;
491 clocks = <&timclk>, <&timclk>, <&pclk>;
492 clock-names = "timerclk6", "timerclk7", "apb_pclk";
495 sp810_syscon1: sysctl@1001a000 {
496 compatible = "arm,sp810", "arm,primecell";
497 reg = <0x1001a000 0x1000>;
498 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
499 clock-names = "refclk", "timclk", "apb_pclk";
501 clock-output-names = "timerclk4",
505 assigned-clocks = <&sp810_syscon1 0>,
509 assigned-clock-parents = <&timclk>,
517 /* These peripherals are inside the FPGA */
519 #address-cells = <1>;
521 compatible = "simple-bus";
524 aaci: aaci@10004000 {
525 compatible = "arm,pl041", "arm,primecell";
526 reg = <0x10004000 0x1000>;
528 clock-names = "apb_pclk";
531 mmc: mmcsd@10005000 {
532 compatible = "arm,pl18x", "arm,primecell";
533 reg = <0x10005000 0x1000>;
535 /* Due to frequent FIFO overruns, use just 500 kHz */
536 max-frequency = <500000>;
540 clocks = <&mclk>, <&pclk>;
541 clock-names = "mclk", "apb_pclk";
542 vmmc-supply = <&vmmc>;
543 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
544 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
548 compatible = "arm,pl050", "arm,primecell";
549 reg = <0x10006000 0x1000>;
550 clocks = <&kmiclk>, <&pclk>;
551 clock-names = "KMIREFCLK", "apb_pclk";
555 compatible = "arm,pl050", "arm,primecell";
556 reg = <0x10007000 0x1000>;
557 clocks = <&kmiclk>, <&pclk>;
558 clock-names = "KMIREFCLK", "apb_pclk";
561 serial3: serial@1000c000 {
562 compatible = "arm,pl011", "arm,primecell";
563 reg = <0x1000c000 0x1000>;
564 clocks = <&uartclk>, <&pclk>;
565 clock-names = "uartclk", "apb_pclk";
569 /* These peripherals are inside the NEC ISSP */
571 #address-cells = <1>;
573 compatible = "simple-bus";
576 clcd: clcd@10020000 {
577 compatible = "arm,pl111", "arm,primecell";
578 reg = <0x10020000 0x1000>;
579 interrupt-names = "combined";
580 clocks = <&oscclk4>, <&pclk>;
581 clock-names = "clcdclk", "apb_pclk";
582 /* 1024x768 16bpp @65MHz works fine */
583 max-memory-bandwidth = <95000000>;
586 clcd_pads: endpoint {
587 remote-endpoint = <&vga_bridge_in>;
588 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;