arch/arm/boot/dts/arm-realview-pb1176.dts

   1 /*
   2  * Copyright 2014 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25 #include "skeleton.dtsi"
  26
  27 / {
  28         model = "ARM RealView PB1176";
  29         compatible = "arm,realview-pb1176";
  30
  31         chosen { };
  32
  33         aliases {
  34                 serial0 = &pb1176_serial0;
  35                 serial1 = &pb1176_serial1;
  36                 serial2 = &pb1176_serial2;
  37                 serial3 = &pb1176_serial3;
  38         };
  39
  40         memory {
  41                 /* 128 MiB memory @ 0x0 */
  42                 reg = <0x00000000 0x08000000>;
  43         };
  44
  45         xtal24mhz: xtal24mhz@24M {
  46                 #clock-cells = <0>;
  47                 compatible = "fixed-clock";
  48                 clock-frequency = <24000000>;
  49         };
  50
  51         timclk: timclk@1M {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-factor-clock";
  54                 clock-div = <24>;
  55                 clock-mult = <1>;
  56                 clocks = <&xtal24mhz>;
  57         };
  58
  59         sspclk: sspclk@24M {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-factor-clock";
  62                 clock-div = <1>;
  63                 clock-mult = <1>;
  64                 clocks = <&xtal24mhz>;
  65         };
  66
  67         uartclk: uartclk@24M {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-factor-clock";
  70                 clock-div = <1>;
  71                 clock-mult = <1>;
  72                 clocks = <&xtal24mhz>;
  73         };
  74
  75         /* FIXME: this actually hangs off the PLL clocks */
  76         pclk: pclk@0 {
  77                 #clock-cells = <0>;
  78                 compatible = "fixed-clock";
  79                 clock-frequency = <0>;
  80         };
  81
  82         soc {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "arm,realview-pb1176-soc", "simple-bus";
  86                 regmap = <&syscon>;
  87                 ranges;
  88
  89                 syscon: syscon@10000000 {
  90                         compatible = "arm,realview-pb1176-syscon", "syscon";
  91                         reg = <0x10000000 0x1000>;
  92
  93                         led@08.0 {
  94                                 compatible = "register-bit-led";
  95                                 offset = <0x08>;
  96                                 mask = <0x01>;
  97                                 label = "versatile:0";
  98                                 linux,default-trigger = "heartbeat";
  99                                 default-state = "on";
 100                         };
 101                         led@08.1 {
 102                                 compatible = "register-bit-led";
 103                                 offset = <0x08>;
 104                                 mask = <0x02>;
 105                                 label = "versatile:1";
 106                                 linux,default-trigger = "mmc0";
 107                                 default-state = "off";
 108                         };
 109                         led@08.2 {
 110                                 compatible = "register-bit-led";
 111                                 offset = <0x08>;
 112                                 mask = <0x04>;
 113                                 label = "versatile:2";
 114                                 linux,default-trigger = "cpu0";
 115                                 default-state = "off";
 116                         };
 117                         led@08.3 {
 118                                 compatible = "register-bit-led";
 119                                 offset = <0x08>;
 120                                 mask = <0x08>;
 121                                 label = "versatile:3";
 122                                 default-state = "off";
 123                         };
 124                         led@08.4 {
 125                                 compatible = "register-bit-led";
 126                                 offset = <0x08>;
 127                                 mask = <0x10>;
 128                                 label = "versatile:4";
 129                                 default-state = "off";
 130                         };
 131                         led@08.5 {
 132                                 compatible = "register-bit-led";
 133                                 offset = <0x08>;
 134                                 mask = <0x20>;
 135                                 label = "versatile:5";
 136                                 default-state = "off";
 137                         };
 138                         led@08.6 {
 139                                 compatible = "register-bit-led";
 140                                 offset = <0x08>;
 141                                 mask = <0x40>;
 142                                 label = "versatile:6";
 143                                 default-state = "off";
 144                         };
 145                         led@08.7 {
 146                                 compatible = "register-bit-led";
 147                                 offset = <0x08>;
 148                                 mask = <0x80>;
 149                                 label = "versatile:7";
 150                                 default-state = "off";
 151                         };
 152                 };
 153
 154                 /* Primary DevChip GIC synthesized with the CPU */
 155                 intc_dc1176: interrupt-controller@10120000 {
 156                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 157                         #interrupt-cells = <3>;
 158                         #address-cells = <1>;
 159                         interrupt-controller;
 160                         reg = <0x10121000 0x1000>,
 161                               <0x10120000 0x100>;
 162                 };
 163
 164                 L2: l2-cache {
 165                         compatible = "arm,l220-cache";
 166                         reg = <0x10110000 0x1000>;
 167                         interrupt-parent = <&intc_dc1176>;
 168                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 169                         cache-unified;
 170                         cache-level = <2>;
 171                         /*
 172                          * Override default cache size, sets and
 173                          * associativity as these may be erroneously set
 174                          * up by boot loader(s).
 175                          */
 176                         arm,override-auxreg;
 177                         cache-size = <131072>; // 128kB
 178                         cache-sets = <512>;
 179                         cache-line-size = <32>;
 180                 };
 181
 182                 pmu {
 183                         compatible = "arm,arm1176-pmu";
 184                         interrupt-parent = <&intc_dc1176>;
 185                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 186                 };
 187
 188                 timer01: timer@10104000 {
 189                         compatible = "arm,sp804", "arm,primecell";
 190                         reg = <0x10104000 0x1000>;
 191                         interrupt-parent = <&intc_dc1176>;
 192                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&timclk>, <&timclk>, <&pclk>;
 194                         clock-names = "timer1", "timer2", "apb_pclk";
 195                 };
 196
 197                 timer23: timer@10105000 {
 198                         compatible = "arm,sp804", "arm,primecell";
 199                         reg = <0x10105000 0x1000>;
 200                         interrupt-parent = <&intc_dc1176>;
 201                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 202                         arm,sp804-has-irq = <1>;
 203                         clocks = <&timclk>, <&timclk>, <&pclk>;
 204                         clock-names = "timer1", "timer2", "apb_pclk";
 205                 };
 206
 207                 pb1176_rtc: rtc@10108000 {
 208                         compatible = "arm,pl031", "arm,primecell";
 209                         reg = <0x10108000 0x1000>;
 210                         interrupt-parent = <&intc_dc1176>;
 211                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&pclk>;
 213                         clock-names = "apb_pclk";
 214                 };
 215
 216                 pb1176_gpio0: gpio@1010a000 {
 217                         compatible = "arm,pl061", "arm,primecell";
 218                         reg = <0x1010a000 0x1000>;
 219                         gpio-controller;
 220                         interrupt-parent = <&intc_dc1176>;
 221                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 222                         #gpio-cells = <2>;
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                         clocks = <&pclk>;
 226                         clock-names = "apb_pclk";
 227                 };
 228
 229                 pb1176_ssp: ssp@1010b000 {
 230                         compatible = "arm,pl022", "arm,primecell";
 231                         reg = <0x1010b000 0x1000>;
 232                         interrupt-parent = <&intc_dc1176>;
 233                         interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
 234                         clocks = <&sspclk>, <&pclk>;
 235                         clock-names = "SSPCLK", "apb_pclk";
 236                 };
 237
 238                 pb1176_serial0: serial@1010c000 {
 239                         compatible = "arm,pl011", "arm,primecell";
 240                         reg = <0x1010c000 0x1000>;
 241                         interrupt-parent = <&intc_dc1176>;
 242                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&uartclk>, <&pclk>;
 244                         clock-names = "uartclk", "apb_pclk";
 245                 };
 246
 247                 pb1176_serial1: serial@1010d000 {
 248                         compatible = "arm,pl011", "arm,primecell";
 249                         reg = <0x1010d000 0x1000>;
 250                         interrupt-parent = <&intc_dc1176>;
 251                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&uartclk>, <&pclk>;
 253                         clock-names = "uartclk", "apb_pclk";
 254                 };
 255
 256                 pb1176_serial2: serial@1010e000 {
 257                         compatible = "arm,pl011", "arm,primecell";
 258                         reg = <0x1010e000 0x1000>;
 259                         interrupt-parent = <&intc_dc1176>;
 260                         interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&uartclk>, <&pclk>;
 262                         clock-names = "uartclk", "apb_pclk";
 263                 };
 264
 265                 pb1176_serial3: serial@1010f000 {
 266                         compatible = "arm,pl011", "arm,primecell";
 267                         reg = <0x1010f000 0x1000>;
 268                         interrupt-parent = <&intc_dc1176>;
 269                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&uartclk>, <&pclk>;
 271                         clock-names = "uartclk", "apb_pclk";
 272                 };
 273         };
 274
 275         /* These peripherals are inside the FPGA rather than the DevChip */
 276         fpga {
 277                 #address-cells = <1>;
 278                 #size-cells = <1>;
 279                 compatible = "simple-bus";
 280                 ranges;
 281
 282                 fpga_charlcd: charlcd@10008000 {
 283                         compatible = "arm,versatile-lcd";
 284                         reg = <0x10008000 0x1000>;
 285                         interrupt-parent = <&intc_fpga1176>;
 286                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&pclk>;
 288                         clock-names = "apb_pclk";
 289                 };
 290
 291                 /* This GIC on the board is cascaded off the DevChip GIC */
 292                 intc_fpga1176: interrupt-controller@10040000 {
 293                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
 294                         #interrupt-cells = <3>;
 295                         #address-cells = <1>;
 296                         interrupt-controller;
 297                         reg = <0x10041000 0x1000>,
 298                               <0x10040000 0x100>;
 299                         interrupt-parent = <&intc_dc1176>;
 300                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 301                 };
 302
 303                 fpga_gpio0: gpio@10014000 {
 304                         compatible = "arm,pl061", "arm,primecell";
 305                         reg = <0x10014000 0x1000>;
 306                         gpio-controller;
 307                         interrupt-parent = <&intc_fpga1176>;
 308                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 309                         #gpio-cells = <2>;
 310                         interrupt-controller;
 311                         #interrupt-cells = <2>;
 312                         clocks = <&pclk>;
 313                         clock-names = "apb_pclk";
 314                 };
 315
 316                 fpga_gpio1: gpio@10015000 {
 317                         compatible = "arm,pl061", "arm,primecell";
 318                         reg = <0x10015000 0x1000>;
 319                         gpio-controller;
 320                         interrupt-parent = <&intc_fpga1176>;
 321                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 322                         #gpio-cells = <2>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                         clocks = <&pclk>;
 326                         clock-names = "apb_pclk";
 327                 };
 328
 329                 fpga_rtc: rtc@10017000 {
 330                         compatible = "arm,pl031", "arm,primecell";
 331                         reg = <0x10017000 0x1000>;
 332                         interrupt-parent = <&intc_fpga1176>;
 333                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&pclk>;
 335                         clock-names = "apb_pclk";
 336                 };
 337         };
 338 };