arch/arm/boot/dts/am43xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for AM43xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &scm_clocks {
   8         sys_clkin_ck: clock-sys-clkin-31@40 {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,mux-clock";
  11                 clock-output-names = "sys_clkin_ck";
  12                 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
  13                 ti,bit-shift = <31>;
  14                 reg = <0x0040>;
  15         };
  16
  17         crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,mux-clock";
  20                 clock-output-names = "crystal_freq_sel_ck";
  21                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  22                 ti,bit-shift = <29>;
  23                 reg = <0x0040>;
  24         };
  25
  26         sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
  27                 #clock-cells = <0>;
  28                 compatible = "ti,mux-clock";
  29                 clock-output-names = "sysboot_freq_sel_ck";
  30                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  31                 ti,bit-shift = <22>;
  32                 reg = <0x0040>;
  33         };
  34
  35         adc_tsc_fck: clock-adc-tsc-fck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-factor-clock";
  38                 clock-output-names = "adc_tsc_fck";
  39                 clocks = <&sys_clkin_ck>;
  40                 clock-mult = <1>;
  41                 clock-div = <1>;
  42         };
  43
  44         dcan0_fck: clock-dcan0-fck {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-factor-clock";
  47                 clock-output-names = "dcan0_fck";
  48                 clocks = <&sys_clkin_ck>;
  49                 clock-mult = <1>;
  50                 clock-div = <1>;
  51         };
  52
  53         dcan1_fck: clock-dcan1-fck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-factor-clock";
  56                 clock-output-names = "dcan1_fck";
  57                 clocks = <&sys_clkin_ck>;
  58                 clock-mult = <1>;
  59                 clock-div = <1>;
  60         };
  61
  62         mcasp0_fck: clock-mcasp0-fck {
  63                 #clock-cells = <0>;
  64                 compatible = "fixed-factor-clock";
  65                 clock-output-names = "mcasp0_fck";
  66                 clocks = <&sys_clkin_ck>;
  67                 clock-mult = <1>;
  68                 clock-div = <1>;
  69         };
  70
  71         mcasp1_fck: clock-mcasp1-fck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-factor-clock";
  74                 clock-output-names = "mcasp1_fck";
  75                 clocks = <&sys_clkin_ck>;
  76                 clock-mult = <1>;
  77                 clock-div = <1>;
  78         };
  79
  80         smartreflex0_fck: clock-smartreflex0-fck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-factor-clock";
  83                 clock-output-names = "smartreflex0_fck";
  84                 clocks = <&sys_clkin_ck>;
  85                 clock-mult = <1>;
  86                 clock-div = <1>;
  87         };
  88
  89         smartreflex1_fck: clock-smartreflex1-fck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-factor-clock";
  92                 clock-output-names = "smartreflex1_fck";
  93                 clocks = <&sys_clkin_ck>;
  94                 clock-mult = <1>;
  95                 clock-div = <1>;
  96         };
  97
  98         sha0_fck: clock-sha0-fck {
  99                 #clock-cells = <0>;
 100                 compatible = "fixed-factor-clock";
 101                 clock-output-names = "sha0_fck";
 102                 clocks = <&sys_clkin_ck>;
 103                 clock-mult = <1>;
 104                 clock-div = <1>;
 105         };
 106
 107         aes0_fck: clock-aes0-fck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-factor-clock";
 110                 clock-output-names = "aes0_fck";
 111                 clocks = <&sys_clkin_ck>;
 112                 clock-mult = <1>;
 113                 clock-div = <1>;
 114         };
 115
 116         rng_fck: clock-rng-fck {
 117                 #clock-cells = <0>;
 118                 compatible = "fixed-factor-clock";
 119                 clock-output-names = "rng_fck";
 120                 clocks = <&sys_clkin_ck>;
 121                 clock-mult = <1>;
 122                 clock-div = <1>;
 123         };
 124
 125         ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 {
 126                 #clock-cells = <0>;
 127                 compatible = "ti,gate-clock";
 128                 clock-output-names = "ehrpwm0_tbclk";
 129                 clocks = <&l4ls_gclk>;
 130                 ti,bit-shift = <0>;
 131                 reg = <0x0664>;
 132         };
 133
 134         ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 {
 135                 #clock-cells = <0>;
 136                 compatible = "ti,gate-clock";
 137                 clock-output-names = "ehrpwm1_tbclk";
 138                 clocks = <&l4ls_gclk>;
 139                 ti,bit-shift = <1>;
 140                 reg = <0x0664>;
 141         };
 142
 143         ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 {
 144                 #clock-cells = <0>;
 145                 compatible = "ti,gate-clock";
 146                 clock-output-names = "ehrpwm2_tbclk";
 147                 clocks = <&l4ls_gclk>;
 148                 ti,bit-shift = <2>;
 149                 reg = <0x0664>;
 150         };
 151
 152         ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 {
 153                 #clock-cells = <0>;
 154                 compatible = "ti,gate-clock";
 155                 clock-output-names = "ehrpwm3_tbclk";
 156                 clocks = <&l4ls_gclk>;
 157                 ti,bit-shift = <4>;
 158                 reg = <0x0664>;
 159         };
 160
 161         ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 {
 162                 #clock-cells = <0>;
 163                 compatible = "ti,gate-clock";
 164                 clock-output-names = "ehrpwm4_tbclk";
 165                 clocks = <&l4ls_gclk>;
 166                 ti,bit-shift = <5>;
 167                 reg = <0x0664>;
 168         };
 169
 170         ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 {
 171                 #clock-cells = <0>;
 172                 compatible = "ti,gate-clock";
 173                 clock-output-names = "ehrpwm5_tbclk";
 174                 clocks = <&l4ls_gclk>;
 175                 ti,bit-shift = <6>;
 176                 reg = <0x0664>;
 177         };
 178 };
 179 &prcm_clocks {
 180         clk_32768_ck: clock-clk-32768 {
 181                 #clock-cells = <0>;
 182                 compatible = "fixed-clock";
 183                 clock-output-names = "clk_32768_ck";
 184                 clock-frequency = <32768>;
 185         };
 186
 187         clk_rc32k_ck: clock-clk-rc32k {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-output-names = "clk_rc32k_ck";
 191                 clock-frequency = <32768>;
 192         };
 193
 194         virt_19200000_ck: clock-virt-19200000 {
 195                 #clock-cells = <0>;
 196                 compatible = "fixed-clock";
 197                 clock-output-names = "virt_19200000_ck";
 198                 clock-frequency = <19200000>;
 199         };
 200
 201         virt_24000000_ck: clock-virt-24000000 {
 202                 #clock-cells = <0>;
 203                 compatible = "fixed-clock";
 204                 clock-output-names = "virt_24000000_ck";
 205                 clock-frequency = <24000000>;
 206         };
 207
 208         virt_25000000_ck: clock-virt-25000000 {
 209                 #clock-cells = <0>;
 210                 compatible = "fixed-clock";
 211                 clock-output-names = "virt_25000000_ck";
 212                 clock-frequency = <25000000>;
 213         };
 214
 215         virt_26000000_ck: clock-virt-26000000 {
 216                 #clock-cells = <0>;
 217                 compatible = "fixed-clock";
 218                 clock-output-names = "virt_26000000_ck";
 219                 clock-frequency = <26000000>;
 220         };
 221
 222         tclkin_ck: clock-tclkin {
 223                 #clock-cells = <0>;
 224                 compatible = "fixed-clock";
 225                 clock-output-names = "tclkin_ck";
 226                 clock-frequency = <26000000>;
 227         };
 228
 229         dpll_core_ck: clock@2d20 {
 230                 #clock-cells = <0>;
 231                 compatible = "ti,am3-dpll-core-clock";
 232                 clock-output-names = "dpll_core_ck";
 233                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 234                 reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
 235         };
 236
 237         dpll_core_x2_ck: clock-dpll-core-x2 {
 238                 #clock-cells = <0>;
 239                 compatible = "ti,am3-dpll-x2-clock";
 240                 clock-output-names = "dpll_core_x2_ck";
 241                 clocks = <&dpll_core_ck>;
 242         };
 243
 244         dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
 245                 #clock-cells = <0>;
 246                 compatible = "ti,divider-clock";
 247                 clock-output-names = "dpll_core_m4_ck";
 248                 clocks = <&dpll_core_x2_ck>;
 249                 ti,max-div = <31>;
 250                 ti,autoidle-shift = <8>;
 251                 reg = <0x2d38>;
 252                 ti,index-starts-at-one;
 253                 ti,invert-autoidle-bit;
 254         };
 255
 256         dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
 257                 #clock-cells = <0>;
 258                 compatible = "ti,divider-clock";
 259                 clock-output-names = "dpll_core_m5_ck";
 260                 clocks = <&dpll_core_x2_ck>;
 261                 ti,max-div = <31>;
 262                 ti,autoidle-shift = <8>;
 263                 reg = <0x2d3c>;
 264                 ti,index-starts-at-one;
 265                 ti,invert-autoidle-bit;
 266         };
 267
 268         dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
 269                 #clock-cells = <0>;
 270                 compatible = "ti,divider-clock";
 271                 clock-output-names = "dpll_core_m6_ck";
 272                 clocks = <&dpll_core_x2_ck>;
 273                 ti,max-div = <31>;
 274                 ti,autoidle-shift = <8>;
 275                 reg = <0x2d40>;
 276                 ti,index-starts-at-one;
 277                 ti,invert-autoidle-bit;
 278         };
 279
 280         dpll_mpu_ck: clock@2d60 {
 281                 #clock-cells = <0>;
 282                 compatible = "ti,am3-dpll-clock";
 283                 clock-output-names = "dpll_mpu_ck";
 284                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 285                 reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
 286         };
 287
 288         dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
 289                 #clock-cells = <0>;
 290                 compatible = "ti,divider-clock";
 291                 clock-output-names = "dpll_mpu_m2_ck";
 292                 clocks = <&dpll_mpu_ck>;
 293                 ti,max-div = <31>;
 294                 ti,autoidle-shift = <8>;
 295                 reg = <0x2d70>;
 296                 ti,index-starts-at-one;
 297                 ti,invert-autoidle-bit;
 298         };
 299
 300         mpu_periphclk: clock-mpu-periphclk {
 301                 #clock-cells = <0>;
 302                 compatible = "fixed-factor-clock";
 303                 clock-output-names = "mpu_periphclk";
 304                 clocks = <&dpll_mpu_m2_ck>;
 305                 clock-mult = <1>;
 306                 clock-div = <2>;
 307         };
 308
 309         dpll_ddr_ck: clock@2da0 {
 310                 #clock-cells = <0>;
 311                 compatible = "ti,am3-dpll-clock";
 312                 clock-output-names = "dpll_ddr_ck";
 313                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 314                 reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
 315         };
 316
 317         dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
 318                 #clock-cells = <0>;
 319                 compatible = "ti,divider-clock";
 320                 clock-output-names = "dpll_ddr_m2_ck";
 321                 clocks = <&dpll_ddr_ck>;
 322                 ti,max-div = <31>;
 323                 ti,autoidle-shift = <8>;
 324                 reg = <0x2db0>;
 325                 ti,index-starts-at-one;
 326                 ti,invert-autoidle-bit;
 327         };
 328
 329         dpll_disp_ck: clock@2e20 {
 330                 #clock-cells = <0>;
 331                 compatible = "ti,am3-dpll-clock";
 332                 clock-output-names = "dpll_disp_ck";
 333                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 334                 reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
 335         };
 336
 337         dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 {
 338                 #clock-cells = <0>;
 339                 compatible = "ti,divider-clock";
 340                 clock-output-names = "dpll_disp_m2_ck";
 341                 clocks = <&dpll_disp_ck>;
 342                 ti,max-div = <31>;
 343                 ti,autoidle-shift = <8>;
 344                 reg = <0x2e30>;
 345                 ti,index-starts-at-one;
 346                 ti,invert-autoidle-bit;
 347                 ti,set-rate-parent;
 348         };
 349
 350         dpll_per_ck: clock@2de0 {
 351                 #clock-cells = <0>;
 352                 compatible = "ti,am3-dpll-j-type-clock";
 353                 clock-output-names = "dpll_per_ck";
 354                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 355                 reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
 356         };
 357
 358         dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 {
 359                 #clock-cells = <0>;
 360                 compatible = "ti,divider-clock";
 361                 clock-output-names = "dpll_per_m2_ck";
 362                 clocks = <&dpll_per_ck>;
 363                 ti,max-div = <127>;
 364                 ti,autoidle-shift = <8>;
 365                 reg = <0x2df0>;
 366                 ti,index-starts-at-one;
 367                 ti,invert-autoidle-bit;
 368         };
 369
 370         dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
 371                 #clock-cells = <0>;
 372                 compatible = "fixed-factor-clock";
 373                 clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
 374                 clocks = <&dpll_per_m2_ck>;
 375                 clock-mult = <1>;
 376                 clock-div = <4>;
 377         };
 378
 379         dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
 380                 #clock-cells = <0>;
 381                 compatible = "fixed-factor-clock";
 382                 clock-output-names = "dpll_per_m2_div4_ck";
 383                 clocks = <&dpll_per_m2_ck>;
 384                 clock-mult = <1>;
 385                 clock-div = <4>;
 386         };
 387
 388         clk_24mhz: clock-clk-24mhz {
 389                 #clock-cells = <0>;
 390                 compatible = "fixed-factor-clock";
 391                 clock-output-names = "clk_24mhz";
 392                 clocks = <&dpll_per_m2_ck>;
 393                 clock-mult = <1>;
 394                 clock-div = <8>;
 395         };
 396
 397         clkdiv32k_ck: clock-clkdiv32k {
 398                 #clock-cells = <0>;
 399                 compatible = "fixed-factor-clock";
 400                 clock-output-names = "clkdiv32k_ck";
 401                 clocks = <&clk_24mhz>;
 402                 clock-mult = <1>;
 403                 clock-div = <732>;
 404         };
 405
 406         clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 {
 407                 #clock-cells = <0>;
 408                 compatible = "ti,gate-clock";
 409                 clock-output-names = "clkdiv32k_ick";
 410                 clocks = <&clkdiv32k_ck>;
 411                 ti,bit-shift = <8>;
 412                 reg = <0x2a38>;
 413         };
 414
 415         sysclk_div: clock-sysclk-div {
 416                 #clock-cells = <0>;
 417                 compatible = "fixed-factor-clock";
 418                 clock-output-names = "sysclk_div";
 419                 clocks = <&dpll_core_m4_ck>;
 420                 clock-mult = <1>;
 421                 clock-div = <1>;
 422         };
 423
 424         pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
 425                 #clock-cells = <0>;
 426                 compatible = "ti,mux-clock";
 427                 clock-output-names = "pruss_ocp_gclk";
 428                 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
 429                 reg = <0x4248>;
 430         };
 431
 432         clk_32k_tpm_ck: clock-clk-32k-tpm {
 433                 #clock-cells = <0>;
 434                 compatible = "fixed-clock";
 435                 clock-output-names = "clk_32k_tpm_ck";
 436                 clock-frequency = <32768>;
 437         };
 438
 439         timer1_fck: clock-timer1-fck@4200 {
 440                 #clock-cells = <0>;
 441                 compatible = "ti,mux-clock";
 442                 clock-output-names = "timer1_fck";
 443                 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 444                 reg = <0x4200>;
 445         };
 446
 447         timer2_fck: clock-timer2-fck@4204 {
 448                 #clock-cells = <0>;
 449                 compatible = "ti,mux-clock";
 450                 clock-output-names = "timer2_fck";
 451                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 452                 reg = <0x4204>;
 453         };
 454
 455         timer3_fck: clock-timer3-fck@4208 {
 456                 #clock-cells = <0>;
 457                 compatible = "ti,mux-clock";
 458                 clock-output-names = "timer3_fck";
 459                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 460                 reg = <0x4208>;
 461         };
 462
 463         timer4_fck: clock-timer4-fck@420c {
 464                 #clock-cells = <0>;
 465                 compatible = "ti,mux-clock";
 466                 clock-output-names = "timer4_fck";
 467                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 468                 reg = <0x420c>;
 469         };
 470
 471         timer5_fck: clock-timer5-fck@4210 {
 472                 #clock-cells = <0>;
 473                 compatible = "ti,mux-clock";
 474                 clock-output-names = "timer5_fck";
 475                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 476                 reg = <0x4210>;
 477         };
 478
 479         timer6_fck: clock-timer6-fck@4214 {
 480                 #clock-cells = <0>;
 481                 compatible = "ti,mux-clock";
 482                 clock-output-names = "timer6_fck";
 483                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 484                 reg = <0x4214>;
 485         };
 486
 487         timer7_fck: clock-timer7-fck@4218 {
 488                 #clock-cells = <0>;
 489                 compatible = "ti,mux-clock";
 490                 clock-output-names = "timer7_fck";
 491                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 492                 reg = <0x4218>;
 493         };
 494
 495         wdt1_fck: clock-wdt1-fck@422c {
 496                 #clock-cells = <0>;
 497                 compatible = "ti,mux-clock";
 498                 clock-output-names = "wdt1_fck";
 499                 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
 500                 reg = <0x422c>;
 501         };
 502
 503         adc_mag_fck: adc_mag_fck@424c {
 504                 #clock-cells = <0>;
 505                 compatible = "ti,mux-clock";
 506                 clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>;
 507                 reg = <0x424c>;
 508         };
 509
 510         l3_gclk: clock-l3-gclk {
 511                 #clock-cells = <0>;
 512                 compatible = "fixed-factor-clock";
 513                 clock-output-names = "l3_gclk";
 514                 clocks = <&dpll_core_m4_ck>;
 515                 clock-mult = <1>;
 516                 clock-div = <1>;
 517         };
 518
 519         dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
 520                 #clock-cells = <0>;
 521                 compatible = "fixed-factor-clock";
 522                 clock-output-names = "dpll_core_m4_div2_ck";
 523                 clocks = <&sysclk_div>;
 524                 clock-mult = <1>;
 525                 clock-div = <2>;
 526         };
 527
 528         l4hs_gclk: clock-l4hs-gclk {
 529                 #clock-cells = <0>;
 530                 compatible = "fixed-factor-clock";
 531                 clock-output-names = "l4hs_gclk";
 532                 clocks = <&dpll_core_m4_ck>;
 533                 clock-mult = <1>;
 534                 clock-div = <1>;
 535         };
 536
 537         l3s_gclk: clock-l3s-gclk {
 538                 #clock-cells = <0>;
 539                 compatible = "fixed-factor-clock";
 540                 clock-output-names = "l3s_gclk";
 541                 clocks = <&dpll_core_m4_div2_ck>;
 542                 clock-mult = <1>;
 543                 clock-div = <1>;
 544         };
 545
 546         l4ls_gclk: clock-l4ls-gclk {
 547                 #clock-cells = <0>;
 548                 compatible = "fixed-factor-clock";
 549                 clock-output-names = "l4ls_gclk";
 550                 clocks = <&dpll_core_m4_div2_ck>;
 551                 clock-mult = <1>;
 552                 clock-div = <1>;
 553         };
 554
 555         cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
 556                 #clock-cells = <0>;
 557                 compatible = "fixed-factor-clock";
 558                 clock-output-names = "cpsw_125mhz_gclk";
 559                 clocks = <&dpll_core_m5_ck>;
 560                 clock-mult = <1>;
 561                 clock-div = <2>;
 562         };
 563
 564         cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 {
 565                 #clock-cells = <0>;
 566                 compatible = "ti,mux-clock";
 567                 clock-output-names = "cpsw_cpts_rft_clk";
 568                 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
 569                 reg = <0x4238>;
 570         };
 571
 572         dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
 573                 #clock-cells = <0>;
 574                 compatible = "ti,divider-clock";
 575                 clock-output-names = "dpll_clksel_mac_clk";
 576                 clocks = <&dpll_core_m5_ck>;
 577                 reg = <0x4234>;
 578                 ti,bit-shift = <2>;
 579                 ti,dividers = <2>, <5>;
 580         };
 581
 582         clk_32k_mosc_ck: clock-clk-32k-mosc {
 583                 #clock-cells = <0>;
 584                 compatible = "fixed-clock";
 585                 clock-output-names = "clk_32k_mosc_ck";
 586                 clock-frequency = <32768>;
 587         };
 588
 589         gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 {
 590                 #clock-cells = <0>;
 591                 compatible = "ti,mux-clock";
 592                 clock-output-names = "gpio0_dbclk_mux_ck";
 593                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
 594                 reg = <0x4240>;
 595         };
 596
 597         mmc_clk: clock-mmc {
 598                 #clock-cells = <0>;
 599                 compatible = "fixed-factor-clock";
 600                 clock-output-names = "mmc_clk";
 601                 clocks = <&dpll_per_m2_ck>;
 602                 clock-mult = <1>;
 603                 clock-div = <2>;
 604         };
 605
 606         gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
 607                 #clock-cells = <0>;
 608                 compatible = "ti,mux-clock";
 609                 clock-output-names = "gfx_fclk_clksel_ck";
 610                 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
 611                 ti,bit-shift = <1>;
 612                 reg = <0x423c>;
 613         };
 614
 615         gfx_fck_div_ck: clock-gfx-fck-div@423c {
 616                 #clock-cells = <0>;
 617                 compatible = "ti,divider-clock";
 618                 clock-output-names = "gfx_fck_div_ck";
 619                 clocks = <&gfx_fclk_clksel_ck>;
 620                 reg = <0x423c>;
 621                 ti,max-div = <2>;
 622         };
 623
 624         disp_clk: clock-disp@4244 {
 625                 #clock-cells = <0>;
 626                 compatible = "ti,mux-clock";
 627                 clock-output-names = "disp_clk";
 628                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 629                 reg = <0x4244>;
 630                 ti,set-rate-parent;
 631         };
 632
 633         dpll_extdev_ck: clock@2e60 {
 634                 #clock-cells = <0>;
 635                 compatible = "ti,am3-dpll-clock";
 636                 clock-output-names = "dpll_extdev_ck";
 637                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 638                 reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
 639         };
 640
 641         dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 {
 642                 #clock-cells = <0>;
 643                 compatible = "ti,divider-clock";
 644                 clock-output-names = "dpll_extdev_m2_ck";
 645                 clocks = <&dpll_extdev_ck>;
 646                 ti,max-div = <127>;
 647                 ti,autoidle-shift = <8>;
 648                 reg = <0x2e70>;
 649                 ti,index-starts-at-one;
 650                 ti,invert-autoidle-bit;
 651         };
 652
 653         mux_synctimer32k_ck: clock-mux-synctimer32k@4230 {
 654                 #clock-cells = <0>;
 655                 compatible = "ti,mux-clock";
 656                 clock-output-names = "mux_synctimer32k_ck";
 657                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
 658                 reg = <0x4230>;
 659         };
 660
 661         timer8_fck: clock-timer8-fck@421c {
 662                 #clock-cells = <0>;
 663                 compatible = "ti,mux-clock";
 664                 clock-output-names = "timer8_fck";
 665                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 666                 reg = <0x421c>;
 667         };
 668
 669         timer9_fck: clock-timer9-fck@4220 {
 670                 #clock-cells = <0>;
 671                 compatible = "ti,mux-clock";
 672                 clock-output-names = "timer9_fck";
 673                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 674                 reg = <0x4220>;
 675         };
 676
 677         timer10_fck: clock-timer10-fck@4224 {
 678                 #clock-cells = <0>;
 679                 compatible = "ti,mux-clock";
 680                 clock-output-names = "timer10_fck";
 681                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 682                 reg = <0x4224>;
 683         };
 684
 685         timer11_fck: clock-timer11-fck@4228 {
 686                 #clock-cells = <0>;
 687                 compatible = "ti,mux-clock";
 688                 clock-output-names = "timer11_fck";
 689                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 690                 reg = <0x4228>;
 691         };
 692
 693         cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
 694                 #clock-cells = <0>;
 695                 compatible = "fixed-factor-clock";
 696                 clock-output-names = "cpsw_50m_clkdiv";
 697                 clocks = <&dpll_core_m5_ck>;
 698                 clock-mult = <1>;
 699                 clock-div = <1>;
 700         };
 701
 702         cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
 703                 #clock-cells = <0>;
 704                 compatible = "fixed-factor-clock";
 705                 clock-output-names = "cpsw_5m_clkdiv";
 706                 clocks = <&cpsw_50m_clkdiv>;
 707                 clock-mult = <1>;
 708                 clock-div = <10>;
 709         };
 710
 711         dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
 712                 #clock-cells = <0>;
 713                 compatible = "ti,am3-dpll-x2-clock";
 714                 clock-output-names = "dpll_ddr_x2_ck";
 715                 clocks = <&dpll_ddr_ck>;
 716         };
 717
 718         dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 {
 719                 #clock-cells = <0>;
 720                 compatible = "ti,divider-clock";
 721                 clock-output-names = "dpll_ddr_m4_ck";
 722                 clocks = <&dpll_ddr_x2_ck>;
 723                 ti,max-div = <31>;
 724                 ti,autoidle-shift = <8>;
 725                 reg = <0x2db8>;
 726                 ti,index-starts-at-one;
 727                 ti,invert-autoidle-bit;
 728         };
 729
 730         dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 {
 731                 #clock-cells = <0>;
 732                 compatible = "ti,fixed-factor-clock";
 733                 clock-output-names = "dpll_per_clkdcoldo";
 734                 clocks = <&dpll_per_ck>;
 735                 ti,clock-mult = <1>;
 736                 ti,clock-div = <1>;
 737                 ti,autoidle-shift = <8>;
 738                 reg = <0x2e14>;
 739                 ti,invert-autoidle-bit;
 740         };
 741
 742         dll_aging_clk_div: clock-dll-aging-clk-div@4250 {
 743                 #clock-cells = <0>;
 744                 compatible = "ti,divider-clock";
 745                 clock-output-names = "dll_aging_clk_div";
 746                 clocks = <&sys_clkin_ck>;
 747                 reg = <0x4250>;
 748                 ti,dividers = <8>, <16>, <32>;
 749         };
 750
 751         div_core_25m_ck: clock-div-core-25m {
 752                 #clock-cells = <0>;
 753                 compatible = "fixed-factor-clock";
 754                 clock-output-names = "div_core_25m_ck";
 755                 clocks = <&sysclk_div>;
 756                 clock-mult = <1>;
 757                 clock-div = <8>;
 758         };
 759
 760         func_12m_clk: clock-func-12m {
 761                 #clock-cells = <0>;
 762                 compatible = "fixed-factor-clock";
 763                 clock-output-names = "func_12m_clk";
 764                 clocks = <&dpll_per_m2_ck>;
 765                 clock-mult = <1>;
 766                 clock-div = <16>;
 767         };
 768
 769         vtp_clk_div: clock-vtp-clk-div {
 770                 #clock-cells = <0>;
 771                 compatible = "fixed-factor-clock";
 772                 clock-output-names = "vtp_clk_div";
 773                 clocks = <&sys_clkin_ck>;
 774                 clock-mult = <1>;
 775                 clock-div = <2>;
 776         };
 777
 778         usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 {
 779                 #clock-cells = <0>;
 780                 compatible = "ti,mux-clock";
 781                 clock-output-names = "usbphy_32khz_clkmux";
 782                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 783                 reg = <0x4260>;
 784         };
 785
 786         usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 {
 787                 #clock-cells = <0>;
 788                 compatible = "ti,gate-clock";
 789                 clock-output-names = "usb_phy0_always_on_clk32k";
 790                 clocks = <&usbphy_32khz_clkmux>;
 791                 ti,bit-shift = <8>;
 792                 reg = <0x2a40>;
 793         };
 794
 795         usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 {
 796                 #clock-cells = <0>;
 797                 compatible = "ti,gate-clock";
 798                 clock-output-names = "usb_phy1_always_on_clk32k";
 799                 clocks = <&usbphy_32khz_clkmux>;
 800                 ti,bit-shift = <8>;
 801                 reg = <0x2a48>;
 802         };
 803
 804         clkout1_osc_div_ck: clock-clkout1-osc-div-ck {
 805                 #clock-cells = <0>;
 806                 compatible = "ti,divider-clock";
 807                 clock-output-names = "clkout1_osc_div_ck";
 808                 clocks = <&sys_clkin_ck>;
 809                 ti,bit-shift = <20>;
 810                 ti,max-div = <4>;
 811                 reg = <0x4100>;
 812         };
 813
 814         clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck {
 815                 #clock-cells = <0>;
 816                 compatible = "ti,mux-clock";
 817                 clock-output-names = "clkout1_src2_mux_ck";
 818                 clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
 819                          <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
 820                          <&dpll_mpu_m2_ck>;
 821                 reg = <0x4100>;
 822         };
 823
 824         clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck {
 825                 #clock-cells = <0>;
 826                 compatible = "ti,divider-clock";
 827                 clock-output-names = "clkout1_src2_pre_div_ck";
 828                 clocks = <&clkout1_src2_mux_ck>;
 829                 ti,bit-shift = <4>;
 830                 ti,max-div = <8>;
 831                 reg = <0x4100>;
 832         };
 833
 834         clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck {
 835                 #clock-cells = <0>;
 836                 compatible = "ti,divider-clock";
 837                 clock-output-names = "clkout1_src2_post_div_ck";
 838                 clocks = <&clkout1_src2_pre_div_ck>;
 839                 ti,bit-shift = <8>;
 840                 ti,max-div = <32>;
 841                 ti,index-power-of-two;
 842                 reg = <0x4100>;
 843         };
 844
 845         clkout1_mux_ck: clock-clkout1-mux-ck {
 846                 #clock-cells = <0>;
 847                 compatible = "ti,mux-clock";
 848                 clock-output-names = "clkout1_mux_ck";
 849                 clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
 850                          <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
 851                 ti,bit-shift = <16>;
 852                 reg = <0x4100>;
 853         };
 854
 855         clkout1_ck: clock-clkout1-ck {
 856                 #clock-cells = <0>;
 857                 compatible = "ti,gate-clock";
 858                 clock-output-names = "clkout1_ck";
 859                 clocks = <&clkout1_mux_ck>;
 860                 ti,bit-shift = <23>;
 861                 reg = <0x4100>;
 862         };
 863 };
 864
 865 &prcm {
 866         wkup_cm: clock@2800 {
 867                 compatible = "ti,omap4-cm";
 868                 clock-output-names = "wkup_cm";
 869                 reg = <0x2800 0x400>;
 870                 #address-cells = <1>;
 871                 #size-cells = <1>;
 872                 ranges = <0 0x2800 0x400>;
 873
 874                 l3s_tsc_clkctrl: clock@120 {
 875                         compatible = "ti,clkctrl";
 876                         clock-output-names = "l3s_tsc_clkctrl";
 877                         reg = <0x120 0x4>;
 878                         #clock-cells = <2>;
 879                 };
 880
 881                 l4_wkup_aon_clkctrl: clock@228 {
 882                         compatible = "ti,clkctrl";
 883                         clock-output-names = "l4_wkup_aon_clkctrl";
 884                         reg = <0x228 0xc>;
 885                         #clock-cells = <2>;
 886                 };
 887
 888                 l4_wkup_clkctrl: clock@220 {
 889                         compatible = "ti,clkctrl";
 890                         clock-output-names = "l4_wkup_clkctrl";
 891                         reg = <0x220 0x4>, <0x328 0x44>;
 892                         #clock-cells = <2>;
 893                 };
 894
 895         };
 896
 897         mpu_cm: clock@8300 {
 898                 compatible = "ti,omap4-cm";
 899                 clock-output-names = "mpu_cm";
 900                 reg = <0x8300 0x100>;
 901                 #address-cells = <1>;
 902                 #size-cells = <1>;
 903                 ranges = <0 0x8300 0x100>;
 904
 905                 mpu_clkctrl: clock@20 {
 906                         compatible = "ti,clkctrl";
 907                         clock-output-names = "mpu_clkctrl";
 908                         reg = <0x20 0x4>;
 909                         #clock-cells = <2>;
 910                 };
 911         };
 912
 913         gfx_l3_cm: clock@8400 {
 914                 compatible = "ti,omap4-cm";
 915                 clock-output-names = "gfx_l3_cm";
 916                 reg = <0x8400 0x100>;
 917                 #address-cells = <1>;
 918                 #size-cells = <1>;
 919                 ranges = <0 0x8400 0x100>;
 920
 921                 gfx_l3_clkctrl: clock@20 {
 922                         compatible = "ti,clkctrl";
 923                         clock-output-names = "gfx_l3_clkctrl";
 924                         reg = <0x20 0x4>;
 925                         #clock-cells = <2>;
 926                 };
 927         };
 928
 929         l4_rtc_cm: clock@8500 {
 930                 compatible = "ti,omap4-cm";
 931                 clock-output-names = "l4_rtc_cm";
 932                 reg = <0x8500 0x100>;
 933                 #address-cells = <1>;
 934                 #size-cells = <1>;
 935                 ranges = <0 0x8500 0x100>;
 936
 937                 l4_rtc_clkctrl: clock@20 {
 938                         compatible = "ti,clkctrl";
 939                         clock-output-names = "l4_rtc_clkctrl";
 940                         reg = <0x20 0x4>;
 941                         #clock-cells = <2>;
 942                 };
 943         };
 944
 945         per_cm: clock@8800 {
 946                 compatible = "ti,omap4-cm";
 947                 clock-output-names = "per_cm";
 948                 reg = <0x8800 0xc00>;
 949                 #address-cells = <1>;
 950                 #size-cells = <1>;
 951                 ranges = <0 0x8800 0xc00>;
 952
 953                 l3_clkctrl: clock@20 {
 954                         compatible = "ti,clkctrl";
 955                         clock-output-names = "l3_clkctrl";
 956                         reg = <0x20 0x3c>, <0x78 0x2c>;
 957                         #clock-cells = <2>;
 958                 };
 959
 960                 l3s_clkctrl: clock@68 {
 961                         compatible = "ti,clkctrl";
 962                         clock-output-names = "l3s_clkctrl";
 963                         reg = <0x68 0xc>, <0x220 0x4c>;
 964                         #clock-cells = <2>;
 965                 };
 966
 967                 pruss_ocp_clkctrl: clock@320 {
 968                         compatible = "ti,clkctrl";
 969                         clock-output-names = "pruss_ocp_clkctrl";
 970                         reg = <0x320 0x4>;
 971                         #clock-cells = <2>;
 972                 };
 973
 974                 l4ls_clkctrl: clock@420 {
 975                         compatible = "ti,clkctrl";
 976                         clock-output-names = "l4ls_clkctrl";
 977                         reg = <0x420 0x1a4>;
 978                         #clock-cells = <2>;
 979                 };
 980
 981                 emif_clkctrl: clock@720 {
 982                         compatible = "ti,clkctrl";
 983                         clock-output-names = "emif_clkctrl";
 984                         reg = <0x720 0x4>;
 985                         #clock-cells = <2>;
 986                 };
 987
 988                 dss_clkctrl: clock@a20 {
 989                         compatible = "ti,clkctrl";
 990                         clock-output-names = "dss_clkctrl";
 991                         reg = <0xa20 0x4>;
 992                         #clock-cells = <2>;
 993                 };
 994
 995                 cpsw_125mhz_clkctrl: clock@b20 {
 996                         compatible = "ti,clkctrl";
 997                         clock-output-names = "cpsw_125mhz_clkctrl";
 998                         reg = <0xb20 0x4>;
 999                         #clock-cells = <2>;
1000                 };
1001
1002         };
1003 };