2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
30 evm_v3_3d: fixedregulator-v3_3d {
31 compatible = "regulator-fixed";
32 regulator-name = "evm_v3_3d";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
38 vtt_fixed: fixedregulator-vtt {
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 regulator-min-microvolt = <1500000>;
42 regulator-max-microvolt = <1500000>;
46 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
49 vmmcwl_fixed: fixedregulator-mmcwl {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmcwl_fixed";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
59 compatible = "pwm-backlight";
60 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
61 brightness-levels = <0 51 53 56 62 75 101 152 255>;
62 default-brightness-level = <8>;
65 matrix_keypad: matrix_keypad0 {
66 compatible = "gpio-matrix-keypad";
67 debounce-delay-ms = <5>;
68 col-scan-delay-us = <2>;
70 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
71 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
72 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
74 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
75 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
77 linux,keymap = <0x00000201 /* P1 */
80 0x0101006a /* RIGHT */
82 0x0201006c>; /* DOWN */
86 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
90 clock-frequency = <33000000>;
102 pixelclk-active = <1>;
107 remote-endpoint = <&dpi_out>;
112 /* fixed 12MHz oscillator */
115 compatible = "fixed-clock";
116 clock-frequency = <12000000>;
119 /* fixed 32k external oscillator clock */
120 clk_32k_rtc: clk_32k_rtc {
122 compatible = "fixed-clock";
123 clock-frequency = <32768>;
127 compatible = "simple-audio-card";
128 simple-audio-card,name = "AM437x-GP-EVM";
129 simple-audio-card,widgets =
130 "Headphone", "Headphone Jack",
132 simple-audio-card,routing =
133 "Headphone Jack", "HPLOUT",
134 "Headphone Jack", "HPROUT",
137 simple-audio-card,format = "dsp_b";
138 simple-audio-card,bitclock-master = <&sound0_master>;
139 simple-audio-card,frame-master = <&sound0_master>;
140 simple-audio-card,bitclock-inversion;
142 simple-audio-card,cpu {
143 sound-dai = <&mcasp1>;
144 system-clock-frequency = <12000000>;
147 sound0_master: simple-audio-card,codec {
148 sound-dai = <&tlv320aic3106>;
149 system-clock-frequency = <12000000>;
154 compatible = "gpio-beeper";
155 pinctrl-names = "default";
156 pinctrl-0 = <&beeper_pins>;
157 gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
162 pinctrl-names = "default", "sleep";
163 pinctrl-0 = <&wlan_pins_default>;
164 pinctrl-1 = <&wlan_pins_sleep>;
166 i2c0_pins: i2c0_pins {
167 pinctrl-single,pins = <
168 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
169 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
173 i2c1_pins: i2c1_pins {
174 pinctrl-single,pins = <
175 AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
176 AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
180 mmc1_pins: pinmux_mmc1_pins {
181 pinctrl-single,pins = <
182 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
186 ecap0_pins: backlight_pins {
187 pinctrl-single,pins = <
188 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
192 pixcir_ts_pins: pixcir_ts_pins {
193 pinctrl-single,pins = <
194 AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
198 cpsw_default: cpsw_default {
199 pinctrl-single,pins = <
201 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
202 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
203 AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
204 AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
205 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
206 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
207 AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
208 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
209 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
210 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
211 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
212 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
216 cpsw_sleep: cpsw_sleep {
217 pinctrl-single,pins = <
218 /* Slave 1 reset value */
219 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
220 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
221 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
222 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
223 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
224 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
225 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
226 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
227 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
228 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
229 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
230 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
234 davinci_mdio_default: davinci_mdio_default {
235 pinctrl-single,pins = <
237 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
238 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
242 davinci_mdio_sleep: davinci_mdio_sleep {
243 pinctrl-single,pins = <
244 /* MDIO reset value */
245 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
246 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
250 nand_flash_x8: nand_flash_x8 {
251 pinctrl-single,pins = <
252 AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
253 AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
254 AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
255 AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
256 AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
257 AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
258 AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
259 AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
260 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
261 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
262 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
263 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
264 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
265 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
266 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
271 pinctrl-single,pins = <
272 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
273 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
274 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
275 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
276 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
277 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
278 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
279 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
280 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
281 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
282 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
283 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
284 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
285 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
286 AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
287 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
288 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
289 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
290 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
291 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
292 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
293 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
294 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
295 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
296 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
297 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
298 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
299 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
304 display_mux_pins: display_mux_pins {
305 pinctrl-single,pins = <
306 /* GPIO 5_8 to select LCD / HDMI */
307 AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
311 dcan0_default: dcan0_default_pins {
312 pinctrl-single,pins = <
313 AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
314 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
318 dcan0_sleep: dcan0_sleep_pins {
319 pinctrl-single,pins = <
320 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
321 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
325 dcan1_default: dcan1_default_pins {
326 pinctrl-single,pins = <
327 AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
328 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
332 dcan1_sleep: dcan1_sleep_pins {
333 pinctrl-single,pins = <
334 AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
335 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
339 vpfe0_pins_default: vpfe0_pins_default {
340 pinctrl-single,pins = <
341 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
342 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
343 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
344 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
345 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
346 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
347 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
348 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
349 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
350 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
351 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
352 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
353 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
357 vpfe0_pins_sleep: vpfe0_pins_sleep {
358 pinctrl-single,pins = <
359 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
360 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
361 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
362 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
363 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
364 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
365 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
366 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
367 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
368 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
369 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
370 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
371 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
375 vpfe1_pins_default: vpfe1_pins_default {
376 pinctrl-single,pins = <
377 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
378 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
379 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
380 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
381 AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
382 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
383 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
384 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
385 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
386 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
387 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
388 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
389 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
393 vpfe1_pins_sleep: vpfe1_pins_sleep {
394 pinctrl-single,pins = <
395 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
396 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
397 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
398 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
399 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
400 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
401 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
402 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
403 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
404 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
405 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
406 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
407 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
411 mmc3_pins_default: pinmux_mmc3_pins_default {
412 pinctrl-single,pins = <
413 AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
414 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
415 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
416 AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
417 AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
418 AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
422 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
423 pinctrl-single,pins = <
424 AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
425 AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
426 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
427 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
428 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
429 AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
433 wlan_pins_default: pinmux_wlan_pins_default {
434 pinctrl-single,pins = <
435 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
436 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
437 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
441 wlan_pins_sleep: pinmux_wlan_pins_sleep {
442 pinctrl-single,pins = <
443 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
444 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
445 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
449 uart3_pins: uart3_pins {
450 pinctrl-single,pins = <
451 AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
452 AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
453 AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
454 AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
458 mcasp1_pins: mcasp1_pins {
459 pinctrl-single,pins = <
460 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
461 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
462 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
463 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
467 mcasp1_sleep_pins: mcasp1_sleep_pins {
468 pinctrl-single,pins = <
469 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
470 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
471 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
472 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
476 gpio0_pins: gpio0_pins {
477 pinctrl-single,pins = <
478 AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
482 emmc_pins_default: emmc_pins_default {
483 pinctrl-single,pins = <
484 AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
485 AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
486 AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
487 AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
488 AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
489 AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
490 AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
491 AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
492 AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
493 AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
497 emmc_pins_sleep: emmc_pins_sleep {
498 pinctrl-single,pins = <
499 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
500 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
501 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
502 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
503 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
504 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
505 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
506 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
507 AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
508 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
512 uart0_pins_default: uart0_pins_default {
513 pinctrl-single,pins = <
514 AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
515 AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
516 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
517 AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
521 beeper_pins: beeper_pins {
522 pinctrl-single,pins = <
523 AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
531 pinctrl-names = "default";
532 pinctrl-0 = <&uart0_pins_default>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c0_pins>;
539 clock-frequency = <100000>;
541 tps65218: tps65218@24 {
543 compatible = "ti,tps65218";
544 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
545 interrupt-controller;
546 #interrupt-cells = <2>;
548 dcdc1: regulator-dcdc1 {
549 regulator-name = "vdd_core";
550 regulator-min-microvolt = <912000>;
551 regulator-max-microvolt = <1144000>;
556 dcdc2: regulator-dcdc2 {
557 regulator-name = "vdd_mpu";
558 regulator-min-microvolt = <912000>;
559 regulator-max-microvolt = <1378000>;
564 dcdc3: regulator-dcdc3 {
565 regulator-name = "vdcdc3";
568 regulator-state-mem {
569 regulator-on-in-suspend;
571 regulator-state-disk {
572 regulator-off-in-suspend;
576 dcdc5: regulator-dcdc5 {
577 regulator-name = "v1_0bat";
578 regulator-min-microvolt = <1000000>;
579 regulator-max-microvolt = <1000000>;
582 regulator-state-mem {
583 regulator-on-in-suspend;
587 dcdc6: regulator-dcdc6 {
588 regulator-name = "v1_8bat";
589 regulator-min-microvolt = <1800000>;
590 regulator-max-microvolt = <1800000>;
593 regulator-state-mem {
594 regulator-on-in-suspend;
598 ldo1: regulator-ldo1 {
599 regulator-min-microvolt = <1800000>;
600 regulator-max-microvolt = <1800000>;
607 compatible = "ovti,ov2659";
610 clocks = <&refclk 0>;
611 clock-names = "xvclk";
615 remote-endpoint = <&vpfe1_ep>;
616 link-frequencies = /bits/ 64 <70000000>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c1_pins>;
627 compatible = "pixcir,pixcir_tangoc";
628 pinctrl-names = "default";
629 pinctrl-0 = <&pixcir_ts_pins>;
632 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
635 * 0x264 represents the offset of padconf register of
636 * gpio3_22 from am43xx_pinmux base.
638 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
639 <&am43xx_pinmux 0x264>;
640 interrupt-names = "tsc", "wakeup";
642 touchscreen-size-x = <1024>;
643 touchscreen-size-y = <600>;
648 compatible = "ovti,ov2659";
651 clocks = <&refclk 0>;
652 clock-names = "xvclk";
656 remote-endpoint = <&vpfe0_ep>;
657 link-frequencies = /bits/ 64 <70000000>;
662 tlv320aic3106: tlv320aic3106@1b {
663 #sound-dai-cells = <0>;
664 compatible = "ti,tlv320aic3106";
669 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
670 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
671 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
672 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
684 ti,adc-channels = <0 1 2 3 4 5 6 7>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&ecap0_pins>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&gpio0_pins>;
701 gpios = <23 GPIO_ACTIVE_HIGH>;
702 /* SelEMMCorNAND selects between eMMC and NAND:
705 * When changing this line make sure the newly
706 * selected device node is enabled and the previously
707 * selected device node is disabled.
710 line-name = "SelEMMCorNAND";
727 pinctrl-names = "default";
728 pinctrl-0 = <&display_mux_pins>;
734 * SelLCDorHDMI selects between display and audio paths:
735 * Low: HDMI display with audio via HDMI
736 * High: LCD display with analog audio via aic3111 codec
739 gpios = <8 GPIO_ACTIVE_HIGH>;
741 line-name = "SelLCDorHDMI";
747 vmmc-supply = <&evm_v3_3d>;
749 pinctrl-names = "default";
750 pinctrl-0 = <&mmc1_pins>;
751 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
754 /* eMMC sits on mmc2 */
757 * When enabling eMMC, disable GPMC/NAND and set
758 * SelEMMCorNAND to output-high
761 vmmc-supply = <&evm_v3_3d>;
763 pinctrl-names = "default", "sleep";
764 pinctrl-0 = <&emmc_pins_default>;
765 pinctrl-1 = <&emmc_pins_sleep>;
771 /* these are on the crossbar and are outlined in the
772 xbar-event-map element */
773 dmas = <&edma_xbar 30 0 1>,
775 dma-names = "tx", "rx";
776 vmmc-supply = <&vmmcwl_fixed>;
778 pinctrl-names = "default", "sleep";
779 pinctrl-0 = <&mmc3_pins_default>;
780 pinctrl-1 = <&mmc3_pins_sleep>;
782 keep-power-in-suspend;
785 #address-cells = <1>;
788 compatible = "ti,wl1835";
790 interrupt-parent = <&gpio1>;
791 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart3_pins>;
806 dr_mode = "peripheral";
821 pinctrl-names = "default", "sleep";
822 pinctrl-0 = <&cpsw_default>;
823 pinctrl-1 = <&cpsw_sleep>;
828 pinctrl-names = "default", "sleep";
829 pinctrl-0 = <&davinci_mdio_default>;
830 pinctrl-1 = <&davinci_mdio_sleep>;
835 phy_id = <&davinci_mdio>, <0>;
845 * When enabling GPMC, disable eMMC and set
846 * SelEMMCorNAND to output-low
849 pinctrl-names = "default";
850 pinctrl-0 = <&nand_flash_x8>;
851 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
853 compatible = "ti,omap2-nand";
854 reg = <0 0 4>; /* device IO registers */
855 interrupt-parent = <&gpmc>;
856 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
857 <1 IRQ_TYPE_NONE>; /* termcount */
858 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
859 ti,nand-xfer-type = "prefetch-dma";
860 ti,nand-ecc-opt = "bch16";
862 nand-bus-width = <8>;
863 gpmc,device-width = <1>;
864 gpmc,sync-clk-ps = <0>;
866 gpmc,cs-rd-off-ns = <40>;
867 gpmc,cs-wr-off-ns = <40>;
868 gpmc,adv-on-ns = <0>;
869 gpmc,adv-rd-off-ns = <25>;
870 gpmc,adv-wr-off-ns = <25>;
872 gpmc,we-off-ns = <20>;
874 gpmc,oe-off-ns = <30>;
875 gpmc,access-ns = <30>;
876 gpmc,rd-cycle-ns = <40>;
877 gpmc,wr-cycle-ns = <40>;
878 gpmc,bus-turnaround-ns = <0>;
879 gpmc,cycle2cycle-delay-ns = <0>;
880 gpmc,clk-activation-ns = <0>;
881 gpmc,wr-access-ns = <40>;
882 gpmc,wr-data-mux-bus-ns = <0>;
883 /* MTD partition table */
884 /* All SPL-* partitions are sized to minimal length
885 * which can be independently programmable. For
886 * NAND flash this is equal to size of erase-block */
887 #address-cells = <1>;
891 reg = <0x00000000 0x00040000>;
894 label = "NAND.SPL.backup1";
895 reg = <0x00040000 0x00040000>;
898 label = "NAND.SPL.backup2";
899 reg = <0x00080000 0x00040000>;
902 label = "NAND.SPL.backup3";
903 reg = <0x000c0000 0x00040000>;
906 label = "NAND.u-boot-spl-os";
907 reg = <0x00100000 0x00080000>;
910 label = "NAND.u-boot";
911 reg = <0x00180000 0x00100000>;
914 label = "NAND.u-boot-env";
915 reg = <0x00280000 0x00040000>;
918 label = "NAND.u-boot-env.backup1";
919 reg = <0x002c0000 0x00040000>;
922 label = "NAND.kernel";
923 reg = <0x00300000 0x00700000>;
926 label = "NAND.file-system";
927 reg = <0x00a00000 0x1f600000>;
935 pinctrl-names = "default";
936 pinctrl-0 = <&dss_pins>;
940 remote-endpoint = <&lcd_in>;
947 pinctrl-names = "default", "sleep";
948 pinctrl-0 = <&dcan0_default>;
949 pinctrl-1 = <&dcan0_sleep>;
954 pinctrl-names = "default", "sleep";
955 pinctrl-0 = <&dcan1_default>;
956 pinctrl-1 = <&dcan1_sleep>;
962 pinctrl-names = "default", "sleep";
963 pinctrl-0 = <&vpfe0_pins_default>;
964 pinctrl-1 = <&vpfe0_pins_sleep>;
968 remote-endpoint = <&ov2659_1>;
969 ti,am437x-vpfe-interface = <0>;
979 pinctrl-names = "default", "sleep";
980 pinctrl-0 = <&vpfe1_pins_default>;
981 pinctrl-1 = <&vpfe1_pins_sleep>;
985 remote-endpoint = <&ov2659_0>;
986 ti,am437x-vpfe-interface = <0>;
995 #sound-dai-cells = <0>;
996 pinctrl-names = "default", "sleep";
997 pinctrl-0 = <&mcasp1_pins>;
998 pinctrl-1 = <&mcasp1_sleep_pins>;
1002 op-mode = <0>; /* MCASP_IIS_MODE */
1005 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1013 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
1014 clock-names = "ext-clk", "int-clk";
1019 cpu0-supply = <&dcdc2>;