2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/am4.h>
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
24 device_type = "memory";
38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
47 compatible = "arm,cortex-a9";
51 clocks = <&dpll_mpu_ck>;
54 operating-points-v2 = <&cpu0_opp_table>;
56 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu0_opp_table: opp-table {
61 compatible = "operating-points-v2-ti-cpu";
65 opp-hz = /bits/ 64 <300000000>;
66 opp-microvolt = <950000 931000 969000>;
67 opp-supported-hw = <0xFF 0x01>;
72 opp-hz = /bits/ 64 <600000000>;
73 opp-microvolt = <1100000 1078000 1122000>;
74 opp-supported-hw = <0xFF 0x04>;
78 opp-hz = /bits/ 64 <720000000>;
79 opp-microvolt = <1200000 1176000 1224000>;
80 opp-supported-hw = <0xFF 0x08>;
84 opp-hz = /bits/ 64 <800000000>;
85 opp-microvolt = <1260000 1234800 1285200>;
86 opp-supported-hw = <0xFF 0x10>;
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = <1325000 1298500 1351500>;
92 opp-supported-hw = <0xFF 0x20>;
97 compatible = "ti,omap-infra";
99 compatible = "ti,omap4-mpu";
101 pm-sram = <&pm_sram_code
106 gic: interrupt-controller@48241000 {
107 compatible = "arm,cortex-a9-gic";
108 interrupt-controller;
109 #interrupt-cells = <3>;
110 reg = <0x48241000 0x1000>,
112 interrupt-parent = <&gic>;
115 wakeupgen: interrupt-controller@48281000 {
116 compatible = "ti,omap4-wugen-mpu";
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 reg = <0x48281000 0x1000>;
120 interrupt-parent = <&gic>;
124 compatible = "arm,cortex-a9-scu";
125 reg = <0x48240000 0x100>;
128 global_timer: timer@48240200 {
129 compatible = "arm,cortex-a9-global-timer";
130 reg = <0x48240200 0x100>;
131 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
132 interrupt-parent = <&gic>;
133 clocks = <&mpu_periphclk>;
136 local_timer: timer@48240600 {
137 compatible = "arm,cortex-a9-twd-timer";
138 reg = <0x48240600 0x100>;
139 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
140 interrupt-parent = <&gic>;
141 clocks = <&mpu_periphclk>;
144 l2-cache-controller@48242000 {
145 compatible = "arm,pl310-cache";
146 reg = <0x48242000 0x1000>;
152 compatible = "ti,am4372-l3-noc", "simple-bus";
153 #address-cells = <1>;
156 ti,hwmods = "l3_main";
158 reg = <0x44000000 0x400000
159 0x44800000 0x400000>;
160 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
163 l4_wkup: interconnect@44c00000 {
164 wkup_m3: wkup_m3@100000 {
165 compatible = "ti,am4372-wkup-m3";
166 reg = <0x100000 0x4000>,
168 reg-names = "umem", "dmem";
169 ti,hwmods = "wkup_m3";
170 ti,pm-firmware = "am335x-pm-firmware.elf";
173 l4_per: interconnect@48000000 {
175 l4_fast: interconnect@4a000000 {
178 emif: emif@4c000000 {
179 compatible = "ti,emif-am4372";
180 reg = <0x4c000000 0x1000000>;
182 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
184 sram = <&pm_sram_code
188 edma: edma@49000000 {
189 compatible = "ti,edma3-tpcc";
191 reg = <0x49000000 0x10000>;
192 reg-names = "edma3_cc";
193 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-names = "edma3_ccint", "edma3_mperr",
201 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
204 ti,edma-memcpy-channels = <58 59>;
207 edma_tptc0: tptc@49800000 {
208 compatible = "ti,edma3-tptc";
210 reg = <0x49800000 0x100000>;
211 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "edma3_tcerrint";
215 edma_tptc1: tptc@49900000 {
216 compatible = "ti,edma3-tptc";
218 reg = <0x49900000 0x100000>;
219 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-names = "edma3_tcerrint";
223 edma_tptc2: tptc@49a00000 {
224 compatible = "ti,edma3-tptc";
226 reg = <0x49a00000 0x100000>;
227 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
228 interrupt-names = "edma3_tcerrint";
231 target-module@47810000 {
232 compatible = "ti,sysc-omap2", "ti,sysc";
233 reg = <0x478102fc 0x4>,
236 reg-names = "rev", "sysc", "syss";
237 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
238 SYSC_OMAP2_ENAWAKEUP |
239 SYSC_OMAP2_SOFTRESET |
240 SYSC_OMAP2_AUTOIDLE)>;
241 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
245 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
247 #address-cells = <1>;
249 ranges = <0x0 0x47810000 0x1000>;
252 compatible = "ti,omap4-hsmmc";
253 ti,needs-special-reset;
254 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
259 sham_target: target-module@53100000 {
260 compatible = "ti,sysc-omap3-sham", "ti,sysc";
261 reg = <0x53100100 0x4>,
264 reg-names = "rev", "sysc", "syss";
265 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
266 SYSC_OMAP2_AUTOIDLE)>;
267 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
271 /* Domains (P, C): per_pwrdm, l3_clkdm */
272 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
274 #address-cells = <1>;
276 ranges = <0x0 0x53100000 0x1000>;
279 compatible = "ti,omap5-sham";
283 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
287 aes_target: target-module@53501000 {
288 compatible = "ti,sysc-omap2", "ti,sysc";
289 reg = <0x53501080 0x4>,
292 reg-names = "rev", "sysc", "syss";
293 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
294 SYSC_OMAP2_AUTOIDLE)>;
295 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
298 <SYSC_IDLE_SMART_WKUP>;
300 /* Domains (P, C): per_pwrdm, l3_clkdm */
301 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
303 #address-cells = <1>;
305 ranges = <0x0 0x53501000 0x1000>;
308 compatible = "ti,omap4-aes";
310 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
313 dma-names = "tx", "rx";
317 des_target: target-module@53701000 {
318 compatible = "ti,sysc-omap2", "ti,sysc";
319 reg = <0x53701030 0x4>,
322 reg-names = "rev", "sysc", "syss";
323 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
324 SYSC_OMAP2_AUTOIDLE)>;
325 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
328 <SYSC_IDLE_SMART_WKUP>;
330 /* Domains (P, C): per_pwrdm, l3_clkdm */
331 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
333 #address-cells = <1>;
335 ranges = <0 0x53701000 0x1000>;
338 compatible = "ti,omap4-des";
340 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
343 dma-names = "tx", "rx";
347 gpmc: gpmc@50000000 {
348 compatible = "ti,am3352-gpmc";
352 clocks = <&l3s_gclk>;
354 reg = <0x50000000 0x2000>;
355 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
357 gpmc,num-waitpins = <2>;
358 #address-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
367 target-module@47900000 {
368 compatible = "ti,sysc-omap4", "ti,sysc";
369 reg = <0x47900000 0x4>,
371 reg-names = "rev", "sysc";
372 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
375 <SYSC_IDLE_SMART_WKUP>;
376 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
378 #address-cells = <1>;
380 ranges = <0x0 0x47900000 0x1000>,
381 <0x30000000 0x30000000 0x4000000>;
384 compatible = "ti,am4372-qspi";
386 <0x30000000 0x4000000>;
387 reg-names = "qspi_base", "qspi_mmap";
388 clocks = <&dpll_per_m2_div4_ck>;
390 #address-cells = <1>;
392 interrupts = <0 138 0x4>;
398 compatible = "ti,omap3-dss";
399 reg = <0x4832a000 0x200>;
401 ti,hwmods = "dss_core";
402 clocks = <&disp_clk>;
404 #address-cells = <1>;
408 dispc: dispc@4832a400 {
409 compatible = "ti,omap3-dispc";
410 reg = <0x4832a400 0x400>;
411 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
412 ti,hwmods = "dss_dispc";
413 clocks = <&disp_clk>;
416 max-memory-bandwidth = <230000000>;
419 rfbi: rfbi@4832a800 {
420 compatible = "ti,omap3-rfbi";
421 reg = <0x4832a800 0x100>;
422 ti,hwmods = "dss_rfbi";
423 clocks = <&disp_clk>;
429 ocmcram: sram@40300000 {
430 compatible = "mmio-sram";
431 reg = <0x40300000 0x40000>; /* 256k */
432 ranges = <0x0 0x40300000 0x40000>;
433 #address-cells = <1>;
436 pm_sram_code: pm-code-sram@0 {
437 compatible = "ti,sram";
442 pm_sram_data: pm-data-sram@1000 {
443 compatible = "ti,sram";
444 reg = <0x1000 0x1000>;
449 target-module@56000000 {
450 compatible = "ti,sysc-omap4", "ti,sysc";
451 reg = <0x5600fe00 0x4>,
453 reg-names = "rev", "sysc";
454 ti,sysc-midle = <SYSC_IDLE_FORCE>,
457 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
460 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
462 resets = <&prm_gfx 0>;
463 reset-names = "rstctrl";
464 #address-cells = <1>;
466 ranges = <0 0x56000000 0x1000000>;
471 #include "am437x-l4.dtsi"
472 #include "am43xx-clocks.dtsi"
476 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
482 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
488 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
489 reg = <0x2000 0x100>;
493 prm_device: prm@4000 {
494 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
495 reg = <0x4000 0x100>;