2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/am4.h>
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
24 device_type = "memory";
38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
47 compatible = "arm,cortex-a9";
48 enable-method = "ti,am4372";
52 clocks = <&dpll_mpu_ck>;
55 operating-points-v2 = <&cpu0_opp_table>;
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cpu-idle-states = <&mpu_gate>;
63 compatible = "arm,idle-state";
64 entry-latency-us = <40>;
65 exit-latency-us = <100>;
66 min-residency-us = <300>;
72 cpu0_opp_table: opp-table {
73 compatible = "operating-points-v2-ti-cpu";
77 opp-hz = /bits/ 64 <300000000>;
78 opp-microvolt = <950000 931000 969000>;
79 opp-supported-hw = <0xFF 0x01>;
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0xFF 0x04>;
90 opp-hz = /bits/ 64 <720000000>;
91 opp-microvolt = <1200000 1176000 1224000>;
92 opp-supported-hw = <0xFF 0x08>;
96 opp-hz = /bits/ 64 <800000000>;
97 opp-microvolt = <1260000 1234800 1285200>;
98 opp-supported-hw = <0xFF 0x10>;
101 oppnitro-1000000000 {
102 opp-hz = /bits/ 64 <1000000000>;
103 opp-microvolt = <1325000 1298500 1351500>;
104 opp-supported-hw = <0xFF 0x20>;
109 compatible = "ti,omap-infra";
111 compatible = "ti,omap4-mpu";
113 pm-sram = <&pm_sram_code
118 gic: interrupt-controller@48241000 {
119 compatible = "arm,cortex-a9-gic";
120 interrupt-controller;
121 #interrupt-cells = <3>;
122 reg = <0x48241000 0x1000>,
124 interrupt-parent = <&gic>;
127 wakeupgen: interrupt-controller@48281000 {
128 compatible = "ti,omap4-wugen-mpu";
129 interrupt-controller;
130 #interrupt-cells = <3>;
131 reg = <0x48281000 0x1000>;
132 interrupt-parent = <&gic>;
136 compatible = "arm,cortex-a9-scu";
137 reg = <0x48240000 0x100>;
140 global_timer: timer@48240200 {
141 compatible = "arm,cortex-a9-global-timer";
142 reg = <0x48240200 0x100>;
143 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
144 interrupt-parent = <&gic>;
145 clocks = <&mpu_periphclk>;
148 local_timer: timer@48240600 {
149 compatible = "arm,cortex-a9-twd-timer";
150 reg = <0x48240600 0x100>;
151 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
152 interrupt-parent = <&gic>;
153 clocks = <&mpu_periphclk>;
156 l2-cache-controller@48242000 {
157 compatible = "arm,pl310-cache";
158 reg = <0x48242000 0x1000>;
164 compatible = "ti,am4372-l3-noc", "simple-bus";
165 #address-cells = <1>;
168 ti,hwmods = "l3_main";
170 reg = <0x44000000 0x400000
171 0x44800000 0x400000>;
172 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
175 l4_wkup: interconnect@44c00000 {
176 wkup_m3: wkup_m3@100000 {
177 compatible = "ti,am4372-wkup-m3";
178 reg = <0x100000 0x4000>,
180 reg-names = "umem", "dmem";
181 ti,hwmods = "wkup_m3";
182 ti,pm-firmware = "am335x-pm-firmware.elf";
185 l4_per: interconnect@48000000 {
187 l4_fast: interconnect@4a000000 {
190 emif: emif@4c000000 {
191 compatible = "ti,emif-am4372";
192 reg = <0x4c000000 0x1000000>;
194 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
196 sram = <&pm_sram_code
200 target-module@49000000 {
201 compatible = "ti,sysc-omap4", "ti,sysc";
202 reg = <0x49000000 0x4>;
204 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
206 #address-cells = <1>;
208 ranges = <0x0 0x49000000 0x10000>;
211 compatible = "ti,edma3-tpcc";
213 reg-names = "edma3_cc";
214 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "edma3_ccint", "edma3_mperr",
222 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
225 ti,edma-memcpy-channels = <58 59>;
229 target-module@49800000 {
230 compatible = "ti,sysc-omap4", "ti,sysc";
231 reg = <0x49800000 0x4>,
233 reg-names = "rev", "sysc";
234 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
235 ti,sysc-midle = <SYSC_IDLE_FORCE>;
236 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
238 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
240 #address-cells = <1>;
242 ranges = <0x0 0x49800000 0x100000>;
245 compatible = "ti,edma3-tptc";
247 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "edma3_tcerrint";
252 target-module@49900000 {
253 compatible = "ti,sysc-omap4", "ti,sysc";
254 reg = <0x49900000 0x4>,
256 reg-names = "rev", "sysc";
257 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
258 ti,sysc-midle = <SYSC_IDLE_FORCE>;
259 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
261 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
263 #address-cells = <1>;
265 ranges = <0x0 0x49900000 0x100000>;
268 compatible = "ti,edma3-tptc";
270 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "edma3_tcerrint";
275 target-module@49a00000 {
276 compatible = "ti,sysc-omap4", "ti,sysc";
277 reg = <0x49a00000 0x4>,
279 reg-names = "rev", "sysc";
280 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
281 ti,sysc-midle = <SYSC_IDLE_FORCE>;
282 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
284 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
286 #address-cells = <1>;
288 ranges = <0x0 0x49a00000 0x100000>;
291 compatible = "ti,edma3-tptc";
293 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-names = "edma3_tcerrint";
298 target-module@47810000 {
299 compatible = "ti,sysc-omap2", "ti,sysc";
300 reg = <0x478102fc 0x4>,
303 reg-names = "rev", "sysc", "syss";
304 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
305 SYSC_OMAP2_ENAWAKEUP |
306 SYSC_OMAP2_SOFTRESET |
307 SYSC_OMAP2_AUTOIDLE)>;
308 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
312 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
314 #address-cells = <1>;
316 ranges = <0x0 0x47810000 0x1000>;
319 compatible = "ti,omap4-hsmmc";
320 ti,needs-special-reset;
321 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
326 sham_target: target-module@53100000 {
327 compatible = "ti,sysc-omap3-sham", "ti,sysc";
328 reg = <0x53100100 0x4>,
331 reg-names = "rev", "sysc", "syss";
332 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
333 SYSC_OMAP2_AUTOIDLE)>;
334 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
338 /* Domains (P, C): per_pwrdm, l3_clkdm */
339 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
341 #address-cells = <1>;
343 ranges = <0x0 0x53100000 0x1000>;
346 compatible = "ti,omap5-sham";
350 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
354 aes_target: target-module@53501000 {
355 compatible = "ti,sysc-omap2", "ti,sysc";
356 reg = <0x53501080 0x4>,
359 reg-names = "rev", "sysc", "syss";
360 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
361 SYSC_OMAP2_AUTOIDLE)>;
362 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
365 <SYSC_IDLE_SMART_WKUP>;
367 /* Domains (P, C): per_pwrdm, l3_clkdm */
368 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
370 #address-cells = <1>;
372 ranges = <0x0 0x53501000 0x1000>;
375 compatible = "ti,omap4-aes";
377 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
380 dma-names = "tx", "rx";
384 des_target: target-module@53701000 {
385 compatible = "ti,sysc-omap2", "ti,sysc";
386 reg = <0x53701030 0x4>,
389 reg-names = "rev", "sysc", "syss";
390 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
391 SYSC_OMAP2_AUTOIDLE)>;
392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
395 <SYSC_IDLE_SMART_WKUP>;
397 /* Domains (P, C): per_pwrdm, l3_clkdm */
398 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
400 #address-cells = <1>;
402 ranges = <0 0x53701000 0x1000>;
405 compatible = "ti,omap4-des";
407 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
410 dma-names = "tx", "rx";
414 pruss_tm: target-module@54400000 {
415 compatible = "ti,sysc-pruss", "ti,sysc";
416 reg = <0x54426000 0x4>,
418 reg-names = "rev", "sysc";
419 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
420 SYSC_PRUSS_SUB_MWAIT)>;
421 ti,sysc-midle = <SYSC_IDLE_FORCE>,
424 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
427 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
429 resets = <&prm_per 1>;
430 reset-names = "rstctrl";
431 #address-cells = <1>;
433 ranges = <0x0 0x54400000 0x80000>;
436 gpmc: gpmc@50000000 {
437 compatible = "ti,am3352-gpmc";
441 clocks = <&l3s_gclk>;
443 reg = <0x50000000 0x2000>;
444 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
446 gpmc,num-waitpins = <2>;
447 #address-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
456 target-module@47900000 {
457 compatible = "ti,sysc-omap4", "ti,sysc";
458 reg = <0x47900000 0x4>,
460 reg-names = "rev", "sysc";
461 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
464 <SYSC_IDLE_SMART_WKUP>;
465 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
467 #address-cells = <1>;
469 ranges = <0x0 0x47900000 0x1000>,
470 <0x30000000 0x30000000 0x4000000>;
473 compatible = "ti,am4372-qspi";
475 <0x30000000 0x4000000>;
476 reg-names = "qspi_base", "qspi_mmap";
477 clocks = <&dpll_per_m2_div4_ck>;
479 #address-cells = <1>;
481 interrupts = <0 138 0x4>;
486 ocmcram: sram@40300000 {
487 compatible = "mmio-sram";
488 reg = <0x40300000 0x40000>; /* 256k */
489 ranges = <0x0 0x40300000 0x40000>;
490 #address-cells = <1>;
493 pm_sram_code: pm-code-sram@0 {
494 compatible = "ti,sram";
499 pm_sram_data: pm-data-sram@1000 {
500 compatible = "ti,sram";
501 reg = <0x1000 0x1000>;
506 target-module@56000000 {
507 compatible = "ti,sysc-omap4", "ti,sysc";
508 reg = <0x5600fe00 0x4>,
510 reg-names = "rev", "sysc";
511 ti,sysc-midle = <SYSC_IDLE_FORCE>,
514 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
517 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
519 resets = <&prm_gfx 0>;
520 reset-names = "rstctrl";
521 #address-cells = <1>;
523 ranges = <0 0x56000000 0x1000000>;
528 #include "am437x-l4.dtsi"
529 #include "am43xx-clocks.dtsi"
533 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
539 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
545 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
546 reg = <0x2000 0x100>;
550 prm_device: prm@4000 {
551 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
552 reg = <0x4000 0x100>;