2 * Device Tree Source for AM33XX SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
49 compatible = "arm,cortex-a8";
50 enable-method = "ti,am3352";
54 operating-points-v2 = <&cpu0_opp_table>;
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu-idle-states = <&mpu_gate>;
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
148 compatible = "arm,cortex-a8-pmu";
150 reg = <0x4b000000 0x1000000>;
151 ti,hwmods = "debugss";
155 * The soc node represents the soc top level view. It is used for IPs
156 * that are not memory mapped in the MPU view or for the MPU itself.
159 compatible = "ti,omap-infra";
161 compatible = "ti,omap3-mpu";
163 pm-sram = <&pm_sram_code
169 * XXX: Use a flat representation of the AM33XX interconnect.
170 * The real AM33XX interconnect network is quite complex. Since
171 * it will not bring real advantage to represent that in DT
172 * for the moment, just use a fake OCP bus entry to represent
173 * the whole bus hierarchy.
176 compatible = "simple-bus";
177 #address-cells = <1>;
180 ti,hwmods = "l3_main";
182 l4_wkup: interconnect@44c00000 {
183 wkup_m3: wkup_m3@100000 {
184 compatible = "ti,am3352-wkup-m3";
185 reg = <0x100000 0x4000>,
187 reg-names = "umem", "dmem";
188 ti,hwmods = "wkup_m3";
189 ti,pm-firmware = "am335x-pm-firmware.elf";
192 l4_per: interconnect@48000000 {
194 l4_fw: interconnect@47c00000 {
196 l4_fast: interconnect@4a000000 {
198 l4_mpuss: interconnect@4b140000 {
201 intc: interrupt-controller@48200000 {
202 compatible = "ti,am33xx-intc";
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 reg = <0x48200000 0x1000>;
208 target-module@49000000 {
209 compatible = "ti,sysc-omap4", "ti,sysc";
210 reg = <0x49000000 0x4>;
212 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
214 #address-cells = <1>;
216 ranges = <0x0 0x49000000 0x10000>;
219 compatible = "ti,edma3-tpcc";
221 reg-names = "edma3_cc";
222 interrupts = <12 13 14>;
223 interrupt-names = "edma3_ccint", "edma3_mperr",
228 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
231 ti,edma-memcpy-channels = <20 21>;
235 target-module@49800000 {
236 compatible = "ti,sysc-omap4", "ti,sysc";
237 reg = <0x49800000 0x4>,
239 reg-names = "rev", "sysc";
240 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
241 ti,sysc-midle = <SYSC_IDLE_FORCE>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
244 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
246 #address-cells = <1>;
248 ranges = <0x0 0x49800000 0x100000>;
251 compatible = "ti,edma3-tptc";
254 interrupt-names = "edma3_tcerrint";
258 target-module@49900000 {
259 compatible = "ti,sysc-omap4", "ti,sysc";
260 reg = <0x49900000 0x4>,
262 reg-names = "rev", "sysc";
263 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
264 ti,sysc-midle = <SYSC_IDLE_FORCE>;
265 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
267 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
269 #address-cells = <1>;
271 ranges = <0x0 0x49900000 0x100000>;
274 compatible = "ti,edma3-tptc";
277 interrupt-names = "edma3_tcerrint";
281 target-module@49a00000 {
282 compatible = "ti,sysc-omap4", "ti,sysc";
283 reg = <0x49a00000 0x4>,
285 reg-names = "rev", "sysc";
286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
287 ti,sysc-midle = <SYSC_IDLE_FORCE>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
290 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
292 #address-cells = <1>;
294 ranges = <0x0 0x49a00000 0x100000>;
297 compatible = "ti,edma3-tptc";
300 interrupt-names = "edma3_tcerrint";
304 target-module@47810000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x478102fc 0x4>,
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
311 SYSC_OMAP2_ENAWAKEUP |
312 SYSC_OMAP2_SOFTRESET |
313 SYSC_OMAP2_AUTOIDLE)>;
314 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
318 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
320 #address-cells = <1>;
322 ranges = <0x0 0x47810000 0x1000>;
325 compatible = "ti,am335-sdhci";
326 ti,needs-special-reset;
333 usb: target-module@47400000 {
334 compatible = "ti,sysc-omap4", "ti,sysc";
335 reg = <0x47400000 0x4>,
337 reg-names = "rev", "sysc";
338 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
339 SYSC_OMAP4_SOFTRESET)>;
340 ti,sysc-midle = <SYSC_IDLE_FORCE>,
343 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
346 <SYSC_IDLE_SMART_WKUP>;
347 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
349 #address-cells = <1>;
351 ranges = <0x0 0x47400000 0x8000>;
353 usb0_phy: usb-phy@1300 {
354 compatible = "ti,am335x-usb-phy";
355 reg = <0x1300 0x100>;
357 ti,ctrl_mod = <&usb_ctrl_mod>;
362 compatible = "ti,musb-am33xx";
363 reg = <0x1400 0x400>,
365 reg-names = "mc", "control";
368 interrupt-names = "mc";
370 mentor,multipoint = <1>;
371 mentor,num-eps = <16>;
372 mentor,ram-bits = <12>;
373 mentor,power = <500>;
376 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
377 &cppi41dma 2 0 &cppi41dma 3 0
378 &cppi41dma 4 0 &cppi41dma 5 0
379 &cppi41dma 6 0 &cppi41dma 7 0
380 &cppi41dma 8 0 &cppi41dma 9 0
381 &cppi41dma 10 0 &cppi41dma 11 0
382 &cppi41dma 12 0 &cppi41dma 13 0
383 &cppi41dma 14 0 &cppi41dma 0 1
384 &cppi41dma 1 1 &cppi41dma 2 1
385 &cppi41dma 3 1 &cppi41dma 4 1
386 &cppi41dma 5 1 &cppi41dma 6 1
387 &cppi41dma 7 1 &cppi41dma 8 1
388 &cppi41dma 9 1 &cppi41dma 10 1
389 &cppi41dma 11 1 &cppi41dma 12 1
390 &cppi41dma 13 1 &cppi41dma 14 1>;
392 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
393 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
395 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
396 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
400 usb1_phy: usb-phy@1b00 {
401 compatible = "ti,am335x-usb-phy";
402 reg = <0x1b00 0x100>;
404 ti,ctrl_mod = <&usb_ctrl_mod>;
409 compatible = "ti,musb-am33xx";
410 reg = <0x1c00 0x400>,
412 reg-names = "mc", "control";
414 interrupt-names = "mc";
416 mentor,multipoint = <1>;
417 mentor,num-eps = <16>;
418 mentor,ram-bits = <12>;
419 mentor,power = <500>;
422 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
423 &cppi41dma 17 0 &cppi41dma 18 0
424 &cppi41dma 19 0 &cppi41dma 20 0
425 &cppi41dma 21 0 &cppi41dma 22 0
426 &cppi41dma 23 0 &cppi41dma 24 0
427 &cppi41dma 25 0 &cppi41dma 26 0
428 &cppi41dma 27 0 &cppi41dma 28 0
429 &cppi41dma 29 0 &cppi41dma 15 1
430 &cppi41dma 16 1 &cppi41dma 17 1
431 &cppi41dma 18 1 &cppi41dma 19 1
432 &cppi41dma 20 1 &cppi41dma 21 1
433 &cppi41dma 22 1 &cppi41dma 23 1
434 &cppi41dma 24 1 &cppi41dma 25 1
435 &cppi41dma 26 1 &cppi41dma 27 1
436 &cppi41dma 28 1 &cppi41dma 29 1>;
438 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
439 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
441 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
442 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
446 cppi41dma: dma-controller@2000 {
447 compatible = "ti,am3359-cppi41";
448 reg = <0x0000 0x1000>,
452 reg-names = "glue", "controller", "scheduler", "queuemgr";
454 interrupt-names = "glue";
456 #dma-channels = <30>;
457 #dma-requests = <256>;
461 ocmcram: sram@40300000 {
462 compatible = "mmio-sram";
463 reg = <0x40300000 0x10000>; /* 64k */
464 ranges = <0x0 0x40300000 0x10000>;
465 #address-cells = <1>;
468 pm_sram_code: pm-code-sram@0 {
469 compatible = "ti,sram";
474 pm_sram_data: pm-data-sram@1000 {
475 compatible = "ti,sram";
476 reg = <0x1000 0x1000>;
481 emif: emif@4c000000 {
482 compatible = "ti,emif-am3352";
483 reg = <0x4c000000 0x1000000>;
486 sram = <&pm_sram_code
491 gpmc: gpmc@50000000 {
492 compatible = "ti,am3352-gpmc";
495 reg = <0x50000000 0x2000>;
500 gpmc,num-waitpins = <2>;
501 #address-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
510 sham_target: target-module@53100000 {
511 compatible = "ti,sysc-omap3-sham", "ti,sysc";
512 reg = <0x53100100 0x4>,
515 reg-names = "rev", "sysc", "syss";
516 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
517 SYSC_OMAP2_AUTOIDLE)>;
518 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
522 /* Domains (P, C): per_pwrdm, l3_clkdm */
523 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
525 #address-cells = <1>;
527 ranges = <0x0 0x53100000 0x1000>;
530 compatible = "ti,omap4-sham";
538 aes_target: target-module@53500000 {
539 compatible = "ti,sysc-omap2", "ti,sysc";
540 reg = <0x53500080 0x4>,
543 reg-names = "rev", "sysc", "syss";
544 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
545 SYSC_OMAP2_AUTOIDLE)>;
546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
549 <SYSC_IDLE_SMART_WKUP>;
551 /* Domains (P, C): per_pwrdm, l3_clkdm */
552 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
554 #address-cells = <1>;
556 ranges = <0x0 0x53500000 0x1000>;
559 compatible = "ti,omap4-aes";
564 dma-names = "tx", "rx";
568 target-module@56000000 {
569 compatible = "ti,sysc-omap4", "ti,sysc";
570 reg = <0x5600fe00 0x4>,
572 reg-names = "rev", "sysc";
573 ti,sysc-midle = <SYSC_IDLE_FORCE>,
576 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
579 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
581 resets = <&prm_gfx 0>;
582 reset-names = "rstctrl";
583 #address-cells = <1>;
585 ranges = <0 0x56000000 0x1000000>;
588 * Closed source PowerVR driver, no child device
589 * binding or driver in mainline
595 #include "am33xx-l4.dtsi"
596 #include "am33xx-clocks.dtsi"
600 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
606 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
611 prm_device: prm@f00 {
612 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
618 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
619 reg = <0x1100 0x100>;
624 /* Preferred always-on timer for clocksource */
629 assigned-clocks = <&timer1_fck>;
630 assigned-clock-parents = <&sys_clkin_ck>;
634 /* Preferred timer for clockevent */
639 assigned-clocks = <&timer2_fck>;
640 assigned-clock-parents = <&sys_clkin_ck>;