2 * Device Tree Source for AM33xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 sys_clkin_ck: sys_clkin_ck@40 {
13 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
19 adc_tsc_fck: adc_tsc_fck {
21 compatible = "fixed-factor-clock";
22 clocks = <&sys_clkin_ck>;
27 dcan0_fck: dcan0_fck {
29 compatible = "fixed-factor-clock";
30 clocks = <&sys_clkin_ck>;
35 dcan1_fck: dcan1_fck {
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
43 mcasp0_fck: mcasp0_fck {
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
51 mcasp1_fck: mcasp1_fck {
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
59 smartreflex0_fck: smartreflex0_fck {
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
67 smartreflex1_fck: smartreflex1_fck {
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
93 compatible = "fixed-factor-clock";
94 clocks = <&sys_clkin_ck>;
99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
101 compatible = "ti,gate-clock";
102 clocks = <&l4ls_gclk>;
107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
109 compatible = "ti,gate-clock";
110 clocks = <&l4ls_gclk>;
115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
117 compatible = "ti,gate-clock";
118 clocks = <&l4ls_gclk>;
124 clk_32768_ck: clk_32768_ck {
126 compatible = "fixed-clock";
127 clock-frequency = <32768>;
130 clk_rc32k_ck: clk_rc32k_ck {
132 compatible = "fixed-clock";
133 clock-frequency = <32000>;
136 virt_19200000_ck: virt_19200000_ck {
138 compatible = "fixed-clock";
139 clock-frequency = <19200000>;
142 virt_24000000_ck: virt_24000000_ck {
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
148 virt_25000000_ck: virt_25000000_ck {
150 compatible = "fixed-clock";
151 clock-frequency = <25000000>;
154 virt_26000000_ck: virt_26000000_ck {
156 compatible = "fixed-clock";
157 clock-frequency = <26000000>;
160 tclkin_ck: tclkin_ck {
162 compatible = "fixed-clock";
163 clock-frequency = <12000000>;
166 dpll_core_ck: dpll_core_ck@490 {
168 compatible = "ti,am3-dpll-core-clock";
169 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
170 reg = <0x0490>, <0x045c>, <0x0468>;
173 dpll_core_x2_ck: dpll_core_x2_ck {
175 compatible = "ti,am3-dpll-x2-clock";
176 clocks = <&dpll_core_ck>;
179 dpll_core_m4_ck: dpll_core_m4_ck@480 {
181 compatible = "ti,divider-clock";
182 clocks = <&dpll_core_x2_ck>;
185 ti,index-starts-at-one;
188 dpll_core_m5_ck: dpll_core_m5_ck@484 {
190 compatible = "ti,divider-clock";
191 clocks = <&dpll_core_x2_ck>;
194 ti,index-starts-at-one;
197 dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
199 compatible = "ti,divider-clock";
200 clocks = <&dpll_core_x2_ck>;
203 ti,index-starts-at-one;
206 dpll_mpu_ck: dpll_mpu_ck@488 {
208 compatible = "ti,am3-dpll-clock";
209 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
210 reg = <0x0488>, <0x0420>, <0x042c>;
213 dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
215 compatible = "ti,divider-clock";
216 clocks = <&dpll_mpu_ck>;
219 ti,index-starts-at-one;
222 dpll_ddr_ck: dpll_ddr_ck@494 {
224 compatible = "ti,am3-dpll-no-gate-clock";
225 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
226 reg = <0x0494>, <0x0434>, <0x0440>;
229 dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
231 compatible = "ti,divider-clock";
232 clocks = <&dpll_ddr_ck>;
235 ti,index-starts-at-one;
238 dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
240 compatible = "fixed-factor-clock";
241 clocks = <&dpll_ddr_m2_ck>;
246 dpll_disp_ck: dpll_disp_ck@498 {
248 compatible = "ti,am3-dpll-no-gate-clock";
249 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
250 reg = <0x0498>, <0x0448>, <0x0454>;
253 dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
255 compatible = "ti,divider-clock";
256 clocks = <&dpll_disp_ck>;
259 ti,index-starts-at-one;
263 dpll_per_ck: dpll_per_ck@48c {
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
266 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
267 reg = <0x048c>, <0x0470>, <0x049c>;
270 dpll_per_m2_ck: dpll_per_m2_ck@4ac {
272 compatible = "ti,divider-clock";
273 clocks = <&dpll_per_ck>;
276 ti,index-starts-at-one;
279 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
281 compatible = "fixed-factor-clock";
282 clocks = <&dpll_per_m2_ck>;
287 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
289 compatible = "fixed-factor-clock";
290 clocks = <&dpll_per_m2_ck>;
295 clk_24mhz: clk_24mhz {
297 compatible = "fixed-factor-clock";
298 clocks = <&dpll_per_m2_ck>;
303 clkdiv32k_ck: clkdiv32k_ck {
305 compatible = "fixed-factor-clock";
306 clocks = <&clk_24mhz>;
313 compatible = "fixed-factor-clock";
314 clocks = <&dpll_core_m4_ck>;
319 pruss_ocp_gclk: pruss_ocp_gclk@530 {
321 compatible = "ti,mux-clock";
322 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
326 mmu_fck: mmu_fck@914 {
328 compatible = "ti,gate-clock";
329 clocks = <&dpll_core_m4_ck>;
334 timer1_fck: timer1_fck@528 {
336 compatible = "ti,mux-clock";
337 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
341 timer2_fck: timer2_fck@508 {
343 compatible = "ti,mux-clock";
344 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
348 timer3_fck: timer3_fck@50c {
350 compatible = "ti,mux-clock";
351 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
355 timer4_fck: timer4_fck@510 {
357 compatible = "ti,mux-clock";
358 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
362 timer5_fck: timer5_fck@518 {
364 compatible = "ti,mux-clock";
365 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
369 timer6_fck: timer6_fck@51c {
371 compatible = "ti,mux-clock";
372 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
376 timer7_fck: timer7_fck@504 {
378 compatible = "ti,mux-clock";
379 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
383 usbotg_fck: usbotg_fck@47c {
385 compatible = "ti,gate-clock";
386 clocks = <&dpll_per_ck>;
391 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
393 compatible = "fixed-factor-clock";
394 clocks = <&dpll_core_m4_ck>;
399 ieee5000_fck: ieee5000_fck@e4 {
401 compatible = "ti,gate-clock";
402 clocks = <&dpll_core_m4_div2_ck>;
407 wdt1_fck: wdt1_fck@538 {
409 compatible = "ti,mux-clock";
410 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
414 l4_rtc_gclk: l4_rtc_gclk {
416 compatible = "fixed-factor-clock";
417 clocks = <&dpll_core_m4_ck>;
422 l4hs_gclk: l4hs_gclk {
424 compatible = "fixed-factor-clock";
425 clocks = <&dpll_core_m4_ck>;
432 compatible = "fixed-factor-clock";
433 clocks = <&dpll_core_m4_div2_ck>;
438 l4fw_gclk: l4fw_gclk {
440 compatible = "fixed-factor-clock";
441 clocks = <&dpll_core_m4_div2_ck>;
446 l4ls_gclk: l4ls_gclk {
448 compatible = "fixed-factor-clock";
449 clocks = <&dpll_core_m4_div2_ck>;
454 sysclk_div_ck: sysclk_div_ck {
456 compatible = "fixed-factor-clock";
457 clocks = <&dpll_core_m4_ck>;
462 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
464 compatible = "fixed-factor-clock";
465 clocks = <&dpll_core_m5_ck>;
470 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
472 compatible = "ti,mux-clock";
473 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
477 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
479 compatible = "ti,mux-clock";
480 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
484 lcd_gclk: lcd_gclk@534 {
486 compatible = "ti,mux-clock";
487 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
494 compatible = "fixed-factor-clock";
495 clocks = <&dpll_per_m2_ck>;
500 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
502 compatible = "ti,mux-clock";
503 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
508 gfx_fck_div_ck: gfx_fck_div_ck@52c {
510 compatible = "ti,divider-clock";
511 clocks = <&gfx_fclk_clksel_ck>;
516 sysclkout_pre_ck: sysclkout_pre_ck@700 {
518 compatible = "ti,mux-clock";
519 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
523 clkout2_div_ck: clkout2_div_ck@700 {
525 compatible = "ti,divider-clock";
526 clocks = <&sysclkout_pre_ck>;
532 clkout2_ck: clkout2_ck@700 {
534 compatible = "ti,gate-clock";
535 clocks = <&clkout2_div_ck>;
543 compatible = "ti,omap4-cm";
545 #address-cells = <1>;
547 ranges = <0 0x0 0x400>;
549 l4ls_clkctrl: l4ls-clkctrl@38 {
550 compatible = "ti,clkctrl";
551 reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
555 l3s_clkctrl: l3s-clkctrl@1c {
556 compatible = "ti,clkctrl";
557 reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
561 l3_clkctrl: l3-clkctrl@24 {
562 compatible = "ti,clkctrl";
563 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
567 l4hs_clkctrl: l4hs-clkctrl@120 {
568 compatible = "ti,clkctrl";
573 pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
574 compatible = "ti,clkctrl";
579 cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
580 compatible = "ti,clkctrl";
585 lcdc_clkctrl: lcdc-clkctrl@18 {
586 compatible = "ti,clkctrl";
591 clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
592 compatible = "ti,clkctrl";
598 wkup_cm: wkup-cm@400 {
599 compatible = "ti,omap4-cm";
601 #address-cells = <1>;
603 ranges = <0 0x400 0x100>;
605 l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
606 compatible = "ti,clkctrl";
607 reg = <0x0 0x10>, <0xb4 0x24>;
611 l3_aon_clkctrl: l3-aon-clkctrl@14 {
612 compatible = "ti,clkctrl";
617 l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
618 compatible = "ti,clkctrl";
625 compatible = "ti,omap4-cm";
627 #address-cells = <1>;
629 ranges = <0 0x600 0x100>;
631 mpu_clkctrl: mpu-clkctrl@0 {
632 compatible = "ti,clkctrl";
638 l4_rtc_cm: l4-rtc-cm@800 {
639 compatible = "ti,omap4-cm";
641 #address-cells = <1>;
643 ranges = <0 0x800 0x100>;
645 l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
646 compatible = "ti,clkctrl";
652 gfx_l3_cm: gfx-l3-cm@900 {
653 compatible = "ti,omap4-cm";
655 #address-cells = <1>;
657 ranges = <0 0x900 0x100>;
659 gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
660 compatible = "ti,clkctrl";
666 l4_cefuse_cm: l4-cefuse-cm@a00 {
667 compatible = "ti,omap4-cm";
669 #address-cells = <1>;
671 ranges = <0 0xa00 0x100>;
673 l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
674 compatible = "ti,clkctrl";