1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
8 model = "Phytec AM335x phyBOARD-WEGA";
9 compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
12 compatible = "ti,da830-evm-audio";
16 compatible = "simple-bus";
18 vcc3v3: fixedregulator1 {
19 compatible = "regulator-fixed";
20 regulator-name = "vcc3v3";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
30 mcasp0_pins: pinmux_mcasp0 {
31 pinctrl-single,pins = <
32 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
33 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
34 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
35 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
36 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
42 tlv320aic3007: tlv320aic3007@18 {
43 compatible = "ti,tlv320aic3007";
45 AVDD-supply = <&vcc3v3>;
46 IOVDD-supply = <&vcc3v3>;
47 DRVDD-supply = <&vcc3v3>;
48 DVDD-supply = <&vdig1_reg>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&mcasp0_pins>;
56 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
59 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
67 ti,model = "AM335x-Wega";
68 ti,audio-codec = <&tlv320aic3007>;
69 ti,mcasp-controller = <&mcasp0>;
75 clocks = <&mcasp0_fck>;
82 dcan1_pins: pinmux_dcan1 {
83 pinctrl-single,pins = <
84 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
85 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
91 pinctrl-names = "default";
92 pinctrl-0 = <&dcan1_pins>;
98 ethernet1_pins: pinmux_ethernet1 {
99 pinctrl-single,pins = <
100 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
101 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
102 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
103 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
104 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
105 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
106 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
107 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
108 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
109 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
110 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
111 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
112 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
113 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
119 phy-handle = <&phy1>;
121 dual_emac_res_vlan = <2>;
125 phy1: ethernet-phy@1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <ðernet0_pins ðernet1_pins>;
139 mmc1_pins: pinmux_mmc1 {
140 pinctrl-single,pins = <
141 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
142 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
143 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
144 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
145 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
146 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
147 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
153 vmmc-supply = <&vcc3v3>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&mmc1_pins>;
157 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
169 uart0_pins: pinmux_uart0 {
170 pinctrl-single,pins = <
171 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
172 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
176 uart1_pins: pinmux_uart1_pins {
177 pinctrl-single,pins = <
178 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
179 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
180 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
181 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
187 pinctrl-names = "default";
188 pinctrl-0 = <&uart0_pins>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart1_pins>;