Merge branch 'for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[linux-2.6-microblaze.git] / arch / arm / boot / dts / am335x-wega.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015 Phytec Messtechnik GmbH
4  * Author: Teresa Remmet <t.remmet@phytec.de>
5  */
6
7 / {
8         model = "Phytec AM335x phyBOARD-WEGA";
9         compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
10
11         sound: sound_iface {
12                 compatible = "ti,da830-evm-audio";
13         };
14
15         vcc3v3: fixedregulator1 {
16                 compatible = "regulator-fixed";
17                 regulator-name = "vcc3v3";
18                 regulator-min-microvolt = <3300000>;
19                 regulator-max-microvolt = <3300000>;
20                 regulator-boot-on;
21         };
22 };
23
24 /* Audio */
25 &am33xx_pinmux {
26         mcasp0_pins: pinmux_mcasp0 {
27                 pinctrl-single,pins = <
28                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
29                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
30                         AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
31                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
32                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
33                 >;
34         };
35 };
36
37 &i2c0 {
38         tlv320aic3007: tlv320aic3007@18 {
39                 compatible = "ti,tlv320aic3007";
40                 reg = <0x18>;
41                 AVDD-supply = <&vcc3v3>;
42                 IOVDD-supply = <&vcc3v3>;
43                 DRVDD-supply = <&vcc3v3>;
44                 DVDD-supply = <&vdig1_reg>;
45                 status = "okay";
46         };
47 };
48
49 &mcasp0 {
50         pinctrl-names = "default";
51         pinctrl-0 = <&mcasp0_pins>;
52         op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
53         tdm-slots = <2>;
54         serial-dir = <
55                 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
56         >;
57         tx-num-evt = <16>;
58         rt-num-evt = <16>;
59         status = "okay";
60 };
61
62 &sound {
63         ti,model = "AM335x-Wega";
64         ti,audio-codec = <&tlv320aic3007>;
65         ti,mcasp-controller = <&mcasp0>;
66         ti,audio-routing =
67                 "Line Out",             "LLOUT",
68                 "Line Out",             "RLOUT",
69                 "LINE1L",               "Line In",
70                 "LINE1R",               "Line In";
71         clocks = <&mcasp0_fck>;
72         clock-names = "mclk";
73         status = "okay";
74 };
75
76 /* CAN Busses */
77 &am33xx_pinmux {
78         dcan1_pins: pinmux_dcan1 {
79                 pinctrl-single,pins = <
80                         AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
81                         AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
82                 >;
83         };
84 };
85
86 &dcan1 {
87         pinctrl-names = "default";
88         pinctrl-0 = <&dcan1_pins>;
89         status = "okay";
90 };
91
92 /* Ethernet */
93 &am33xx_pinmux {
94         ethernet1_pins: pinmux_ethernet1 {
95                 pinctrl-single,pins = <
96                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a0.mii2_txen */
97                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a1.mii2_rxdv */
98                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a2.mii2_txd3 */
99                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a3.mii2_txd2 */
100                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a4.mii2_txd1 */
101                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a5.mii2_txd0 */
102                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a6.mii2_txclk */
103                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a7.mii2_rxclk */
104                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a8.mii2_rxd3 */
105                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a9.mii2_rxd2 */
106                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a10.mii2_rxd1 */
107                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a11.mii2_rxd0 */
108                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_wpn.mii2_rxerr */
109                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* gpmc_ben1.mii2_col */
110                 >;
111         };
112 };
113
114 &cpsw_emac1 {
115         phy-handle = <&phy1>;
116         phy-mode = "mii";
117         dual_emac_res_vlan = <2>;
118 };
119
120 &davinci_mdio {
121         phy1: ethernet-phy@1 {
122                 reg = <1>;
123         };
124 };
125
126 &mac {
127         slaves = <2>;
128         pinctrl-names = "default";
129         pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
130         dual_emac = <1>;
131 };
132
133 /* MMC */
134 &am33xx_pinmux {
135         mmc1_pins: pinmux_mmc1 {
136                 pinctrl-single,pins = <
137                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
138                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
139                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
140                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
141                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
142                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
143                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
144                 >;
145         };
146 };
147
148 &mmc1 {
149         vmmc-supply = <&vcc3v3>;
150         bus-width = <4>;
151         pinctrl-names = "default";
152         pinctrl-0 = <&mmc1_pins>;
153         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
154         status = "okay";
155 };
156
157 /* Power */
158 &vdig1_reg {
159         regulator-boot-on;
160         regulator-always-on;
161 };
162
163 /* UARTs */
164 &am33xx_pinmux {
165         uart0_pins: pinmux_uart0 {
166                 pinctrl-single,pins = <
167                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
168                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
169                 >;
170         };
171
172         uart1_pins: pinmux_uart1_pins {
173                 pinctrl-single,pins = <
174                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
175                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
176                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
177                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
178                 >;
179         };
180 };
181
182 &uart0 {
183         pinctrl-names = "default";
184         pinctrl-0 = <&uart0_pins>;
185         status = "okay";
186 };
187
188 &uart1 {
189         pinctrl-names = "default";
190         pinctrl-0 = <&uart1_pins>;
191         status = "okay";
192 };
193
194 &usb1 {
195         dr_mode = "host";
196 };