arch/arm/boot/dts/am335x-myirtech-myc.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
   3
   4 /* Based on code by myc_c335x.dts, MYiRtech.com */
   5 /* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
   6
   7 /dts-v1/;
   8
   9 #include "am33xx.dtsi"
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/leds/common.h>
  13
  14 / {
  15         model = "MYIR MYC-AM335X";
  16         compatible = "myir,myc-am335x", "ti,am33xx";
  17
  18         cpus {
  19                 cpu@0 {
  20                         cpu0-supply = <&vdd_core>;
  21                         voltage-tolerance = <2>;
  22                 };
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x80000000 0x10000000>;
  28         };
  29
  30         clk32k: clk32k {
  31                 compatible = "fixed-clock";
  32                 clock-frequency = <32768>;
  33
  34                 #clock-cells = <0>;
  35         };
  36
  37         vdd_mod: vdd_mod_reg {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "vdd-mod";
  40                 regulator-always-on;
  41                 regulator-boot-on;
  42         };
  43
  44         vdd_core: vdd_core_reg {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "vdd-core";
  47                 regulator-always-on;
  48                 regulator-boot-on;
  49                 vin-supply = <&vdd_mod>;
  50         };
  51
  52         leds: leds {
  53                 compatible = "gpio-leds";
  54                 pinctrl-names = "default";
  55                 pinctrl-0 = <&led_mod_pins>;
  56
  57                 led_mod: led_mod {
  58                         label = "module:user";
  59                         gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
  60                         color = <LED_COLOR_ID_GREEN>;
  61                         default-state = "off";
  62                         panic-indicator;
  63                 };
  64         };
  65 };
  66
  67 &mac_sw {
  68         pinctrl-names = "default", "sleep";
  69         pinctrl-0 = <&eth_slave1_pins_default>;
  70         pinctrl-1 = <&eth_slave1_pins_sleep>;
  71         status = "okay";
  72 };
  73
  74 &cpsw_port1 {
  75         phy-handle = <&phy0>;
  76         phy-mode = "rgmii-id";
  77         ti,dual-emac-pvid = <1>;
  78 };
  79
  80 &cpsw_port2 {
  81         status = "disabled";
  82 };
  83
  84 &davinci_mdio_sw {
  85         pinctrl-names = "default", "sleep";
  86         pinctrl-0 = <&mdio_pins_default>;
  87         pinctrl-1 = <&mdio_pins_sleep>;
  88
  89         phy0: ethernet-phy@4 {
  90                 reg = <4>;
  91         };
  92 };
  93
  94 &elm {
  95         status = "okay";
  96 };
  97
  98 &gpmc {
  99         pinctrl-names = "default", "sleep";
 100         pinctrl-0 = <&nand_pins_default>;
 101         pinctrl-1 = <&nand_pins_sleep>;
 102         ranges = <0 0 0x8000000 0x1000000>;
 103         status = "okay";
 104
 105         nand0: nand@0,0 {
 106                 compatible = "ti,omap2-nand";
 107                 reg = <0 0 4>;
 108                 interrupt-parent = <&gpmc>;
 109                 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
 110                 nand-bus-width = <8>;
 111                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
 112                 gpmc,device-width = <1>;
 113                 gpmc,sync-clk-ps = <0>;
 114                 gpmc,cs-on-ns = <0>;
 115                 gpmc,cs-rd-off-ns = <44>;
 116                 gpmc,cs-wr-off-ns = <44>;
 117                 gpmc,adv-on-ns = <6>;
 118                 gpmc,adv-rd-off-ns = <34>;
 119                 gpmc,adv-wr-off-ns = <44>;
 120                 gpmc,we-on-ns = <0>;
 121                 gpmc,we-off-ns = <40>;
 122                 gpmc,oe-on-ns = <0>;
 123                 gpmc,oe-off-ns = <54>;
 124                 gpmc,access-ns = <64>;
 125                 gpmc,rd-cycle-ns = <82>;
 126                 gpmc,wr-cycle-ns = <82>;
 127                 gpmc,bus-turnaround-ns = <0>;
 128                 gpmc,cycle2cycle-delay-ns = <0>;
 129                 gpmc,clk-activation-ns = <0>;
 130                 gpmc,wr-access-ns = <40>;
 131                 gpmc,wr-data-mux-bus-ns = <0>;
 132                 ti,elm-id = <&elm>;
 133                 ti,nand-ecc-opt = "bch8";
 134         };
 135 };
 136
 137 &i2c0 {
 138         pinctrl-names = "default", "gpio", "sleep";
 139         pinctrl-0 = <&i2c0_pins_default>;
 140         pinctrl-1 = <&i2c0_pins_gpio>;
 141         pinctrl-2 = <&i2c0_pins_sleep>;
 142         clock-frequency = <400000>;
 143         scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 144         sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 145         status = "okay";
 146
 147         eeprom: eeprom@50 {
 148                 compatible = "atmel,24c32";
 149                 reg = <0x50>;
 150                 pagesize = <32>;
 151                 vcc-supply = <&vdd_mod>;
 152         };
 153 };
 154
 155 &rtc {
 156         clocks = <&clk32k>;
 157         clock-names = "ext-clk";
 158         system-power-controller;
 159 };
 160
 161 &am33xx_pinmux {
 162         mdio_pins_default: pinmux_mdio_pins_default {
 163                 pinctrl-single,pins = <
 164                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)    /* mdio_data */
 165                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)                    /* mdio_clk */
 166                 >;
 167         };
 168
 169         mdio_pins_sleep: pinmux_mdio_pins_sleep {
 170                 pinctrl-single,pins = <
 171                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 172                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 173                 >;
 174         };
 175
 176         eth_slave1_pins_default: pinmux_eth_slave1_pins_default {
 177                 pinctrl-single,pins = <
 178                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)           /* rgmii1_tctl */
 179                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)            /* rgmii1_rctl */
 180                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)            /* rgmii1_td3 */
 181                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)            /* rgmii1_td2 */
 182                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)            /* rgmii1_td1 */
 183                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)            /* rgmii1_td0 */
 184                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)          /* rgmii1_tclk */
 185                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)           /* rgmii1_rclk */
 186                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)             /* rgmii1_rd3 */
 187                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)             /* rgmii1_rd2 */
 188                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)             /* rgmii1_rd1 */
 189                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)             /* rgmii1_rd0 */
 190                 >;
 191         };
 192
 193         eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep {
 194                 pinctrl-single,pins = <
 195                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 196                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
 197                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 198                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 199                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 200                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 201                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 202                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 203                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 204                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 205                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 206                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 207                 >;
 208         };
 209
 210         i2c0_pins_default: pinmux_i2c0_pins_default {
 211                 pinctrl-single,pins = <
 212                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0)       /* I2C0_SDA */
 213                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0)       /* I2C0_SCL */
 214                 >;
 215         };
 216
 217         i2c0_pins_gpio: pinmux_i2c0_pins_gpio {
 218                 pinctrl-single,pins = <
 219                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7)                       /* gpio3[5] */
 220                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7)                       /* gpio3[6] */
 221                 >;
 222         };
 223
 224         i2c0_pins_sleep: pinmux_i2c0_pins_sleep {
 225                 pinctrl-single,pins = <
 226                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7)
 227                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7)
 228                 >;
 229         };
 230
 231         led_mod_pins: pinmux_led_mod_pins {
 232                 pinctrl-single,pins = <
 233                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)         /* gpio3[18] */
 234                 >;
 235         };
 236
 237         nand_pins_default: pinmux_nand_pins_default {
 238                 pinctrl-single,pins = <
 239                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad0 */
 240                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad1 */
 241                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad2 */
 242                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad3 */
 243                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad4 */
 244                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad5 */
 245                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad6 */
 246                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)                /* gpmc_ad7 */
 247                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)              /* gpmc_wait0 */
 248                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)                /* gpio0[31] */
 249                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)                     /* gpmc_csn0 */
 250                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)                 /* gpmc_advn_ale */
 251                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)                  /* gpmc_oen_ren */
 252                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)                      /* gpmc_wen */
 253                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)                 /* gpmc_be0n_cle */
 254                 >;
 255         };
 256
 257         nand_pins_sleep: pinmux_nand_pins_sleep {
 258                 pinctrl-single,pins = <
 259                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 260                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 261                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 262                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 263                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7)
 264                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7)
 265                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7)
 266                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7)
 267                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 268                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 269                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 270                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)
 271                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 272                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 273                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)
 274                 >;
 275         };
 276 };