1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/boot/compressed/head.S
5 * Copyright (C) 1996-2002 Russell King
6 * Copyright (C) 2004 Hyok S. Choi (MPU support)
8 #include <linux/linkage.h>
9 #include <asm/assembler.h>
12 #include "efi-header.S"
15 #define OF_DT_MAGIC 0xd00dfeed
17 #define OF_DT_MAGIC 0xedfe0dd0
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
26 * Note that these macros must not contain any code which is not
27 * 100% relocatable. Any attempt to do so will result in a crash.
28 * Please select one of the following when turning on debugging.
32 #if defined(CONFIG_DEBUG_ICEDCC)
34 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
35 .macro loadsp, rb, tmp1, tmp2
37 .macro writeb, ch, rb, tmp
38 mcr p14, 0, \ch, c0, c5, 0
40 #elif defined(CONFIG_CPU_XSCALE)
41 .macro loadsp, rb, tmp1, tmp2
43 .macro writeb, ch, rb, tmp
44 mcr p14, 0, \ch, c8, c0, 0
47 .macro loadsp, rb, tmp1, tmp2
49 .macro writeb, ch, rb, tmp
50 mcr p14, 0, \ch, c1, c0, 0
56 #include CONFIG_DEBUG_LL_INCLUDE
58 .macro writeb, ch, rb, tmp
59 #ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
62 waituarttxrdy \tmp, \rb
67 #if defined(CONFIG_ARCH_SA1100)
68 .macro loadsp, rb, tmp1, tmp2
69 mov \rb, #0x80000000 @ physical base address
70 #ifdef CONFIG_DEBUG_LL_SER3
71 add \rb, \rb, #0x00050000 @ Ser3
73 add \rb, \rb, #0x00010000 @ Ser1
77 .macro loadsp, rb, tmp1, tmp2
78 addruart \rb, \tmp1, \tmp2
96 * Debug kernel copy by printing the memory addresses involved
98 .macro dbgkc, begin, end, cbegin, cend
104 kphex \begin, 8 /* Start of compressed kernel */
108 kphex \end, 8 /* End of compressed kernel */
113 kphex \cbegin, 8 /* Start of kernel copy */
117 kphex \cend, 8 /* End of kernel copy */
123 * Debug print of the final appended DTB location
125 .macro dbgadtb, begin, size
133 kphex \begin, 8 /* Start of appended DTB */
138 kphex \size, 8 /* Size of appended DTB */
144 .macro enable_cp15_barriers, reg
145 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
146 tst \reg, #(1 << 5) @ CP15BEN bit set?
148 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
149 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
150 ARM( .inst 0xf57ff06f @ v7+ isb )
156 * The kernel build system appends the size of the
157 * decompressed kernel at the end of the compressed data
158 * in little-endian form.
160 .macro get_inflated_image_size, res:req, tmp1:req, tmp2:req
161 adr \res, .Linflated_image_size_offset
163 add \tmp1, \tmp1, \res @ address of inflated image size
165 ldrb \res, [\tmp1] @ get_unaligned_le32
166 ldrb \tmp2, [\tmp1, #1]
167 orr \res, \res, \tmp2, lsl #8
168 ldrb \tmp2, [\tmp1, #2]
169 ldrb \tmp1, [\tmp1, #3]
170 orr \res, \res, \tmp2, lsl #16
171 orr \res, \res, \tmp1, lsl #24
174 .macro be32tocpu, val, tmp
176 /* convert to little endian */
181 .section ".start", "ax"
183 * sort out different calling conventions
187 * Always enter in ARM state for CPUs that support the ARM ISA.
188 * As of today (2014) that's exactly the members of the A and R
193 .type start,#function
195 * These 7 nops along with the 1 nop immediately below for
196 * !THUMB2 form 8 nops that make the compressed kernel bootable
197 * on legacy ARM systems that were assuming the kernel in a.out
198 * binary format. The boot loaders on these systems would
199 * jump 32 bytes into the image to skip the a.out header.
200 * with these 8 nops filling exactly 32 bytes, things still
201 * work as expected on these legacy systems. Thumb2 mode keeps
202 * 7 of the nops as it turns out that some boot loaders
203 * were patching the initial instructions of the kernel, i.e
204 * had started to exploit this "patch area".
209 #ifndef CONFIG_THUMB2_KERNEL
212 AR_CLASS( sub pc, pc, #3 ) @ A/R: switch to Thumb2 mode
213 M_CLASS( nop.w ) @ M: already in Thumb2 mode
218 .word _magic_sig @ Magic numbers to help the loader
219 .word _magic_start @ absolute load/run zImage address
220 .word _magic_end @ zImage end address
221 .word 0x04030201 @ endianness flag
222 .word 0x45454545 @ another magic number to indicate
223 .word _magic_table @ additional data table
227 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
228 AR_CLASS( mrs r9, cpsr )
229 #ifdef CONFIG_ARM_VIRT_EXT
230 bl __hyp_stub_install @ get into SVC mode, reversibly
232 mov r7, r1 @ save architecture ID
233 mov r8, r2 @ save atags pointer
235 #ifndef CONFIG_CPU_V7M
237 * Booting from Angel - need to enter SVC mode and disable
238 * FIQs/IRQs (numeric definitions from angel arm.h source).
239 * We only do this if we were in user mode on entry.
241 mrs r2, cpsr @ get current mode
242 tst r2, #3 @ not user?
244 mov r0, #0x17 @ angel_SWIreason_EnterSVC
245 ARM( swi 0x123456 ) @ angel_SWI_ARM
246 THUMB( svc 0xab ) @ angel_SWI_THUMB
248 safe_svcmode_maskall r0
249 msr spsr_cxsf, r9 @ Save the CPU boot mode in
253 * Note that some cache flushing and other stuff may
254 * be needed here - is there an Angel SWI call for this?
258 * some architecture specific code can be inserted
259 * by the linker here, but it should preserve r7, r8, and r9.
264 #ifdef CONFIG_AUTO_ZRELADDR
266 * Find the start of physical memory. As we are executing
267 * without the MMU on, we are in the physical address space.
268 * We just need to get rid of any offset by aligning the
271 * This alignment is a balance between the requirements of
272 * different platforms - we have chosen 128MB to allow
273 * platforms which align the start of their physical memory
274 * to 128MB to use this feature, while allowing the zImage
275 * to be placed within the first 128MB of memory on other
276 * platforms. Increasing the alignment means we place
277 * stricter alignment requirements on the start of physical
278 * memory, but relaxing it means that we break people who
279 * are already placing their zImage in (eg) the top 64MB
283 and r0, r0, #0xf8000000
286 #ifdef CONFIG_ARM_APPENDED_DTB
288 * Look for an appended DTB. If found, we cannot use it to
289 * validate the calculated start of physical memory, as its
290 * memory nodes may need to be augmented by ATAGS stored at
291 * an offset from the same start of physical memory.
293 ldr r2, [r1, #4] @ get &_edata
294 add r2, r2, r1 @ relocate it
295 ldr r2, [r2] @ get DTB signature
297 cmp r2, r3 @ do we have a DTB there?
298 beq 1f @ if yes, skip validation
299 #endif /* CONFIG_ARM_APPENDED_DTB */
302 * Make sure we have some stack before calling C code.
303 * No GOT fixup has occurred yet, but none of the code we're
304 * about to call uses any global variables.
306 ldr sp, [r1] @ get stack location
307 add sp, sp, r1 @ apply relocation
309 /* Validate calculated start against passed DTB */
311 bl fdt_check_mem_start
313 #endif /* CONFIG_USE_OF */
314 /* Determine final kernel image address. */
315 add r4, r0, #TEXT_OFFSET
321 * Set up a page table only if it won't overwrite ourself.
322 * That means r4 < pc || r4 - 16k page directory > &_end.
323 * Given that r4 > &_end is most unfrequent, we add a rough
324 * additional 1MB of room for a possible appended DTB.
331 orrcc r4, r4, #1 @ remember we skipped cache_on
340 get_inflated_image_size r9, r10, lr
342 #ifndef CONFIG_ZBOOT_ROM
343 /* malloc space is above the relocated stack (64k max) */
344 add r10, sp, #MALLOC_SIZE
347 * With ZBOOT_ROM the bss/stack is non relocatable,
348 * but someone could still run this code from RAM,
349 * in which case our reference is _edata.
354 mov r5, #0 @ init dtb size to 0
355 #ifdef CONFIG_ARM_APPENDED_DTB
357 * r4 = final kernel address (possibly with LSB set)
358 * r5 = appended dtb size (still unknown)
360 * r7 = architecture ID
361 * r8 = atags/device tree pointer
362 * r9 = size of decompressed image
363 * r10 = end of this image, including bss/stack/malloc space if non XIP
366 * if there are device trees (dtb) appended to zImage, advance r10 so that the
367 * dtb data will get relocated along with the kernel if necessary.
373 bne dtb_check_done @ not found
375 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
377 * OK... Let's do some funky business here.
378 * If we do have a DTB appended to zImage, and we do have
379 * an ATAG list around, we want the later to be translated
380 * and folded into the former here. No GOT fixup has occurred
381 * yet, but none of the code we're about to call uses any
385 /* Get the initial DTB size */
389 /* 50% DTB growth should be good enough */
390 add r5, r5, r5, lsr #1
391 /* preserve 64-bit alignment */
394 /* clamp to 32KB min and 1MB max */
399 /* temporarily relocate the stack past the DTB work space */
408 * If returned value is 1, there is no ATAG at the location
409 * pointed by r8. Try the typical 0x100 offset from start
410 * of RAM and hope for the best.
413 sub r0, r4, #TEXT_OFFSET
423 mov r8, r6 @ use the appended device tree
426 * Make sure that the DTB doesn't end up in the final
427 * kernel's .bss area. To do so, we adjust the decompressed
428 * kernel size to compensate if that .bss size is larger
429 * than the relocated code.
431 ldr r5, =_kernel_bss_size
432 adr r1, wont_overwrite
437 /* Get the current DTB size */
441 /* preserve 64-bit alignment */
445 /* relocate some pointers past the appended dtb */
453 * Check to see if we will overwrite ourselves.
454 * r4 = final kernel address (possibly with LSB set)
455 * r9 = size of decompressed image
456 * r10 = end of this image, including bss/stack/malloc space if non XIP
458 * r4 - 16k page directory >= r10 -> OK
459 * r4 + image length <= address of wont_overwrite -> OK
460 * Note: the possible LSB in r4 is harmless here.
466 adr r9, wont_overwrite
471 * Relocate ourselves past the end of the decompressed kernel.
473 * r10 = end of the decompressed kernel
474 * Because we always copy ahead, we need to do it from the end and go
475 * backward in case the source and destination overlap.
478 * Bump to the next 256-byte boundary with the size of
479 * the relocation code added. This avoids overwriting
480 * ourself when the offset is small.
482 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
485 /* Get start of code we want to copy and align it down. */
489 /* Relocate the hyp vector base if necessary */
490 #ifdef CONFIG_ARM_VIRT_EXT
492 and r0, r0, #MODE_MASK
497 * Compute the address of the hyp vectors after relocation.
498 * Call __hyp_set_vectors with the new address so that we
499 * can HVC again after the copy.
501 adr_l r0, __hyp_stub_vectors
508 sub r9, r6, r5 @ size to copy
509 add r9, r9, #31 @ rounded up to a multiple
510 bic r9, r9, #31 @ ... of 32 bytes
518 * We are about to copy the kernel to a new memory area.
519 * The boundaries of the new memory area can be found in
520 * r10 and r9, whilst r5 and r6 contain the boundaries
521 * of the memory we are going to copy.
522 * Calling dbgkc will help with the printing of this
525 dbgkc r5, r6, r10, r9
528 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
530 stmdb r9!, {r0 - r3, r10 - r12, lr}
533 /* Preserve offset to relocated code. */
536 mov r0, r9 @ start of relocated zImage
537 add r1, sp, r6 @ end of relocated zImage
546 ldmia r0, {r1, r2, r3, r11, r12}
547 sub r0, r0, r1 @ calculate the delta offset
550 * If delta is zero, we are running at the address we were linked at.
554 * r4 = kernel execution address (possibly with LSB set)
555 * r5 = appended dtb size (0 if not present)
556 * r7 = architecture ID
568 #ifndef CONFIG_ZBOOT_ROM
570 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
571 * we need to fix up pointers into the BSS region.
572 * Note that the stack pointer has already been fixed up.
578 * Relocate all entries in the GOT table.
579 * Bump bss entries to _edata + dtb size
581 1: ldr r1, [r11, #0] @ relocate entries in the GOT
582 add r1, r1, r0 @ This fixes up C references
583 cmp r1, r2 @ if entry >= bss_start &&
584 cmphs r3, r1 @ bss_end > entry
585 addhi r1, r1, r5 @ entry += dtb size
586 str r1, [r11], #4 @ next entry
590 /* bump our bss pointers too */
597 * Relocate entries in the GOT table. We only relocate
598 * the entries that are outside the (relocated) BSS region.
600 1: ldr r1, [r11, #0] @ relocate entries in the GOT
601 cmp r1, r2 @ entry < bss_start ||
602 cmphs r3, r1 @ _end < entry
603 addlo r1, r1, r0 @ table. This fixes up the
604 str r1, [r11], #4 @ C references.
609 not_relocated: mov r0, #0
610 1: str r0, [r2], #4 @ clear bss
618 * Did we skip the cache setup earlier?
619 * That is indicated by the LSB in r4.
627 * The C runtime environment should now be setup sufficiently.
628 * Set up some pointers, and start decompressing.
629 * r4 = kernel execution address
630 * r7 = architecture ID
634 mov r1, sp @ malloc space above stack
635 add r2, sp, #MALLOC_SIZE @ 64k max
639 get_inflated_image_size r1, r2, r3
641 mov r0, r4 @ start of inflated image
642 add r1, r1, r0 @ end of inflated image
646 #ifdef CONFIG_ARM_VIRT_EXT
647 mrs r0, spsr @ Get saved CPU boot mode
648 and r0, r0, #MODE_MASK
649 cmp r0, #HYP_MODE @ if not booted in HYP mode...
650 bne __enter_kernel @ boot kernel directly
652 adr_l r0, __hyp_reentry_vectors
654 __HVC(0) @ otherwise bounce to hyp mode
656 b . @ should never be reached
664 .word __bss_start @ r2
666 .word _got_start @ r11
671 LC1: .word .L_user_stack_end - LC1 @ sp
672 .word _edata - LC1 @ r6
676 .word _end - restart + 16384 + 1024*1024
678 .Linflated_image_size_offset:
679 .long (input_data_end - 4) - .
681 #ifdef CONFIG_ARCH_RPC
683 params: ldr r0, =0x10000100 @ params_phys for RPC
690 * dcache_line_size - get the minimum D-cache line size from the CTR register
693 .macro dcache_line_size, reg, tmp
694 #ifdef CONFIG_CPU_V7M
695 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
696 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
699 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
702 and \tmp, \tmp, #0xf @ cache line size encoding
703 mov \reg, #4 @ bytes per word
704 mov \reg, \reg, lsl \tmp @ actual cache line size
708 * Turn on the cache. We need to setup some page tables so that we
709 * can have both the I and D caches on.
711 * We place the page tables 16k down from the kernel execution address,
712 * and we hope that nothing else is using it. If we're using it, we
716 * r4 = kernel execution address
717 * r7 = architecture number
720 * r0, r1, r2, r3, r9, r10, r12 corrupted
721 * This routine must preserve:
725 cache_on: mov r3, #8 @ cache_on function
729 * Initialize the highest priority protection region, PR7
730 * to cover all 32bit address and cacheable and bufferable.
732 __armv4_mpu_cache_on:
733 mov r0, #0x3f @ 4G, the whole
734 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
735 mcr p15, 0, r0, c6, c7, 1
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
747 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
749 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
750 mrc p15, 0, r0, c1, c0, 0 @ read control reg
751 @ ...I .... ..D. WC.M
752 orr r0, r0, #0x002d @ .... .... ..1. 11.1
753 orr r0, r0, #0x1000 @ ...1 .... .... ....
755 mcr p15, 0, r0, c1, c0, 0 @ write control reg
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
759 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
762 __armv3_mpu_cache_on:
763 mov r0, #0x3f @ 4G, the whole
764 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
767 mcr p15, 0, r0, c2, c0, 0 @ cache on
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
776 * ?? ARMv3 MMU does not allow reading the control register,
777 * does this really work on ARMv3 MPU?
779 mrc p15, 0, r0, c1, c0, 0 @ read control reg
780 @ .... .... .... WC.M
781 orr r0, r0, #0x000d @ .... .... .... 11.1
782 /* ?? this overwrites the value constructed above? */
784 mcr p15, 0, r0, c1, c0, 0 @ write control reg
786 /* ?? invalidate for the second time? */
787 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
790 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
796 __setup_mmu: sub r3, r4, #16384 @ Page directory size
797 bic r3, r3, #0xff @ Align the pointer
800 * Initialise the page tables, turning on the cacheable and bufferable
801 * bits for the RAM area only.
805 mov r9, r9, lsl #18 @ start of RAM
806 add r10, r9, #0x10000000 @ a reasonable RAM size
807 mov r1, #0x12 @ XN|U + section mapping
808 orr r1, r1, #3 << 10 @ AP=11
810 1: cmp r1, r9 @ if virt > start of RAM
811 cmphs r10, r1 @ && end of RAM > virt
812 bic r1, r1, #0x1c @ clear XN|U + C + B
813 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
814 orrhs r1, r1, r6 @ set RAM section settings
815 str r1, [r0], #4 @ 1:1 mapping
820 * If ever we are running from Flash, then we surely want the cache
821 * to be enabled also for our execution instance... We map 2MB of it
822 * so there is no map overlap problem for up to 1 MB compressed kernel.
823 * If the execution is in RAM then we would only be duplicating the above.
825 orr r1, r6, #0x04 @ ensure B is set for this
829 orr r1, r1, r2, lsl #20
830 add r0, r3, r2, lsl #2
837 @ Enable unaligned access on v6, to allow better code generation
838 @ for the decompressor C code:
839 __armv6_mmu_cache_on:
840 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
841 bic r0, r0, #2 @ A (no unaligned access fault)
842 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
843 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
844 b __armv4_mmu_cache_on
846 __arm926ejs_mmu_cache_on:
847 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
848 mov r0, #4 @ put dcache in WT mode
849 mcr p15, 7, r0, c15, c0, 0
852 __armv4_mmu_cache_on:
855 mov r6, #CB_BITS | 0x12 @ U
858 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
859 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
860 mrc p15, 0, r0, c1, c0, 0 @ read control reg
861 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
863 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
864 bl __common_mmu_cache_on
866 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
870 __armv7_mmu_cache_on:
871 enable_cp15_barriers r11
874 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
876 movne r6, #CB_BITS | 0x02 @ !XN
879 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
881 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
883 mrc p15, 0, r0, c1, c0, 0 @ read control reg
884 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
885 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
886 orr r0, r0, #0x003c @ write buffer
887 bic r0, r0, #2 @ A (no unaligned access fault)
888 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
889 @ (needed for ARM1176)
891 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
892 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
893 orrne r0, r0, #1 @ MMU enabled
894 movne r1, #0xfffffffd @ domain 0 = client
895 bic r6, r6, #1 << 31 @ 32-bit translation system
896 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
897 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
898 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
899 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
901 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c1, c0, 0 @ load control register
903 mrc p15, 0, r0, c1, c0, 0 @ and read it back
905 mcr p15, 0, r0, c7, c5, 4 @ ISB
910 mov r6, #CB_BITS | 0x12 @ U
913 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
914 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
915 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
916 mrc p15, 0, r0, c1, c0, 0 @ read control reg
917 orr r0, r0, #0x1000 @ I-cache enable
918 bl __common_mmu_cache_on
920 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
923 __common_mmu_cache_on:
924 #ifndef CONFIG_THUMB2_KERNEL
926 orr r0, r0, #0x000d @ Write buffer, mmu
929 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
930 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
932 .align 5 @ cache line aligned
933 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
934 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
935 sub pc, lr, r0, lsr #32 @ properly flush pipeline
938 #define PROC_ENTRY_SIZE (4*5)
941 * Here follow the relocatable cache support functions for the
942 * various processors. This is a generic hook for locating an
943 * entry and jumping to an instruction at the specified offset
944 * from the start of the block. Please note this is all position
954 call_cache_fn: adr r12, proc_types
955 #ifdef CONFIG_CPU_CP15
956 mrc p15, 0, r9, c0, c0 @ get processor ID
957 #elif defined(CONFIG_CPU_V7M)
959 * On v7-M the processor id is located in the V7M_SCB_CPUID
960 * register, but as cache handling is IMPLEMENTATION DEFINED on
961 * v7-M (if existant at all) we just return early here.
962 * If V7M_SCB_CPUID were used the cpu ID functions (i.e.
963 * __armv7_mmu_cache_{on,off,flush}) would be selected which
964 * use cp15 registers that are not implemented on v7-M.
968 ldr r9, =CONFIG_PROCESSOR_ID
970 1: ldr r1, [r12, #0] @ get value
971 ldr r2, [r12, #4] @ get mask
972 eor r1, r1, r9 @ (real ^ match)
974 ARM( addeq pc, r12, r3 ) @ call cache function
975 THUMB( addeq r12, r3 )
976 THUMB( moveq pc, r12 ) @ call cache function
977 add r12, r12, #PROC_ENTRY_SIZE
981 * Table for cache operations. This is basically:
984 * - 'cache on' method instruction
985 * - 'cache off' method instruction
986 * - 'cache flush' method instruction
988 * We match an entry using: ((real_id ^ match) & mask) == 0
990 * Writethrough caches generally only need 'on' and 'off'
991 * methods. Writeback caches _must_ have the flush method
995 .type proc_types,#object
997 .word 0x41000000 @ old ARM ID
1006 .word 0x41007000 @ ARM7/710
1015 .word 0x41807200 @ ARM720T (writethrough)
1017 W(b) __armv4_mmu_cache_on
1018 W(b) __armv4_mmu_cache_off
1022 .word 0x41007400 @ ARM74x
1024 W(b) __armv3_mpu_cache_on
1025 W(b) __armv3_mpu_cache_off
1026 W(b) __armv3_mpu_cache_flush
1028 .word 0x41009400 @ ARM94x
1030 W(b) __armv4_mpu_cache_on
1031 W(b) __armv4_mpu_cache_off
1032 W(b) __armv4_mpu_cache_flush
1034 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1036 W(b) __arm926ejs_mmu_cache_on
1037 W(b) __armv4_mmu_cache_off
1038 W(b) __armv5tej_mmu_cache_flush
1040 .word 0x00007000 @ ARM7 IDs
1049 @ Everything from here on will be the new ID system.
1051 .word 0x4401a100 @ sa110 / sa1100
1053 W(b) __armv4_mmu_cache_on
1054 W(b) __armv4_mmu_cache_off
1055 W(b) __armv4_mmu_cache_flush
1057 .word 0x6901b110 @ sa1110
1059 W(b) __armv4_mmu_cache_on
1060 W(b) __armv4_mmu_cache_off
1061 W(b) __armv4_mmu_cache_flush
1064 .word 0xffffff00 @ PXA9xx
1065 W(b) __armv4_mmu_cache_on
1066 W(b) __armv4_mmu_cache_off
1067 W(b) __armv4_mmu_cache_flush
1069 .word 0x56158000 @ PXA168
1071 W(b) __armv4_mmu_cache_on
1072 W(b) __armv4_mmu_cache_off
1073 W(b) __armv5tej_mmu_cache_flush
1075 .word 0x56050000 @ Feroceon
1077 W(b) __armv4_mmu_cache_on
1078 W(b) __armv4_mmu_cache_off
1079 W(b) __armv5tej_mmu_cache_flush
1081 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
1082 /* this conflicts with the standard ARMv5TE entry */
1083 .long 0x41009260 @ Old Feroceon
1085 b __armv4_mmu_cache_on
1086 b __armv4_mmu_cache_off
1087 b __armv5tej_mmu_cache_flush
1090 .word 0x66015261 @ FA526
1092 W(b) __fa526_cache_on
1093 W(b) __armv4_mmu_cache_off
1094 W(b) __fa526_cache_flush
1096 @ These match on the architecture ID
1098 .word 0x00020000 @ ARMv4T
1100 W(b) __armv4_mmu_cache_on
1101 W(b) __armv4_mmu_cache_off
1102 W(b) __armv4_mmu_cache_flush
1104 .word 0x00050000 @ ARMv5TE
1106 W(b) __armv4_mmu_cache_on
1107 W(b) __armv4_mmu_cache_off
1108 W(b) __armv4_mmu_cache_flush
1110 .word 0x00060000 @ ARMv5TEJ
1112 W(b) __armv4_mmu_cache_on
1113 W(b) __armv4_mmu_cache_off
1114 W(b) __armv5tej_mmu_cache_flush
1116 .word 0x0007b000 @ ARMv6
1118 W(b) __armv6_mmu_cache_on
1119 W(b) __armv4_mmu_cache_off
1120 W(b) __armv6_mmu_cache_flush
1122 .word 0x000f0000 @ new CPU Id
1124 W(b) __armv7_mmu_cache_on
1125 W(b) __armv7_mmu_cache_off
1126 W(b) __armv7_mmu_cache_flush
1128 .word 0 @ unrecognised type
1137 .size proc_types, . - proc_types
1140 * If you get a "non-constant expression in ".if" statement"
1141 * error from the assembler on this line, check that you have
1142 * not accidentally written a "b" instruction where you should
1143 * have written W(b).
1145 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1146 .error "The size of one or more proc_types entries is wrong."
1150 * Turn off the Cache and MMU. ARMv3 does not support
1151 * reading the control register, but ARMv4 does.
1154 * r0, r1, r2, r3, r9, r12 corrupted
1155 * This routine must preserve:
1159 cache_off: mov r3, #12 @ cache_off function
1162 __armv4_mpu_cache_off:
1163 mrc p15, 0, r0, c1, c0
1165 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1167 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1168 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1172 __armv3_mpu_cache_off:
1173 mrc p15, 0, r0, c1, c0
1175 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1177 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1180 __armv4_mmu_cache_off:
1182 mrc p15, 0, r0, c1, c0
1184 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1186 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1187 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1191 __armv7_mmu_cache_off:
1192 mrc p15, 0, r0, c1, c0
1198 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1201 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1203 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1204 mcr p15, 0, r0, c7, c10, 4 @ DSB
1205 mcr p15, 0, r0, c7, c5, 4 @ ISB
1209 * Clean and flush the cache to maintain consistency.
1212 * r0 = start address
1213 * r1 = end address (exclusive)
1215 * r1, r2, r3, r9, r10, r11, r12 corrupted
1216 * This routine must preserve:
1225 __armv4_mpu_cache_flush:
1230 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1231 mov r1, #7 << 5 @ 8 segments
1232 1: orr r3, r1, #63 << 26 @ 64 entries
1233 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1234 subs r3, r3, #1 << 26
1235 bcs 2b @ entries 63 to 0
1236 subs r1, r1, #1 << 5
1237 bcs 1b @ segments 7 to 0
1240 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1244 __fa526_cache_flush:
1248 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1249 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1250 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1253 __armv6_mmu_cache_flush:
1256 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1257 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1258 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1259 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1262 __armv7_mmu_cache_flush:
1263 enable_cp15_barriers r10
1266 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1267 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1270 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1273 dcache_line_size r1, r2 @ r1 := dcache min line size
1274 sub r2, r1, #1 @ r2 := line size mask
1275 bic r0, r0, r2 @ round down start to line size
1276 sub r11, r11, #1 @ end address is exclusive
1277 bic r11, r11, r2 @ round down end to line size
1278 0: cmp r0, r11 @ finished?
1280 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1284 mcr p15, 0, r10, c7, c10, 4 @ DSB
1285 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1286 mcr p15, 0, r10, c7, c10, 4 @ DSB
1287 mcr p15, 0, r10, c7, c5, 4 @ ISB
1290 __armv5tej_mmu_cache_flush:
1293 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1295 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1296 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1299 __armv4_mmu_cache_flush:
1302 mov r2, #64*1024 @ default: 32K dcache size (*2)
1303 mov r11, #32 @ default: 32 byte line size
1304 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1305 teq r3, r9 @ cache ID register present?
1310 mov r2, r2, lsl r1 @ base dcache size *2
1311 tst r3, #1 << 14 @ test M bit
1312 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1316 mov r11, r11, lsl r3 @ cache line size in bytes
1319 bic r1, r1, #63 @ align to longest cache line
1322 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1323 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1324 THUMB( add r1, r1, r11 )
1328 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1329 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1330 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1333 __armv3_mmu_cache_flush:
1334 __armv3_mpu_cache_flush:
1338 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1342 * Various debugging routines for printing hex characters and
1343 * memory, which again must be relocatable.
1347 .type phexbuf,#object
1349 .size phexbuf, . - phexbuf
1351 @ phex corrupts {r0, r1, r2, r3}
1352 phex: adr r3, phexbuf
1366 @ puts corrupts {r0, r1, r2, r3}
1367 puts: loadsp r3, r2, r1
1368 1: ldrb r2, [r0], #1
1371 2: writeb r2, r3, r1
1381 @ putc corrupts {r0, r1, r2, r3}
1388 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1389 memdump: mov r12, r0
1392 2: mov r0, r11, lsl #2
1400 ldr r0, [r12, r11, lsl #2]
1420 #ifdef CONFIG_ARM_VIRT_EXT
1422 __hyp_reentry_vectors:
1425 #ifdef CONFIG_EFI_STUB
1426 W(b) __enter_kernel_from_hyp @ hvc from HYP
1432 W(b) __enter_kernel @ hyp
1435 #endif /* CONFIG_ARM_VIRT_EXT */
1438 mov r0, #0 @ must be 0
1439 mov r1, r7 @ restore architecture number
1440 mov r2, r8 @ restore atags pointer
1441 ARM( mov pc, r4 ) @ call kernel
1442 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1443 THUMB( bx r4 ) @ entry point is always ARM for A/R classes
1447 #ifdef CONFIG_EFI_STUB
1448 __enter_kernel_from_hyp:
1449 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1450 bic r0, r0, #0x5 @ disable MMU and caches
1451 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1455 ENTRY(efi_enter_kernel)
1456 mov r4, r0 @ preserve image base
1457 mov r8, r1 @ preserve DT pointer
1459 adr_l r0, call_cache_fn
1460 adr r1, 0f @ clean the region of code we
1461 bl cache_clean_flush @ may run with the MMU off
1463 #ifdef CONFIG_ARM_VIRT_EXT
1465 @ The EFI spec does not support booting on ARM in HYP mode,
1466 @ since it mandates that the MMU and caches are on, with all
1467 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1469 @ While the EDK2 reference implementation adheres to this,
1470 @ U-Boot might decide to enter the EFI stub in HYP mode
1471 @ anyway, with the MMU and caches either on or off.
1473 mrs r0, cpsr @ get the current mode
1474 msr spsr_cxsf, r0 @ record boot mode
1475 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1479 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1480 tst r1, #0x1 @ MMU enabled at HYP?
1484 @ When running in HYP mode with the caches on, we're better
1485 @ off just carrying on using the cached 1:1 mapping that the
1486 @ firmware provided. Set up the HYP vectors so HVC instructions
1487 @ issued from HYP mode take us to the correct handler code. We
1488 @ will disable the MMU before jumping to the kernel proper.
1490 ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE
1491 THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE
1492 mcr p15, 4, r1, c1, c0, 0
1493 adr r0, __hyp_reentry_vectors
1494 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1499 @ When running in HYP mode with the caches off, we need to drop
1500 @ into SVC mode now, and let the decompressor set up its cached
1501 @ 1:1 mapping as usual.
1503 1: mov r9, r4 @ preserve image base
1504 bl __hyp_stub_install @ install HYP stub vectors
1505 safe_svcmode_maskall r1 @ drop to SVC mode
1506 msr spsr_cxsf, r0 @ record boot mode
1507 orr r4, r9, #1 @ restore image base and set LSB
1511 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1512 tst r0, #0x1 @ MMU enabled?
1513 orreq r4, r4, #1 @ set LSB if not
1516 mov r0, r8 @ DT start
1517 add r1, r8, r2 @ DT end
1518 bl cache_clean_flush
1520 adr r0, 0f @ switch to our stack
1524 mov r5, #0 @ appended DTB size
1525 mov r7, #0xFFFFFFFF @ machine ID
1527 ENDPROC(efi_enter_kernel)
1528 0: .long .L_user_stack_end - .
1532 .section ".stack", "aw", %nobits
1533 .L_user_stack: .space 4096