1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CURRENT_STACK_POINTER
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_KEEPINITRD
15 select ARCH_HAS_MEMBARRIER_SYNC_CORE
16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
24 select ARCH_HAS_SYNC_DMA_FOR_CPU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
32 select ARCH_MIGHT_HAVE_PC_PARPORT
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
37 select ARCH_USE_BUILTIN_BSWAP
38 select ARCH_USE_CMPXCHG_LOCKREF
39 select ARCH_USE_MEMTEST
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
41 select ARCH_WANT_GENERAL_HUGETLB
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select ARCH_WANT_LD_ORPHAN_WARN
44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
45 select BUILDTIME_TABLE_SORT if MMU
46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
47 select CLONE_BACKWARDS
48 select CPU_PM if SUSPEND || CPU_IDLE
49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
50 select DMA_DECLARE_COHERENT
51 select DMA_GLOBAL_POOL if !MMU
53 select DMA_NONCOHERENT_MMAP if MMU
55 select EDAC_ATOMIC_SCRUB
56 select GENERIC_ALLOCATOR
57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
60 select GENERIC_IRQ_IPI if SMP
61 select GENERIC_CPU_AUTOPROBE
62 select GENERIC_EARLY_IOREMAP
63 select GENERIC_IDLE_POLL_SETUP
64 select GENERIC_IRQ_MULTI_HANDLER
65 select GENERIC_IRQ_PROBE
66 select GENERIC_IRQ_SHOW
67 select GENERIC_IRQ_SHOW_LEVEL
68 select GENERIC_LIB_DEVMEM_IS_ALLOWED
69 select GENERIC_PCI_IOMAP
70 select GENERIC_SCHED_CLOCK
71 select GENERIC_SMP_IDLE_THREAD
72 select HARDIRQS_SW_RESEND
73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
80 select HAVE_ARCH_MMAP_RND_BITS if MMU
81 select HAVE_ARCH_PFN_VALID
82 select HAVE_ARCH_SECCOMP
83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
85 select HAVE_ARCH_TRACEHOOK
86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
87 select HAVE_ARM_SMCCC if CPU_V7
88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
89 select HAVE_CONTEXT_TRACKING_USER
90 select HAVE_C_RECORDMCOUNT
91 select HAVE_BUILDTIME_MCOUNT_SORT
92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
93 select HAVE_DMA_CONTIGUOUS if MMU
94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
97 select HAVE_EXIT_THREAD
98 select HAVE_FAST_GUP if ARM_LPAE
99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
100 select HAVE_FUNCTION_ERROR_INJECTION
101 select HAVE_FUNCTION_GRAPH_TRACER
102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
103 select HAVE_GCC_PLUGINS
104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
105 select HAVE_IRQ_TIME_ACCOUNTING
106 select HAVE_KERNEL_GZIP
107 select HAVE_KERNEL_LZ4
108 select HAVE_KERNEL_LZMA
109 select HAVE_KERNEL_LZO
110 select HAVE_KERNEL_XZ
111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
112 select HAVE_KRETPROBES if HAVE_KPROBES
113 select HAVE_MOD_ARCH_SPECIFIC
115 select HAVE_OPTPROBES if !THUMB2_KERNEL
116 select HAVE_PCI if MMU
117 select HAVE_PERF_EVENTS
118 select HAVE_PERF_REGS
119 select HAVE_PERF_USER_STACK_DUMP
120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
121 select HAVE_REGS_AND_STACK_ACCESS_API
123 select HAVE_STACKPROTECTOR
124 select HAVE_SYSCALL_TRACEPOINTS
126 select HAVE_VIRT_CPU_ACCOUNTING_GEN
127 select IRQ_FORCED_THREADING
128 select MODULES_USE_ELF_REL
129 select NEED_DMA_MAP_STATE
130 select OF_EARLY_FLATTREE if OF
132 select OLD_SIGSUSPEND3
133 select PCI_DOMAINS_GENERIC if PCI
134 select PCI_SYSCALL if PCI
135 select PERF_USE_VMALLOC
137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
138 select SYS_SUPPORTS_APM_EMULATION
139 select THREAD_INFO_IN_TASK
140 select TIMER_OF if OF
141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
144 # Above selects are sorted alphabetically; please add new ones
145 # according to that. Thanks.
147 The ARM series is a line of low-power-consumption RISC chip designs
148 licensed by ARM Ltd and targeted at embedded applications and
149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
150 manufactured, but legacy ARM-based PC hardware remains popular in
151 Europe. There is an ARM Linux project with a web page at
152 <http://www.arm.linux.org.uk/>.
154 config ARM_HAS_GROUP_RELOCS
156 depends on !LD_IS_LLD || LLD_VERSION >= 140000
157 depends on !COMPILE_TEST
159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
160 relocations, which have been around for a long time, but were not
161 supported in LLD until version 14. The combined range is -/+ 256 MiB,
162 which is usually sufficient, but not for allyesconfig, so we disable
163 this feature when doing compile testing.
165 config ARM_DMA_USE_IOMMU
167 select NEED_SG_DMA_LENGTH
171 config ARM_DMA_IOMMU_ALIGNMENT
172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
176 DMA mapping framework by default aligns all buffers to the smallest
177 PAGE_SIZE order which is greater than or equal to the requested buffer
178 size. This works well for buffers up to a few hundreds kilobytes, but
179 for larger buffers it just a waste of address space. Drivers which has
180 relatively small addressing window (like 64Mib) might run out of
181 virtual space with just a few allocations.
183 With this parameter you can specify the maximum PAGE_SIZE order for
184 DMA IOMMU buffers. Larger buffers will be aligned only to this
185 specified order. The order is expressed as a power of two multiplied
190 config SYS_SUPPORTS_APM_EMULATION
195 select GENERIC_ALLOCATOR
206 config STACKTRACE_SUPPORT
210 config LOCKDEP_SUPPORT
214 config ARCH_HAS_ILOG2_U32
217 config ARCH_HAS_ILOG2_U64
220 config ARCH_HAS_BANDGAP
223 config FIX_EARLYCON_MEM
226 config GENERIC_HWEIGHT
230 config GENERIC_CALIBRATE_DELAY
234 config ARCH_MAY_HAVE_PC_FDC
237 config ARCH_SUPPORTS_UPROBES
240 config GENERIC_ISA_DMA
249 config ARM_PATCH_PHYS_VIRT
250 bool "Patch physical to virtual translations at runtime" if EMBEDDED
254 Patch phys-to-virt and virt-to-phys translation functions at
255 boot and module load time according to the position of the
256 kernel in system memory.
258 This can only be used with non-XIP MMU kernels where the base
259 of physical memory is at a 2 MiB boundary.
261 Only disable this option if you know that you do not require
262 this feature (eg, building a kernel for a single machine) and
263 you need to shrink the kernel to the minimal size.
265 config NEED_MACH_IO_H
268 Select this when mach/io.h is required to provide special
269 definitions for this platform. The need for mach/io.h should
270 be avoided when possible.
272 config NEED_MACH_MEMORY_H
275 Select this when mach/memory.h is required to provide special
276 definitions for this platform. The need for mach/memory.h should
277 be avoided when possible.
280 hex "Physical address of main memory" if MMU
281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
282 default DRAM_BASE if !MMU
283 default 0x00000000 if ARCH_FOOTBRIDGE
284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
285 default 0x30000000 if ARCH_S3C24XX
286 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
287 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
290 Please provide the physical address corresponding to the
291 location of main memory in your system.
297 config PGTABLE_LEVELS
299 default 3 if ARM_LPAE
305 bool "MMU-based Paged Memory Management Support"
308 Select if you want MMU-based virtualised addressing space
309 support by paged memory management. If unsure, say 'Y'.
311 config ARM_SINGLE_ARMV7M
317 config ARCH_MMAP_RND_BITS_MIN
320 config ARCH_MMAP_RND_BITS_MAX
321 default 14 if PAGE_OFFSET=0x40000000
322 default 15 if PAGE_OFFSET=0x80000000
325 config ARCH_MULTIPLATFORM
326 bool "Require kernel to be portable to multiple machines" if EXPERT
327 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
330 In general, all Arm machines can be supported in a single
331 kernel image, covering either Armv4/v5 or Armv6/v7.
333 However, some configuration options require hardcoding machine
334 specific physical addresses or enable errata workarounds that may
335 break other machines.
337 Selecting N here allows using those options, including
338 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
340 menu "Platform selection"
343 comment "CPU Core family selection"
346 bool "ARMv4 based platforms (FA526, StrongARM)"
347 depends on !ARCH_MULTI_V6_V7
348 select ARCH_MULTI_V4_V5
349 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
351 config ARCH_MULTI_V4T
352 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
353 depends on !ARCH_MULTI_V6_V7
354 select ARCH_MULTI_V4_V5
355 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
356 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
357 CPU_ARM925T || CPU_ARM940T)
360 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
361 depends on !ARCH_MULTI_V6_V7
362 select ARCH_MULTI_V4_V5
363 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
364 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
365 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
367 config ARCH_MULTI_V4_V5
371 bool "ARMv6 based platforms (ARM11)"
372 select ARCH_MULTI_V6_V7
376 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
378 select ARCH_MULTI_V6_V7
382 config ARCH_MULTI_V6_V7
384 select MIGHT_HAVE_CACHE_L2X0
386 config ARCH_MULTI_CPU_AUTO
387 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
393 bool "Dummy Virtual Machine"
394 depends on ARCH_MULTI_V7
397 select ARM_GIC_V2M if PCI
399 select ARM_GIC_V3_ITS if PCI
401 select HAVE_ARM_ARCH_TIMER
404 bool "Airoha SoC Support"
405 depends on ARCH_MULTI_V7
410 select HAVE_ARM_ARCH_TIMER
412 Support for Airoha EN7523 SoCs
415 # This is sorted alphabetically by mach-* pathname. However, plat-*
416 # Kconfigs may be included either alphabetically (according to the
417 # plat- suffix) or along side the corresponding mach-* source.
419 source "arch/arm/mach-actions/Kconfig"
421 source "arch/arm/mach-alpine/Kconfig"
423 source "arch/arm/mach-artpec/Kconfig"
425 source "arch/arm/mach-asm9260/Kconfig"
427 source "arch/arm/mach-aspeed/Kconfig"
429 source "arch/arm/mach-at91/Kconfig"
431 source "arch/arm/mach-axxia/Kconfig"
433 source "arch/arm/mach-bcm/Kconfig"
435 source "arch/arm/mach-berlin/Kconfig"
437 source "arch/arm/mach-clps711x/Kconfig"
439 source "arch/arm/mach-cns3xxx/Kconfig"
441 source "arch/arm/mach-davinci/Kconfig"
443 source "arch/arm/mach-digicolor/Kconfig"
445 source "arch/arm/mach-dove/Kconfig"
447 source "arch/arm/mach-ep93xx/Kconfig"
449 source "arch/arm/mach-exynos/Kconfig"
451 source "arch/arm/mach-footbridge/Kconfig"
453 source "arch/arm/mach-gemini/Kconfig"
455 source "arch/arm/mach-highbank/Kconfig"
457 source "arch/arm/mach-hisi/Kconfig"
459 source "arch/arm/mach-hpe/Kconfig"
461 source "arch/arm/mach-imx/Kconfig"
463 source "arch/arm/mach-iop32x/Kconfig"
465 source "arch/arm/mach-ixp4xx/Kconfig"
467 source "arch/arm/mach-keystone/Kconfig"
469 source "arch/arm/mach-lpc32xx/Kconfig"
471 source "arch/arm/mach-mediatek/Kconfig"
473 source "arch/arm/mach-meson/Kconfig"
475 source "arch/arm/mach-milbeaut/Kconfig"
477 source "arch/arm/mach-mmp/Kconfig"
479 source "arch/arm/mach-moxart/Kconfig"
481 source "arch/arm/mach-mstar/Kconfig"
483 source "arch/arm/mach-mv78xx0/Kconfig"
485 source "arch/arm/mach-mvebu/Kconfig"
487 source "arch/arm/mach-mxs/Kconfig"
489 source "arch/arm/mach-nomadik/Kconfig"
491 source "arch/arm/mach-npcm/Kconfig"
493 source "arch/arm/mach-nspire/Kconfig"
495 source "arch/arm/mach-omap1/Kconfig"
497 source "arch/arm/mach-omap2/Kconfig"
499 source "arch/arm/mach-orion5x/Kconfig"
501 source "arch/arm/mach-oxnas/Kconfig"
503 source "arch/arm/mach-pxa/Kconfig"
505 source "arch/arm/mach-qcom/Kconfig"
507 source "arch/arm/mach-rda/Kconfig"
509 source "arch/arm/mach-realtek/Kconfig"
511 source "arch/arm/mach-rpc/Kconfig"
513 source "arch/arm/mach-rockchip/Kconfig"
515 source "arch/arm/mach-s3c/Kconfig"
517 source "arch/arm/mach-s5pv210/Kconfig"
519 source "arch/arm/mach-sa1100/Kconfig"
521 source "arch/arm/mach-shmobile/Kconfig"
523 source "arch/arm/mach-socfpga/Kconfig"
525 source "arch/arm/mach-spear/Kconfig"
527 source "arch/arm/mach-sti/Kconfig"
529 source "arch/arm/mach-stm32/Kconfig"
531 source "arch/arm/mach-sunplus/Kconfig"
533 source "arch/arm/mach-sunxi/Kconfig"
535 source "arch/arm/mach-tegra/Kconfig"
537 source "arch/arm/mach-uniphier/Kconfig"
539 source "arch/arm/mach-ux500/Kconfig"
541 source "arch/arm/mach-versatile/Kconfig"
543 source "arch/arm/mach-vt8500/Kconfig"
545 source "arch/arm/mach-zynq/Kconfig"
547 # ARMv7-M architecture
549 bool "NXP LPC18xx/LPC43xx"
550 depends on ARM_SINGLE_ARMV7M
551 select ARCH_HAS_RESET_CONTROLLER
553 select CLKSRC_LPC32XX
556 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
557 high performance microcontrollers.
560 bool "ARM MPS2 platform"
561 depends on ARM_SINGLE_ARMV7M
565 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
566 with a range of available cores like Cortex-M3/M4/M7.
568 Please, note that depends which Application Note is used memory map
569 for the platform may vary, so adjustment of RAM base might be needed.
571 # Definitions to make life easier
578 select GENERIC_IRQ_CHIP
581 config PLAT_ORION_LEGACY
585 config PLAT_VERSATILE
588 source "arch/arm/mm/Kconfig"
591 bool "Enable iWMMXt support"
592 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
593 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
595 Enable support for iWMMXt context switching at run time if
596 running on a CPU that supports it.
599 source "arch/arm/Kconfig-nommu"
602 config PJ4B_ERRATA_4742
603 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
604 depends on CPU_PJ4B && MACH_ARMADA_370
607 When coming out of either a Wait for Interrupt (WFI) or a Wait for
608 Event (WFE) IDLE states, a specific timing sensitivity exists between
609 the retiring WFI/WFE instructions and the newly issued subsequent
610 instructions. This sensitivity can result in a CPU hang scenario.
612 The software must insert either a Data Synchronization Barrier (DSB)
613 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
616 config ARM_ERRATA_326103
617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
620 Executing a SWP instruction to read-only memory does not set bit 11
621 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
622 treat the access as a read, preventing a COW from occurring and
623 causing the faulting task to livelock.
625 config ARM_ERRATA_411920
626 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
627 depends on CPU_V6 || CPU_V6K
629 Invalidation of the Instruction Cache operation can
630 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
631 It does not affect the MPCore. This option enables the ARM Ltd.
632 recommended workaround.
634 config ARM_ERRATA_430973
635 bool "ARM errata: Stale prediction on replaced interworking branch"
638 This option enables the workaround for the 430973 Cortex-A8
639 r1p* erratum. If a code sequence containing an ARM/Thumb
640 interworking branch is replaced with another code sequence at the
641 same virtual address, whether due to self-modifying code or virtual
642 to physical address re-mapping, Cortex-A8 does not recover from the
643 stale interworking branch prediction. This results in Cortex-A8
644 executing the new code sequence in the incorrect ARM or Thumb state.
645 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
646 and also flushes the branch target cache at every context switch.
647 Note that setting specific bits in the ACTLR register may not be
648 available in non-secure mode.
650 config ARM_ERRATA_458693
651 bool "ARM errata: Processor deadlock when a false hazard is created"
653 depends on !ARCH_MULTIPLATFORM
655 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
656 erratum. For very specific sequences of memory operations, it is
657 possible for a hazard condition intended for a cache line to instead
658 be incorrectly associated with a different cache line. This false
659 hazard might then cause a processor deadlock. The workaround enables
660 the L1 caching of the NEON accesses and disables the PLD instruction
661 in the ACTLR register. Note that setting specific bits in the ACTLR
662 register may not be available in non-secure mode.
664 config ARM_ERRATA_460075
665 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
667 depends on !ARCH_MULTIPLATFORM
669 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
670 erratum. Any asynchronous access to the L2 cache may encounter a
671 situation in which recent store transactions to the L2 cache are lost
672 and overwritten with stale memory contents from external memory. The
673 workaround disables the write-allocate mode for the L2 cache via the
674 ACTLR register. Note that setting specific bits in the ACTLR register
675 may not be available in non-secure mode.
677 config ARM_ERRATA_742230
678 bool "ARM errata: DMB operation may be faulty"
679 depends on CPU_V7 && SMP
680 depends on !ARCH_MULTIPLATFORM
682 This option enables the workaround for the 742230 Cortex-A9
683 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
684 between two write operations may not ensure the correct visibility
685 ordering of the two writes. This workaround sets a specific bit in
686 the diagnostic register of the Cortex-A9 which causes the DMB
687 instruction to behave as a DSB, ensuring the correct behaviour of
690 config ARM_ERRATA_742231
691 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
692 depends on CPU_V7 && SMP
693 depends on !ARCH_MULTIPLATFORM
695 This option enables the workaround for the 742231 Cortex-A9
696 (r2p0..r2p2) erratum. Under certain conditions, specific to the
697 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
698 accessing some data located in the same cache line, may get corrupted
699 data due to bad handling of the address hazard when the line gets
700 replaced from one of the CPUs at the same time as another CPU is
701 accessing it. This workaround sets specific bits in the diagnostic
702 register of the Cortex-A9 which reduces the linefill issuing
703 capabilities of the processor.
705 config ARM_ERRATA_643719
706 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
707 depends on CPU_V7 && SMP
710 This option enables the workaround for the 643719 Cortex-A9 (prior to
711 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
712 register returns zero when it should return one. The workaround
713 corrects this value, ensuring cache maintenance operations which use
714 it behave as intended and avoiding data corruption.
716 config ARM_ERRATA_720789
717 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
720 This option enables the workaround for the 720789 Cortex-A9 (prior to
721 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
722 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
723 As a consequence of this erratum, some TLB entries which should be
724 invalidated are not, resulting in an incoherency in the system page
725 tables. The workaround changes the TLB flushing routines to invalidate
726 entries regardless of the ASID.
728 config ARM_ERRATA_743622
729 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
731 depends on !ARCH_MULTIPLATFORM
733 This option enables the workaround for the 743622 Cortex-A9
734 (r2p*) erratum. Under very rare conditions, a faulty
735 optimisation in the Cortex-A9 Store Buffer may lead to data
736 corruption. This workaround sets a specific bit in the diagnostic
737 register of the Cortex-A9 which disables the Store Buffer
738 optimisation, preventing the defect from occurring. This has no
739 visible impact on the overall performance or power consumption of the
742 config ARM_ERRATA_751472
743 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
745 depends on !ARCH_MULTIPLATFORM
747 This option enables the workaround for the 751472 Cortex-A9 (prior
748 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
749 completion of a following broadcasted operation if the second
750 operation is received by a CPU before the ICIALLUIS has completed,
751 potentially leading to corrupted entries in the cache or TLB.
753 config ARM_ERRATA_754322
754 bool "ARM errata: possible faulty MMU translations following an ASID switch"
757 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
758 r3p*) erratum. A speculative memory access may cause a page table walk
759 which starts prior to an ASID switch but completes afterwards. This
760 can populate the micro-TLB with a stale entry which may be hit with
761 the new ASID. This workaround places two dsb instructions in the mm
762 switching code so that no page table walks can cross the ASID switch.
764 config ARM_ERRATA_754327
765 bool "ARM errata: no automatic Store Buffer drain"
766 depends on CPU_V7 && SMP
768 This option enables the workaround for the 754327 Cortex-A9 (prior to
769 r2p0) erratum. The Store Buffer does not have any automatic draining
770 mechanism and therefore a livelock may occur if an external agent
771 continuously polls a memory location waiting to observe an update.
772 This workaround defines cpu_relax() as smp_mb(), preventing correctly
773 written polling loops from denying visibility of updates to memory.
775 config ARM_ERRATA_364296
776 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
779 This options enables the workaround for the 364296 ARM1136
780 r0p2 erratum (possible cache data corruption with
781 hit-under-miss enabled). It sets the undocumented bit 31 in
782 the auxiliary control register and the FI bit in the control
783 register, thus disabling hit-under-miss without putting the
784 processor into full low interrupt latency mode. ARM11MPCore
787 config ARM_ERRATA_764369
788 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
789 depends on CPU_V7 && SMP
791 This option enables the workaround for erratum 764369
792 affecting Cortex-A9 MPCore with two or more processors (all
793 current revisions). Under certain timing circumstances, a data
794 cache line maintenance operation by MVA targeting an Inner
795 Shareable memory region may fail to proceed up to either the
796 Point of Coherency or to the Point of Unification of the
797 system. This workaround adds a DSB instruction before the
798 relevant cache maintenance functions and sets a specific bit
799 in the diagnostic control register of the SCU.
801 config ARM_ERRATA_764319
802 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
805 This option enables the workaround for the 764319 Cortex A-9 erratum.
806 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
807 unexpected Undefined Instruction exception when the DBGSWENABLE
808 external pin is set to 0, even when the CP14 accesses are performed
809 from a privileged mode. This work around catches the exception in a
810 way the kernel does not stop execution.
812 config ARM_ERRATA_775420
813 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
816 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
817 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
818 operation aborts with MMU exception, it might cause the processor
819 to deadlock. This workaround puts DSB before executing ISB if
820 an abort may occur on cache maintenance.
822 config ARM_ERRATA_798181
823 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
824 depends on CPU_V7 && SMP
826 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
827 adequately shooting down all use of the old entries. This
828 option enables the Linux kernel workaround for this erratum
829 which sends an IPI to the CPUs that are running the same ASID
830 as the one being invalidated.
832 config ARM_ERRATA_773022
833 bool "ARM errata: incorrect instructions may be executed from loop buffer"
836 This option enables the workaround for the 773022 Cortex-A15
837 (up to r0p4) erratum. In certain rare sequences of code, the
838 loop buffer may deliver incorrect instructions. This
839 workaround disables the loop buffer to avoid the erratum.
841 config ARM_ERRATA_818325_852422
842 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
845 This option enables the workaround for:
846 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
847 instruction might deadlock. Fixed in r0p1.
848 - Cortex-A12 852422: Execution of a sequence of instructions might
849 lead to either a data corruption or a CPU deadlock. Not fixed in
850 any Cortex-A12 cores yet.
851 This workaround for all both errata involves setting bit[12] of the
852 Feature Register. This bit disables an optimisation applied to a
853 sequence of 2 instructions that use opposing condition codes.
855 config ARM_ERRATA_821420
856 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
859 This option enables the workaround for the 821420 Cortex-A12
860 (all revs) erratum. In very rare timing conditions, a sequence
861 of VMOV to Core registers instructions, for which the second
862 one is in the shadow of a branch or abort, can lead to a
863 deadlock when the VMOV instructions are issued out-of-order.
865 config ARM_ERRATA_825619
866 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
869 This option enables the workaround for the 825619 Cortex-A12
870 (all revs) erratum. Within rare timing constraints, executing a
871 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
872 and Device/Strongly-Ordered loads and stores might cause deadlock
874 config ARM_ERRATA_857271
875 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
878 This option enables the workaround for the 857271 Cortex-A12
879 (all revs) erratum. Under very rare timing conditions, the CPU might
880 hang. The workaround is expected to have a < 1% performance impact.
882 config ARM_ERRATA_852421
883 bool "ARM errata: A17: DMB ST might fail to create order between stores"
886 This option enables the workaround for the 852421 Cortex-A17
887 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
888 execution of a DMB ST instruction might fail to properly order
889 stores from GroupA and stores from GroupB.
891 config ARM_ERRATA_852423
892 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
895 This option enables the workaround for:
896 - Cortex-A17 852423: Execution of a sequence of instructions might
897 lead to either a data corruption or a CPU deadlock. Not fixed in
898 any Cortex-A17 cores yet.
899 This is identical to Cortex-A12 erratum 852422. It is a separate
900 config option from the A12 erratum due to the way errata are checked
903 config ARM_ERRATA_857272
904 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
907 This option enables the workaround for the 857272 Cortex-A17 erratum.
908 This erratum is not known to be fixed in any A17 revision.
909 This is identical to Cortex-A12 erratum 857271. It is a separate
910 config option from the A12 erratum due to the way errata are checked
915 source "arch/arm/common/Kconfig"
922 Find out whether you have ISA slots on your motherboard. ISA is the
923 name of a bus system, i.e. the way the CPU talks to the other stuff
924 inside your box. Other bus systems are PCI, EISA, MicroChannel
925 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
926 newer boards don't support it. If you have ISA, say Y, otherwise N.
928 # Select ISA DMA interface
932 config PCI_NANOENGINE
933 bool "BSE nanoEngine PCI support"
934 depends on SA1100_NANOENGINE
936 Enable PCI on the BSE nanoEngine board.
938 config ARM_ERRATA_814220
939 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
942 The v7 ARM states that all cache and branch predictor maintenance
943 operations that do not specify an address execute, relative to
944 each other, in program order.
945 However, because of this erratum, an L2 set/way cache maintenance
946 operation can overtake an L1 set/way cache maintenance operation.
947 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
952 menu "Kernel Features"
957 This option should be selected by machines which have an SMP-
960 The only effect of this option is to make the SMP-related
961 options available to the user for configuration.
964 bool "Symmetric Multi-Processing"
965 depends on CPU_V6K || CPU_V7
967 depends on MMU || ARM_MPU
970 This enables support for systems with more than one CPU. If you have
971 a system with only one CPU, say N. If you have a system with more
974 If you say N here, the kernel will run on uni- and multiprocessor
975 machines, but will use only one CPU of a multiprocessor machine. If
976 you say Y here, the kernel will run on many, but not all,
977 uniprocessor machines. On a uniprocessor machine, the kernel
978 will run faster if you say N here.
980 See also <file:Documentation/x86/i386/IO-APIC.rst>,
981 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
982 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
984 If you don't know what to do here, say N.
987 bool "Allow booting SMP kernel on uniprocessor systems"
988 depends on SMP && MMU
991 SMP kernels contain instructions which fail on non-SMP processors.
992 Enabling this option allows the kernel to modify itself to make
993 these instructions safe. Disabling it allows about 1K of space
996 If you don't know what to do here, say Y.
999 config CURRENT_POINTER_IN_TPIDRURO
1001 depends on CPU_32v6K && !CPU_V6
1005 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1006 select HAVE_SOFTIRQ_ON_OWN_STACK
1008 config ARM_CPU_TOPOLOGY
1009 bool "Support cpu topology definition"
1010 depends on SMP && CPU_V7
1013 Support ARM cpu topology definition. The MPIDR register defines
1014 affinity between processors which is then used to describe the cpu
1015 topology of an ARM System.
1018 bool "Multi-core scheduler support"
1019 depends on ARM_CPU_TOPOLOGY
1021 Multi-core scheduler support improves the CPU scheduler's decision
1022 making when dealing with multi-core CPU chips at a cost of slightly
1023 increased overhead in some places. If unsure say N here.
1026 bool "SMT scheduler support"
1027 depends on ARM_CPU_TOPOLOGY
1029 Improves the CPU scheduler's decision making when dealing with
1030 MultiThreading at a cost of slightly increased overhead in some
1031 places. If unsure say N here.
1036 This option enables support for the ARM snoop control unit
1038 config HAVE_ARM_ARCH_TIMER
1039 bool "Architected timer support"
1041 select ARM_ARCH_TIMER
1043 This option enables support for the ARM architected timer
1048 This options enables support for the ARM timer and watchdog unit
1051 bool "Multi-Cluster Power Management"
1052 depends on CPU_V7 && SMP
1054 This option provides the common power management infrastructure
1055 for (multi-)cluster based systems, such as big.LITTLE based
1058 config MCPM_QUAD_CLUSTER
1062 To avoid wasting resources unnecessarily, MCPM only supports up
1063 to 2 clusters by default.
1064 Platforms with 3 or 4 clusters that use MCPM must select this
1065 option to allow the additional clusters to be managed.
1068 bool "big.LITTLE support (Experimental)"
1069 depends on CPU_V7 && SMP
1072 This option enables support selections for the big.LITTLE
1073 system architecture.
1076 bool "big.LITTLE switcher support"
1077 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1080 The big.LITTLE "switcher" provides the core functionality to
1081 transparently handle transition between a cluster of A15's
1082 and a cluster of A7's in a big.LITTLE system.
1084 config BL_SWITCHER_DUMMY_IF
1085 tristate "Simple big.LITTLE switcher user interface"
1086 depends on BL_SWITCHER && DEBUG_KERNEL
1088 This is a simple and dummy char dev interface to control
1089 the big.LITTLE switcher core code. It is meant for
1090 debugging purposes only.
1093 prompt "Memory split"
1097 Select the desired split between kernel and user memory.
1099 If you are not absolutely sure what you are doing, leave this
1103 bool "3G/1G user/kernel split"
1104 config VMSPLIT_3G_OPT
1105 depends on !ARM_LPAE
1106 bool "3G/1G user/kernel split (for full 1G low memory)"
1108 bool "2G/2G user/kernel split"
1110 bool "1G/3G user/kernel split"
1115 default PHYS_OFFSET if !MMU
1116 default 0x40000000 if VMSPLIT_1G
1117 default 0x80000000 if VMSPLIT_2G
1118 default 0xB0000000 if VMSPLIT_3G_OPT
1121 config KASAN_SHADOW_OFFSET
1124 default 0x1f000000 if PAGE_OFFSET=0x40000000
1125 default 0x5f000000 if PAGE_OFFSET=0x80000000
1126 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1127 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1131 int "Maximum number of CPUs (2-32)"
1132 range 2 16 if DEBUG_KMAP_LOCAL
1133 range 2 32 if !DEBUG_KMAP_LOCAL
1137 The maximum number of CPUs that the kernel can support.
1138 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1139 debugging is enabled, which uses half of the per-CPU fixmap
1140 slots as guard regions.
1143 bool "Support for hot-pluggable CPUs"
1145 select GENERIC_IRQ_MIGRATION
1147 Say Y here to experiment with turning CPUs off and on. CPUs
1148 can be controlled through /sys/devices/system/cpu.
1151 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1152 depends on HAVE_ARM_SMCCC
1155 Say Y here if you want Linux to communicate with system firmware
1156 implementing the PSCI specification for CPU-centric power
1157 management operations described in ARM document number ARM DEN
1158 0022A ("Power State Coordination Interface System Software on
1163 default 128 if SOC_AT91RM9200
1167 depends on HZ_FIXED = 0
1168 prompt "Timer frequency"
1192 default HZ_FIXED if HZ_FIXED != 0
1193 default 100 if HZ_100
1194 default 200 if HZ_200
1195 default 250 if HZ_250
1196 default 300 if HZ_300
1197 default 500 if HZ_500
1201 def_bool HIGH_RES_TIMERS
1203 config THUMB2_KERNEL
1204 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1205 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1206 default y if CPU_THUMBONLY
1209 By enabling this option, the kernel will be compiled in
1214 config ARM_PATCH_IDIV
1215 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1219 The ARM compiler inserts calls to __aeabi_idiv() and
1220 __aeabi_uidiv() when it needs to perform division on signed
1221 and unsigned integers. Some v7 CPUs have support for the sdiv
1222 and udiv instructions that can be used to implement those
1225 Enabling this option allows the kernel to modify itself to
1226 replace the first two instructions of these library functions
1227 with the sdiv or udiv plus "bx lr" instructions when the CPU
1228 it is running on supports them. Typically this will be faster
1229 and less power intensive than running the original library
1230 code to do integer division.
1233 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1234 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1235 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1237 This option allows for the kernel to be compiled using the latest
1238 ARM ABI (aka EABI). This is only useful if you are using a user
1239 space environment that is also compiled with EABI.
1241 Since there are major incompatibilities between the legacy ABI and
1242 EABI, especially with regard to structure member alignment, this
1243 option also changes the kernel syscall calling convention to
1244 disambiguate both ABIs and allow for backward compatibility support
1245 (selected with CONFIG_OABI_COMPAT).
1247 To use this you need GCC version 4.0.0 or later.
1250 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1251 depends on AEABI && !THUMB2_KERNEL
1253 This option preserves the old syscall interface along with the
1254 new (ARM EABI) one. It also provides a compatibility layer to
1255 intercept syscalls that have structure arguments which layout
1256 in memory differs between the legacy ABI and the new ARM EABI
1257 (only for non "thumb" binaries). This option adds a tiny
1258 overhead to all syscalls and produces a slightly larger kernel.
1260 The seccomp filter system will not be available when this is
1261 selected, since there is no way yet to sensibly distinguish
1262 between calling conventions during filtering.
1264 If you know you'll be using only pure EABI user space then you
1265 can say N here. If this option is not selected and you attempt
1266 to execute a legacy ABI binary then the result will be
1267 UNPREDICTABLE (in fact it can be predicted that it won't work
1268 at all). If in doubt say N.
1270 config ARCH_SELECT_MEMORY_MODEL
1273 config ARCH_FLATMEM_ENABLE
1274 def_bool !(ARCH_RPC || ARCH_SA1100)
1276 config ARCH_SPARSEMEM_ENABLE
1277 def_bool !ARCH_FOOTBRIDGE
1278 select SPARSEMEM_STATIC if SPARSEMEM
1281 bool "High Memory Support"
1284 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1286 The address space of ARM processors is only 4 Gigabytes large
1287 and it has to accommodate user address space, kernel address
1288 space as well as some memory mapped IO. That means that, if you
1289 have a large amount of physical memory and/or IO, not all of the
1290 memory can be "permanently mapped" by the kernel. The physical
1291 memory that is not permanently mapped is called "high memory".
1293 Depending on the selected kernel/user memory split, minimum
1294 vmalloc space and actual amount of RAM, you may not need this
1295 option which should result in a slightly faster kernel.
1300 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1304 The VM uses one page of physical memory for each page table.
1305 For systems with a lot of processes, this can use a lot of
1306 precious low memory, eventually leading to low memory being
1307 consumed by page tables. Setting this option will allow
1308 user-space 2nd level page tables to reside in high memory.
1310 config CPU_SW_DOMAIN_PAN
1311 bool "Enable use of CPU domains to implement privileged no-access"
1312 depends on MMU && !ARM_LPAE
1315 Increase kernel security by ensuring that normal kernel accesses
1316 are unable to access userspace addresses. This can help prevent
1317 use-after-free bugs becoming an exploitable privilege escalation
1318 by ensuring that magic values (such as LIST_POISON) will always
1319 fault when dereferenced.
1321 CPUs with low-vector mappings use a best-efforts implementation.
1322 Their lower 1MB needs to remain accessible for the vectors, but
1323 the remainder of userspace will become appropriately inaccessible.
1325 config HW_PERF_EVENTS
1329 config ARM_MODULE_PLTS
1330 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1332 select KASAN_VMALLOC if KASAN
1335 Allocate PLTs when loading modules so that jumps and calls whose
1336 targets are too far away for their relative offsets to be encoded
1337 in the instructions themselves can be bounced via veneers in the
1338 module's PLT. This allows modules to be allocated in the generic
1339 vmalloc area after the dedicated module memory area has been
1340 exhausted. The modules will use slightly more memory, but after
1341 rounding up to page size, the actual memory footprint is usually
1344 Disabling this is usually safe for small single-platform
1345 configurations. If unsure, say y.
1347 config ARCH_FORCE_MAX_ORDER
1348 int "Maximum zone order"
1349 default "12" if SOC_AM33XX
1350 default "9" if SA1111
1353 The kernel memory allocator divides physically contiguous memory
1354 blocks into "zones", where each zone is a power of two number of
1355 pages. This option selects the largest power of two that the kernel
1356 keeps in the memory allocator. If you need to allocate very large
1357 blocks of physically contiguous memory, then you may need to
1358 increase this value.
1360 This config option is actually maximum order plus one. For example,
1361 a value of 11 means that the largest free memory block is 2^10 pages.
1363 config ALIGNMENT_TRAP
1364 def_bool CPU_CP15_MMU
1365 select HAVE_PROC_CPU if PROC_FS
1367 ARM processors cannot fetch/store information which is not
1368 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1369 address divisible by 4. On 32-bit ARM processors, these non-aligned
1370 fetch/store instructions will be emulated in software if you say
1371 here, which has a severe performance impact. This is necessary for
1372 correct operation of some network protocols. With an IP-only
1373 configuration it is safe to say N, otherwise say Y.
1375 config UACCESS_WITH_MEMCPY
1376 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1378 default y if CPU_FEROCEON
1380 Implement faster copy_to_user and clear_user methods for CPU
1381 cores where a 8-word STM instruction give significantly higher
1382 memory write throughput than a sequence of individual 32bit stores.
1384 A possible side effect is a slight increase in scheduling latency
1385 between threads sharing the same address space if they invoke
1386 such copy operations with large buffers.
1388 However, if the CPU data cache is using a write-allocate mode,
1389 this option is unlikely to provide any performance gain.
1392 bool "Enable paravirtualization code"
1394 This changes the kernel so it can modify itself when it is run
1395 under a hypervisor, potentially improving performance significantly
1396 over full virtualization.
1398 config PARAVIRT_TIME_ACCOUNTING
1399 bool "Paravirtual steal time accounting"
1402 Select this option to enable fine granularity task steal time
1403 accounting. Time spent executing other tasks in parallel with
1404 the current vCPU is discounted from the vCPU power. To account for
1405 that, there can be a small performance impact.
1407 If in doubt, say N here.
1414 bool "Xen guest support on ARM"
1415 depends on ARM && AEABI && OF
1416 depends on CPU_V7 && !CPU_V6
1417 depends on !GENERIC_ATOMIC64
1419 select ARCH_DMA_ADDR_T_64BIT
1425 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1427 config CC_HAVE_STACKPROTECTOR_TLS
1428 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1430 config STACKPROTECTOR_PER_TASK
1431 bool "Use a unique stack canary value for each task"
1432 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1433 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1434 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1437 Due to the fact that GCC uses an ordinary symbol reference from
1438 which to load the value of the stack canary, this value can only
1439 change at reboot time on SMP systems, and all tasks running in the
1440 kernel's address space are forced to use the same canary value for
1441 the entire duration that the system is up.
1443 Enable this option to switch to a different method that uses a
1444 different canary value for each task.
1451 bool "Flattened Device Tree support"
1455 Include support for flattened device tree machine descriptions.
1458 bool "Support for the traditional ATAGS boot data passing"
1461 This is the traditional way of passing data to the kernel at boot
1462 time. If you are solely relying on the flattened device tree (or
1463 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1464 to remove ATAGS support from your kernel binary.
1466 config UNUSED_BOARD_FILES
1467 bool "Board support for machines without known users"
1470 Most ATAGS based board files are completely unused and are
1471 scheduled for removal in early 2023, and left out of kernels
1472 by default now. If you are using a board file that is marked
1473 as unused, turn on this option to build support into the kernel.
1475 To keep support for your individual board from being removed,
1476 send a reply to the email discussion at
1477 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
1479 config DEPRECATED_PARAM_STRUCT
1480 bool "Provide old way to pass kernel parameters"
1483 This was deprecated in 2001 and announced to live on for 5 years.
1484 Some old boot loaders still use this way.
1486 # Compressed boot loader in ROM. Yes, we really want to ask about
1487 # TEXT and BSS so we preserve their values in the config files.
1488 config ZBOOT_ROM_TEXT
1489 hex "Compressed ROM boot loader base address"
1492 The physical address at which the ROM-able zImage is to be
1493 placed in the target. Platforms which normally make use of
1494 ROM-able zImage formats normally set this to a suitable
1495 value in their defconfig file.
1497 If ZBOOT_ROM is not enabled, this has no effect.
1499 config ZBOOT_ROM_BSS
1500 hex "Compressed ROM boot loader BSS address"
1503 The base address of an area of read/write memory in the target
1504 for the ROM-able zImage which must be available while the
1505 decompressor is running. It must be large enough to hold the
1506 entire decompressed kernel plus an additional 128 KiB.
1507 Platforms which normally make use of ROM-able zImage formats
1508 normally set this to a suitable value in their defconfig file.
1510 If ZBOOT_ROM is not enabled, this has no effect.
1513 bool "Compressed boot loader in ROM/flash"
1514 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1515 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1517 Say Y here if you intend to execute your compressed kernel image
1518 (zImage) directly from ROM or flash. If unsure, say N.
1520 config ARM_APPENDED_DTB
1521 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1524 With this option, the boot code will look for a device tree binary
1525 (DTB) appended to zImage
1526 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1528 This is meant as a backward compatibility convenience for those
1529 systems with a bootloader that can't be upgraded to accommodate
1530 the documented boot protocol using a device tree.
1532 Beware that there is very little in terms of protection against
1533 this option being confused by leftover garbage in memory that might
1534 look like a DTB header after a reboot if no actual DTB is appended
1535 to zImage. Do not leave this option active in a production kernel
1536 if you don't intend to always append a DTB. Proper passing of the
1537 location into r2 of a bootloader provided DTB is always preferable
1540 config ARM_ATAG_DTB_COMPAT
1541 bool "Supplement the appended DTB with traditional ATAG information"
1542 depends on ARM_APPENDED_DTB
1544 Some old bootloaders can't be updated to a DTB capable one, yet
1545 they provide ATAGs with memory configuration, the ramdisk address,
1546 the kernel cmdline string, etc. Such information is dynamically
1547 provided by the bootloader and can't always be stored in a static
1548 DTB. To allow a device tree enabled kernel to be used with such
1549 bootloaders, this option allows zImage to extract the information
1550 from the ATAG list and store it at run time into the appended DTB.
1553 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1554 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1556 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1557 bool "Use bootloader kernel arguments if available"
1559 Uses the command-line options passed by the boot loader instead of
1560 the device tree bootargs property. If the boot loader doesn't provide
1561 any, the device tree bootargs property will be used.
1563 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1564 bool "Extend with bootloader kernel arguments"
1566 The command-line arguments provided by the boot loader will be
1567 appended to the the device tree bootargs property.
1572 string "Default kernel command string"
1575 On some architectures (e.g. CATS), there is currently no way
1576 for the boot loader to pass arguments to the kernel. For these
1577 architectures, you should supply some command-line options at build
1578 time by entering them here. As a minimum, you should specify the
1579 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1582 prompt "Kernel command line type" if CMDLINE != ""
1583 default CMDLINE_FROM_BOOTLOADER
1585 config CMDLINE_FROM_BOOTLOADER
1586 bool "Use bootloader kernel arguments if available"
1588 Uses the command-line options passed by the boot loader. If
1589 the boot loader doesn't provide any, the default kernel command
1590 string provided in CMDLINE will be used.
1592 config CMDLINE_EXTEND
1593 bool "Extend bootloader kernel arguments"
1595 The command-line arguments provided by the boot loader will be
1596 appended to the default kernel command string.
1598 config CMDLINE_FORCE
1599 bool "Always use the default kernel command string"
1601 Always use the default kernel command string, even if the boot
1602 loader passes other arguments to the kernel.
1603 This is useful if you cannot or don't want to change the
1604 command-line options your boot loader passes to the kernel.
1608 bool "Kernel Execute-In-Place from ROM"
1609 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1610 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1612 Execute-In-Place allows the kernel to run from non-volatile storage
1613 directly addressable by the CPU, such as NOR flash. This saves RAM
1614 space since the text section of the kernel is not loaded from flash
1615 to RAM. Read-write sections, such as the data section and stack,
1616 are still copied to RAM. The XIP kernel is not compressed since
1617 it has to run directly from flash, so it will take more space to
1618 store it. The flash address used to link the kernel object files,
1619 and for storing it, is configuration dependent. Therefore, if you
1620 say Y here, you must know the proper physical address where to
1621 store the kernel image depending on your own flash memory usage.
1623 Also note that the make target becomes "make xipImage" rather than
1624 "make zImage" or "make Image". The final kernel binary to put in
1625 ROM memory will be arch/arm/boot/xipImage.
1629 config XIP_PHYS_ADDR
1630 hex "XIP Kernel Physical Location"
1631 depends on XIP_KERNEL
1632 default "0x00080000"
1634 This is the physical address in your flash memory the kernel will
1635 be linked for and stored to. This address is dependent on your
1638 config XIP_DEFLATED_DATA
1639 bool "Store kernel .data section compressed in ROM"
1640 depends on XIP_KERNEL
1643 Before the kernel is actually executed, its .data section has to be
1644 copied to RAM from ROM. This option allows for storing that data
1645 in compressed form and decompressed to RAM rather than merely being
1646 copied, saving some precious ROM space. A possible drawback is a
1647 slightly longer boot delay.
1650 bool "Kexec system call (EXPERIMENTAL)"
1651 depends on (!SMP || PM_SLEEP_SMP)
1655 kexec is a system call that implements the ability to shutdown your
1656 current kernel, and to start another kernel. It is like a reboot
1657 but it is independent of the system firmware. And like a reboot
1658 you can start any kernel with it, not just Linux.
1660 It is an ongoing process to be certain the hardware in a machine
1661 is properly shutdown, so do not be surprised if this code does not
1662 initially work for you.
1665 bool "Export atags in procfs"
1666 depends on ATAGS && KEXEC
1669 Should the atags used to boot the kernel be exported in an "atags"
1670 file in procfs. Useful with kexec.
1673 bool "Build kdump crash kernel (EXPERIMENTAL)"
1675 Generate crash dump after being started by kexec. This should
1676 be normally only set in special crash dump kernels which are
1677 loaded in the main kernel with kexec-tools into a specially
1678 reserved region and then later executed after a crash by
1679 kdump/kexec. The crash dump kernel must be compiled to a
1680 memory address not used by the main kernel
1682 For more details see Documentation/admin-guide/kdump/kdump.rst
1684 config AUTO_ZRELADDR
1685 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1686 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1688 ZRELADDR is the physical address where the decompressed kernel
1689 image will be placed. If AUTO_ZRELADDR is selected, the address
1690 will be determined at run-time, either by masking the current IP
1691 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1692 This assumes the zImage being placed in the first 128MB from
1699 bool "UEFI runtime support"
1700 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1702 select EFI_PARAMS_FROM_FDT
1704 select EFI_GENERIC_STUB
1705 select EFI_RUNTIME_WRAPPERS
1707 This option provides support for runtime services provided
1708 by UEFI firmware (such as non-volatile variables, realtime
1709 clock, and platform reset). A UEFI stub is also provided to
1710 allow the kernel to be booted as an EFI application. This
1711 is only useful for kernels that may run on systems that have
1715 bool "Enable support for SMBIOS (DMI) tables"
1719 This enables SMBIOS/DMI feature for systems.
1721 This option is only useful on systems that have UEFI firmware.
1722 However, even with this option, the resultant kernel should
1723 continue to boot on existing non-UEFI platforms.
1725 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1726 i.e., the the practice of identifying the platform via DMI to
1727 decide whether certain workarounds for buggy hardware and/or
1728 firmware need to be enabled. This would require the DMI subsystem
1729 to be enabled much earlier than we do on ARM, which is non-trivial.
1733 menu "CPU Power Management"
1735 source "drivers/cpufreq/Kconfig"
1737 source "drivers/cpuidle/Kconfig"
1741 menu "Floating point emulation"
1743 comment "At least one emulation must be selected"
1746 bool "NWFPE math emulation"
1747 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1749 Say Y to include the NWFPE floating point emulator in the kernel.
1750 This is necessary to run most binaries. Linux does not currently
1751 support floating point hardware so you need to say Y here even if
1752 your machine has an FPA or floating point co-processor podule.
1754 You may say N here if you are going to load the Acorn FPEmulator
1755 early in the bootup.
1758 bool "Support extended precision"
1759 depends on FPE_NWFPE
1761 Say Y to include 80-bit support in the kernel floating-point
1762 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1763 Note that gcc does not generate 80-bit operations by default,
1764 so in most cases this option only enlarges the size of the
1765 floating point emulator without any good reason.
1767 You almost surely want to say N here.
1770 bool "FastFPE math emulation (EXPERIMENTAL)"
1771 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1773 Say Y here to include the FAST floating point emulator in the kernel.
1774 This is an experimental much faster emulator which now also has full
1775 precision for the mantissa. It does not support any exceptions.
1776 It is very simple, and approximately 3-6 times faster than NWFPE.
1778 It should be sufficient for most programs. It may be not suitable
1779 for scientific calculations, but you have to check this for yourself.
1780 If you do not feel you need a faster FP emulation you should better
1784 bool "VFP-format floating point maths"
1785 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1787 Say Y to include VFP support code in the kernel. This is needed
1788 if your hardware includes a VFP unit.
1790 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1791 release notes and additional status information.
1793 Say N if your target does not have VFP hardware.
1801 bool "Advanced SIMD (NEON) Extension support"
1802 depends on VFPv3 && CPU_V7
1804 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1807 config KERNEL_MODE_NEON
1808 bool "Support for NEON in kernel mode"
1809 depends on NEON && AEABI
1811 Say Y to include support for NEON in kernel mode.
1815 menu "Power management options"
1817 source "kernel/power/Kconfig"
1819 config ARCH_SUSPEND_POSSIBLE
1820 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1821 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1824 config ARM_CPU_SUSPEND
1825 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1826 depends on ARCH_SUSPEND_POSSIBLE
1828 config ARCH_HIBERNATION_POSSIBLE
1831 default y if ARCH_SUSPEND_POSSIBLE
1835 source "arch/arm/Kconfig.assembler"