1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
48 select DMA_REMAP if MMU
50 select EDAC_ATOMIC_SCRUB
51 select GENERIC_ALLOCATOR
52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
55 select GENERIC_IRQ_IPI if SMP
56 select GENERIC_CPU_AUTOPROBE
57 select GENERIC_EARLY_IOREMAP
58 select GENERIC_IDLE_POLL_SETUP
59 select GENERIC_IRQ_PROBE
60 select GENERIC_IRQ_SHOW
61 select GENERIC_IRQ_SHOW_LEVEL
62 select GENERIC_LIB_DEVMEM_IS_ALLOWED
63 select GENERIC_PCI_IOMAP
64 select GENERIC_SCHED_CLOCK
65 select GENERIC_SMP_IDLE_THREAD
66 select GENERIC_STRNCPY_FROM_USER
67 select GENERIC_STRNLEN_USER
68 select HANDLE_DOMAIN_IRQ
69 select HARDIRQS_SW_RESEND
70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
75 select HAVE_ARCH_MMAP_RND_BITS if MMU
76 select HAVE_ARCH_PFN_VALID
77 select HAVE_ARCH_SECCOMP
78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
80 select HAVE_ARCH_TRACEHOOK
81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
82 select HAVE_ARM_SMCCC if CPU_V7
83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
84 select HAVE_CONTEXT_TRACKING
85 select HAVE_C_RECORDMCOUNT
86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
87 select HAVE_DMA_CONTIGUOUS if MMU
88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
91 select HAVE_EXIT_THREAD
92 select HAVE_FAST_GUP if ARM_LPAE
93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
96 select HAVE_GCC_PLUGINS
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
98 select HAVE_IDE if PCI || ISA || PCMCIA
99 select HAVE_IRQ_TIME_ACCOUNTING
100 select HAVE_KERNEL_GZIP
101 select HAVE_KERNEL_LZ4
102 select HAVE_KERNEL_LZMA
103 select HAVE_KERNEL_LZO
104 select HAVE_KERNEL_XZ
105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
106 select HAVE_KRETPROBES if HAVE_KPROBES
107 select HAVE_MOD_ARCH_SPECIFIC
109 select HAVE_OPTPROBES if !THUMB2_KERNEL
110 select HAVE_PERF_EVENTS
111 select HAVE_PERF_REGS
112 select HAVE_PERF_USER_STACK_DUMP
113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
114 select HAVE_REGS_AND_STACK_ACCESS_API
116 select HAVE_STACKPROTECTOR
117 select HAVE_SYSCALL_TRACEPOINTS
119 select HAVE_VIRT_CPU_ACCOUNTING_GEN
120 select IRQ_FORCED_THREADING
121 select MODULES_USE_ELF_REL
122 select NEED_DMA_MAP_STATE
123 select OF_EARLY_FLATTREE if OF
125 select OLD_SIGSUSPEND3
126 select PCI_SYSCALL if PCI
127 select PERF_USE_VMALLOC
130 select SYS_SUPPORTS_APM_EMULATION
131 # Above selects are sorted alphabetically; please add new ones
132 # according to that. Thanks.
134 The ARM series is a line of low-power-consumption RISC chip designs
135 licensed by ARM Ltd and targeted at embedded applications and
136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
137 manufactured, but legacy ARM-based PC hardware remains popular in
138 Europe. There is an ARM Linux project with a web page at
139 <http://www.arm.linux.org.uk/>.
141 config ARM_HAS_SG_CHAIN
144 config ARM_DMA_USE_IOMMU
146 select ARM_HAS_SG_CHAIN
147 select NEED_SG_DMA_LENGTH
151 config ARM_DMA_IOMMU_ALIGNMENT
152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
156 DMA mapping framework by default aligns all buffers to the smallest
157 PAGE_SIZE order which is greater than or equal to the requested buffer
158 size. This works well for buffers up to a few hundreds kilobytes, but
159 for larger buffers it just a waste of address space. Drivers which has
160 relatively small addressing window (like 64Mib) might run out of
161 virtual space with just a few allocations.
163 With this parameter you can specify the maximum PAGE_SIZE order for
164 DMA IOMMU buffers. Larger buffers will be aligned only to this
165 specified order. The order is expressed as a power of two multiplied
170 config SYS_SUPPORTS_APM_EMULATION
175 select GENERIC_ALLOCATOR
186 config STACKTRACE_SUPPORT
190 config LOCKDEP_SUPPORT
194 config TRACE_IRQFLAGS_SUPPORT
198 config ARCH_HAS_ILOG2_U32
201 config ARCH_HAS_ILOG2_U64
204 config ARCH_HAS_BANDGAP
207 config FIX_EARLYCON_MEM
210 config GENERIC_HWEIGHT
214 config GENERIC_CALIBRATE_DELAY
218 config ARCH_MAY_HAVE_PC_FDC
224 config ARCH_SUPPORTS_UPROBES
227 config ARCH_HAS_DMA_SET_COHERENT_MASK
230 config GENERIC_ISA_DMA
236 config NEED_RET_TO_USER
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
247 Patch phys-to-virt and virt-to-phys translation functions at
248 boot and module load time according to the position of the
249 kernel in system memory.
251 This can only be used with non-XIP MMU kernels where the base
252 of physical memory is at a 2 MiB boundary.
254 Only disable this option if you know that you do not require
255 this feature (eg, building a kernel for a single machine) and
256 you need to shrink the kernel to the minimal size.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT
275 default DRAM_BASE if !MMU
276 default 0x00000000 if ARCH_FOOTBRIDGE
277 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
278 default 0x20000000 if ARCH_S5PV210
279 default 0xc0000000 if ARCH_SA1100
281 Please provide the physical address corresponding to the
282 location of main memory in your system.
288 config PGTABLE_LEVELS
290 default 3 if ARM_LPAE
296 bool "MMU-based Paged Memory Management Support"
299 Select if you want MMU-based virtualised addressing space
300 support by paged memory management. If unsure, say 'Y'.
302 config ARCH_MMAP_RND_BITS_MIN
305 config ARCH_MMAP_RND_BITS_MAX
306 default 14 if PAGE_OFFSET=0x40000000
307 default 15 if PAGE_OFFSET=0x80000000
311 # The "ARM system type" choice list is ordered alphabetically by option
312 # text. Please add new entries in the option alphabetic order.
315 prompt "ARM system type"
316 default ARM_SINGLE_ARMV7M if !MMU
317 default ARCH_MULTIPLATFORM if MMU
319 config ARCH_MULTIPLATFORM
320 bool "Allow multiple platforms to be selected"
322 select ARCH_FLATMEM_ENABLE
323 select ARCH_SPARSEMEM_ENABLE
324 select ARCH_SELECT_MEMORY_MODEL
325 select ARM_HAS_SG_CHAIN
326 select ARM_PATCH_PHYS_VIRT
330 select GENERIC_IRQ_MULTI_HANDLER
332 select PCI_DOMAINS_GENERIC if PCI
336 config ARM_SINGLE_ARMV7M
337 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
350 select ARCH_SPARSEMEM_ENABLE
352 imply ARM_PATCH_PHYS_VIRT
354 select GENERIC_IRQ_MULTI_HANDLER
360 select HAVE_LEGACY_CLK
362 This enables support for the Cirrus EP93xx series of CPUs.
364 config ARCH_FOOTBRIDGE
369 select NEED_MACH_IO_H if !MMU
370 select NEED_MACH_MEMORY_H
372 Support for systems based on the DC21285 companion chip
373 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
381 select NEED_RET_TO_USER
385 Support for Intel's 80219 and IOP32X (XScale) family of
391 select ARCH_HAS_DMA_SET_COHERENT_MASK
392 select ARCH_SUPPORTS_BIG_ENDIAN
394 select DMABOUNCE if PCI
395 select GENERIC_IRQ_MULTI_HANDLER
401 select NEED_MACH_IO_H
402 select USB_EHCI_BIG_ENDIAN_DESC
403 select USB_EHCI_BIG_ENDIAN_MMIO
405 Support for Intel's IXP4XX (XScale) family of processors.
410 select GENERIC_IRQ_MULTI_HANDLER
416 select PLAT_ORION_LEGACY
418 select PM_GENERIC_DOMAINS if PM
420 Support for the Marvell Dove SoC 88AP510
423 bool "PXA2xx/PXA3xx-based"
426 select ARM_CPU_SUSPEND if PM
432 select CPU_XSCALE if !CPU_XSC3
433 select GENERIC_IRQ_MULTI_HANDLER
441 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
447 select ARCH_MAY_HAVE_PC_FDC
448 select ARCH_SPARSEMEM_ENABLE
449 select ARM_HAS_SG_CHAIN
453 select HAVE_PATA_PLATFORM
455 select LEGACY_TIMER_TICK
456 select NEED_MACH_IO_H
457 select NEED_MACH_MEMORY_H
460 On the Acorn Risc-PC, Linux can support the internal IDE disk and
461 CD-ROM interface, serial and parallel port, and the floppy drive.
466 select ARCH_SPARSEMEM_ENABLE
469 select TIMER_OF if OF
473 select GENERIC_IRQ_MULTI_HANDLER
478 select NEED_MACH_MEMORY_H
481 Support for StrongARM 11x0 based boards.
484 bool "Samsung S3C24XX SoCs"
486 select CLKSRC_SAMSUNG_PWM
489 select GENERIC_IRQ_MULTI_HANDLER
490 select HAVE_S3C2410_I2C if I2C
491 select HAVE_S3C_RTC if RTC_CLASS
492 select NEED_MACH_IO_H
493 select S3C2410_WATCHDOG
498 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
499 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
500 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
501 Samsung SMDK2410 development board (and derivatives).
509 select GENERIC_IRQ_CHIP
510 select GENERIC_IRQ_MULTI_HANDLER
513 select HAVE_LEGACY_CLK
515 select NEED_MACH_IO_H if PCCARD
516 select NEED_MACH_MEMORY_H
519 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
523 menu "Multiple platform selection"
524 depends on ARCH_MULTIPLATFORM
526 comment "CPU Core family selection"
529 bool "ARMv4 based platforms (FA526)"
530 depends on !ARCH_MULTI_V6_V7
531 select ARCH_MULTI_V4_V5
534 config ARCH_MULTI_V4T
535 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
536 depends on !ARCH_MULTI_V6_V7
537 select ARCH_MULTI_V4_V5
538 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
539 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
540 CPU_ARM925T || CPU_ARM940T)
543 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
544 depends on !ARCH_MULTI_V6_V7
545 select ARCH_MULTI_V4_V5
546 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
547 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
548 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
550 config ARCH_MULTI_V4_V5
554 bool "ARMv6 based platforms (ARM11)"
555 select ARCH_MULTI_V6_V7
559 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
561 select ARCH_MULTI_V6_V7
565 config ARCH_MULTI_V6_V7
567 select MIGHT_HAVE_CACHE_L2X0
569 config ARCH_MULTI_CPU_AUTO
570 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
576 bool "Dummy Virtual Machine"
577 depends on ARCH_MULTI_V7
580 select ARM_GIC_V2M if PCI
582 select ARM_GIC_V3_ITS if PCI
584 select HAVE_ARM_ARCH_TIMER
585 select ARCH_SUPPORTS_BIG_ENDIAN
588 # This is sorted alphabetically by mach-* pathname. However, plat-*
589 # Kconfigs may be included either alphabetically (according to the
590 # plat- suffix) or along side the corresponding mach-* source.
592 source "arch/arm/mach-actions/Kconfig"
594 source "arch/arm/mach-alpine/Kconfig"
596 source "arch/arm/mach-artpec/Kconfig"
598 source "arch/arm/mach-asm9260/Kconfig"
600 source "arch/arm/mach-aspeed/Kconfig"
602 source "arch/arm/mach-at91/Kconfig"
604 source "arch/arm/mach-axxia/Kconfig"
606 source "arch/arm/mach-bcm/Kconfig"
608 source "arch/arm/mach-berlin/Kconfig"
610 source "arch/arm/mach-clps711x/Kconfig"
612 source "arch/arm/mach-cns3xxx/Kconfig"
614 source "arch/arm/mach-davinci/Kconfig"
616 source "arch/arm/mach-digicolor/Kconfig"
618 source "arch/arm/mach-dove/Kconfig"
620 source "arch/arm/mach-ep93xx/Kconfig"
622 source "arch/arm/mach-exynos/Kconfig"
624 source "arch/arm/mach-footbridge/Kconfig"
626 source "arch/arm/mach-gemini/Kconfig"
628 source "arch/arm/mach-highbank/Kconfig"
630 source "arch/arm/mach-hisi/Kconfig"
632 source "arch/arm/mach-imx/Kconfig"
634 source "arch/arm/mach-integrator/Kconfig"
636 source "arch/arm/mach-iop32x/Kconfig"
638 source "arch/arm/mach-ixp4xx/Kconfig"
640 source "arch/arm/mach-keystone/Kconfig"
642 source "arch/arm/mach-lpc32xx/Kconfig"
644 source "arch/arm/mach-mediatek/Kconfig"
646 source "arch/arm/mach-meson/Kconfig"
648 source "arch/arm/mach-milbeaut/Kconfig"
650 source "arch/arm/mach-mmp/Kconfig"
652 source "arch/arm/mach-moxart/Kconfig"
654 source "arch/arm/mach-mstar/Kconfig"
656 source "arch/arm/mach-mv78xx0/Kconfig"
658 source "arch/arm/mach-mvebu/Kconfig"
660 source "arch/arm/mach-mxs/Kconfig"
662 source "arch/arm/mach-nomadik/Kconfig"
664 source "arch/arm/mach-npcm/Kconfig"
666 source "arch/arm/mach-nspire/Kconfig"
668 source "arch/arm/plat-omap/Kconfig"
670 source "arch/arm/mach-omap1/Kconfig"
672 source "arch/arm/mach-omap2/Kconfig"
674 source "arch/arm/mach-orion5x/Kconfig"
676 source "arch/arm/mach-oxnas/Kconfig"
678 source "arch/arm/mach-pxa/Kconfig"
679 source "arch/arm/plat-pxa/Kconfig"
681 source "arch/arm/mach-qcom/Kconfig"
683 source "arch/arm/mach-rda/Kconfig"
685 source "arch/arm/mach-realtek/Kconfig"
687 source "arch/arm/mach-realview/Kconfig"
689 source "arch/arm/mach-rockchip/Kconfig"
691 source "arch/arm/mach-s3c/Kconfig"
693 source "arch/arm/mach-s5pv210/Kconfig"
695 source "arch/arm/mach-sa1100/Kconfig"
697 source "arch/arm/mach-shmobile/Kconfig"
699 source "arch/arm/mach-socfpga/Kconfig"
701 source "arch/arm/mach-spear/Kconfig"
703 source "arch/arm/mach-sti/Kconfig"
705 source "arch/arm/mach-stm32/Kconfig"
707 source "arch/arm/mach-sunxi/Kconfig"
709 source "arch/arm/mach-tegra/Kconfig"
711 source "arch/arm/mach-uniphier/Kconfig"
713 source "arch/arm/mach-ux500/Kconfig"
715 source "arch/arm/mach-versatile/Kconfig"
717 source "arch/arm/mach-vexpress/Kconfig"
719 source "arch/arm/mach-vt8500/Kconfig"
721 source "arch/arm/mach-zynq/Kconfig"
723 # ARMv7-M architecture
725 bool "NXP LPC18xx/LPC43xx"
726 depends on ARM_SINGLE_ARMV7M
727 select ARCH_HAS_RESET_CONTROLLER
729 select CLKSRC_LPC32XX
732 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
733 high performance microcontrollers.
736 bool "ARM MPS2 platform"
737 depends on ARM_SINGLE_ARMV7M
741 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
742 with a range of available cores like Cortex-M3/M4/M7.
744 Please, note that depends which Application Note is used memory map
745 for the platform may vary, so adjustment of RAM base might be needed.
747 # Definitions to make life easier
758 select GENERIC_IRQ_CHIP
761 config PLAT_ORION_LEGACY
768 config PLAT_VERSATILE
771 source "arch/arm/mm/Kconfig"
774 bool "Enable iWMMXt support"
775 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
776 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
778 Enable support for iWMMXt context switching at run time if
779 running on a CPU that supports it.
782 source "arch/arm/Kconfig-nommu"
785 config PJ4B_ERRATA_4742
786 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
787 depends on CPU_PJ4B && MACH_ARMADA_370
790 When coming out of either a Wait for Interrupt (WFI) or a Wait for
791 Event (WFE) IDLE states, a specific timing sensitivity exists between
792 the retiring WFI/WFE instructions and the newly issued subsequent
793 instructions. This sensitivity can result in a CPU hang scenario.
795 The software must insert either a Data Synchronization Barrier (DSB)
796 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
799 config ARM_ERRATA_326103
800 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
803 Executing a SWP instruction to read-only memory does not set bit 11
804 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
805 treat the access as a read, preventing a COW from occurring and
806 causing the faulting task to livelock.
808 config ARM_ERRATA_411920
809 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
810 depends on CPU_V6 || CPU_V6K
812 Invalidation of the Instruction Cache operation can
813 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
814 It does not affect the MPCore. This option enables the ARM Ltd.
815 recommended workaround.
817 config ARM_ERRATA_430973
818 bool "ARM errata: Stale prediction on replaced interworking branch"
821 This option enables the workaround for the 430973 Cortex-A8
822 r1p* erratum. If a code sequence containing an ARM/Thumb
823 interworking branch is replaced with another code sequence at the
824 same virtual address, whether due to self-modifying code or virtual
825 to physical address re-mapping, Cortex-A8 does not recover from the
826 stale interworking branch prediction. This results in Cortex-A8
827 executing the new code sequence in the incorrect ARM or Thumb state.
828 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
829 and also flushes the branch target cache at every context switch.
830 Note that setting specific bits in the ACTLR register may not be
831 available in non-secure mode.
833 config ARM_ERRATA_458693
834 bool "ARM errata: Processor deadlock when a false hazard is created"
836 depends on !ARCH_MULTIPLATFORM
838 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
839 erratum. For very specific sequences of memory operations, it is
840 possible for a hazard condition intended for a cache line to instead
841 be incorrectly associated with a different cache line. This false
842 hazard might then cause a processor deadlock. The workaround enables
843 the L1 caching of the NEON accesses and disables the PLD instruction
844 in the ACTLR register. Note that setting specific bits in the ACTLR
845 register may not be available in non-secure mode.
847 config ARM_ERRATA_460075
848 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
850 depends on !ARCH_MULTIPLATFORM
852 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
853 erratum. Any asynchronous access to the L2 cache may encounter a
854 situation in which recent store transactions to the L2 cache are lost
855 and overwritten with stale memory contents from external memory. The
856 workaround disables the write-allocate mode for the L2 cache via the
857 ACTLR register. Note that setting specific bits in the ACTLR register
858 may not be available in non-secure mode.
860 config ARM_ERRATA_742230
861 bool "ARM errata: DMB operation may be faulty"
862 depends on CPU_V7 && SMP
863 depends on !ARCH_MULTIPLATFORM
865 This option enables the workaround for the 742230 Cortex-A9
866 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
867 between two write operations may not ensure the correct visibility
868 ordering of the two writes. This workaround sets a specific bit in
869 the diagnostic register of the Cortex-A9 which causes the DMB
870 instruction to behave as a DSB, ensuring the correct behaviour of
873 config ARM_ERRATA_742231
874 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
875 depends on CPU_V7 && SMP
876 depends on !ARCH_MULTIPLATFORM
878 This option enables the workaround for the 742231 Cortex-A9
879 (r2p0..r2p2) erratum. Under certain conditions, specific to the
880 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
881 accessing some data located in the same cache line, may get corrupted
882 data due to bad handling of the address hazard when the line gets
883 replaced from one of the CPUs at the same time as another CPU is
884 accessing it. This workaround sets specific bits in the diagnostic
885 register of the Cortex-A9 which reduces the linefill issuing
886 capabilities of the processor.
888 config ARM_ERRATA_643719
889 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
890 depends on CPU_V7 && SMP
893 This option enables the workaround for the 643719 Cortex-A9 (prior to
894 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
895 register returns zero when it should return one. The workaround
896 corrects this value, ensuring cache maintenance operations which use
897 it behave as intended and avoiding data corruption.
899 config ARM_ERRATA_720789
900 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
903 This option enables the workaround for the 720789 Cortex-A9 (prior to
904 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
905 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
906 As a consequence of this erratum, some TLB entries which should be
907 invalidated are not, resulting in an incoherency in the system page
908 tables. The workaround changes the TLB flushing routines to invalidate
909 entries regardless of the ASID.
911 config ARM_ERRATA_743622
912 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
914 depends on !ARCH_MULTIPLATFORM
916 This option enables the workaround for the 743622 Cortex-A9
917 (r2p*) erratum. Under very rare conditions, a faulty
918 optimisation in the Cortex-A9 Store Buffer may lead to data
919 corruption. This workaround sets a specific bit in the diagnostic
920 register of the Cortex-A9 which disables the Store Buffer
921 optimisation, preventing the defect from occurring. This has no
922 visible impact on the overall performance or power consumption of the
925 config ARM_ERRATA_751472
926 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
928 depends on !ARCH_MULTIPLATFORM
930 This option enables the workaround for the 751472 Cortex-A9 (prior
931 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
932 completion of a following broadcasted operation if the second
933 operation is received by a CPU before the ICIALLUIS has completed,
934 potentially leading to corrupted entries in the cache or TLB.
936 config ARM_ERRATA_754322
937 bool "ARM errata: possible faulty MMU translations following an ASID switch"
940 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
941 r3p*) erratum. A speculative memory access may cause a page table walk
942 which starts prior to an ASID switch but completes afterwards. This
943 can populate the micro-TLB with a stale entry which may be hit with
944 the new ASID. This workaround places two dsb instructions in the mm
945 switching code so that no page table walks can cross the ASID switch.
947 config ARM_ERRATA_754327
948 bool "ARM errata: no automatic Store Buffer drain"
949 depends on CPU_V7 && SMP
951 This option enables the workaround for the 754327 Cortex-A9 (prior to
952 r2p0) erratum. The Store Buffer does not have any automatic draining
953 mechanism and therefore a livelock may occur if an external agent
954 continuously polls a memory location waiting to observe an update.
955 This workaround defines cpu_relax() as smp_mb(), preventing correctly
956 written polling loops from denying visibility of updates to memory.
958 config ARM_ERRATA_364296
959 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
962 This options enables the workaround for the 364296 ARM1136
963 r0p2 erratum (possible cache data corruption with
964 hit-under-miss enabled). It sets the undocumented bit 31 in
965 the auxiliary control register and the FI bit in the control
966 register, thus disabling hit-under-miss without putting the
967 processor into full low interrupt latency mode. ARM11MPCore
970 config ARM_ERRATA_764369
971 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
972 depends on CPU_V7 && SMP
974 This option enables the workaround for erratum 764369
975 affecting Cortex-A9 MPCore with two or more processors (all
976 current revisions). Under certain timing circumstances, a data
977 cache line maintenance operation by MVA targeting an Inner
978 Shareable memory region may fail to proceed up to either the
979 Point of Coherency or to the Point of Unification of the
980 system. This workaround adds a DSB instruction before the
981 relevant cache maintenance functions and sets a specific bit
982 in the diagnostic control register of the SCU.
984 config ARM_ERRATA_775420
985 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
988 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
989 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
990 operation aborts with MMU exception, it might cause the processor
991 to deadlock. This workaround puts DSB before executing ISB if
992 an abort may occur on cache maintenance.
994 config ARM_ERRATA_798181
995 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
996 depends on CPU_V7 && SMP
998 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
999 adequately shooting down all use of the old entries. This
1000 option enables the Linux kernel workaround for this erratum
1001 which sends an IPI to the CPUs that are running the same ASID
1002 as the one being invalidated.
1004 config ARM_ERRATA_773022
1005 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1008 This option enables the workaround for the 773022 Cortex-A15
1009 (up to r0p4) erratum. In certain rare sequences of code, the
1010 loop buffer may deliver incorrect instructions. This
1011 workaround disables the loop buffer to avoid the erratum.
1013 config ARM_ERRATA_818325_852422
1014 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1017 This option enables the workaround for:
1018 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1019 instruction might deadlock. Fixed in r0p1.
1020 - Cortex-A12 852422: Execution of a sequence of instructions might
1021 lead to either a data corruption or a CPU deadlock. Not fixed in
1022 any Cortex-A12 cores yet.
1023 This workaround for all both errata involves setting bit[12] of the
1024 Feature Register. This bit disables an optimisation applied to a
1025 sequence of 2 instructions that use opposing condition codes.
1027 config ARM_ERRATA_821420
1028 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1031 This option enables the workaround for the 821420 Cortex-A12
1032 (all revs) erratum. In very rare timing conditions, a sequence
1033 of VMOV to Core registers instructions, for which the second
1034 one is in the shadow of a branch or abort, can lead to a
1035 deadlock when the VMOV instructions are issued out-of-order.
1037 config ARM_ERRATA_825619
1038 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1041 This option enables the workaround for the 825619 Cortex-A12
1042 (all revs) erratum. Within rare timing constraints, executing a
1043 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1044 and Device/Strongly-Ordered loads and stores might cause deadlock
1046 config ARM_ERRATA_857271
1047 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1050 This option enables the workaround for the 857271 Cortex-A12
1051 (all revs) erratum. Under very rare timing conditions, the CPU might
1052 hang. The workaround is expected to have a < 1% performance impact.
1054 config ARM_ERRATA_852421
1055 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1058 This option enables the workaround for the 852421 Cortex-A17
1059 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1060 execution of a DMB ST instruction might fail to properly order
1061 stores from GroupA and stores from GroupB.
1063 config ARM_ERRATA_852423
1064 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1067 This option enables the workaround for:
1068 - Cortex-A17 852423: Execution of a sequence of instructions might
1069 lead to either a data corruption or a CPU deadlock. Not fixed in
1070 any Cortex-A17 cores yet.
1071 This is identical to Cortex-A12 erratum 852422. It is a separate
1072 config option from the A12 erratum due to the way errata are checked
1075 config ARM_ERRATA_857272
1076 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1079 This option enables the workaround for the 857272 Cortex-A17 erratum.
1080 This erratum is not known to be fixed in any A17 revision.
1081 This is identical to Cortex-A12 erratum 857271. It is a separate
1082 config option from the A12 erratum due to the way errata are checked
1087 source "arch/arm/common/Kconfig"
1094 Find out whether you have ISA slots on your motherboard. ISA is the
1095 name of a bus system, i.e. the way the CPU talks to the other stuff
1096 inside your box. Other bus systems are PCI, EISA, MicroChannel
1097 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1098 newer boards don't support it. If you have ISA, say Y, otherwise N.
1100 # Select ISA DMA controller support
1105 # Select ISA DMA interface
1109 config PCI_NANOENGINE
1110 bool "BSE nanoEngine PCI support"
1111 depends on SA1100_NANOENGINE
1113 Enable PCI on the BSE nanoEngine board.
1115 config ARM_ERRATA_814220
1116 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1119 The v7 ARM states that all cache and branch predictor maintenance
1120 operations that do not specify an address execute, relative to
1121 each other, in program order.
1122 However, because of this erratum, an L2 set/way cache maintenance
1123 operation can overtake an L1 set/way cache maintenance operation.
1124 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1129 menu "Kernel Features"
1134 This option should be selected by machines which have an SMP-
1137 The only effect of this option is to make the SMP-related
1138 options available to the user for configuration.
1141 bool "Symmetric Multi-Processing"
1142 depends on CPU_V6K || CPU_V7
1144 depends on MMU || ARM_MPU
1147 This enables support for systems with more than one CPU. If you have
1148 a system with only one CPU, say N. If you have a system with more
1149 than one CPU, say Y.
1151 If you say N here, the kernel will run on uni- and multiprocessor
1152 machines, but will use only one CPU of a multiprocessor machine. If
1153 you say Y here, the kernel will run on many, but not all,
1154 uniprocessor machines. On a uniprocessor machine, the kernel
1155 will run faster if you say N here.
1157 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1158 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1159 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1161 If you don't know what to do here, say N.
1164 bool "Allow booting SMP kernel on uniprocessor systems"
1165 depends on SMP && !XIP_KERNEL && MMU
1168 SMP kernels contain instructions which fail on non-SMP processors.
1169 Enabling this option allows the kernel to modify itself to make
1170 these instructions safe. Disabling it allows about 1K of space
1173 If you don't know what to do here, say Y.
1175 config ARM_CPU_TOPOLOGY
1176 bool "Support cpu topology definition"
1177 depends on SMP && CPU_V7
1180 Support ARM cpu topology definition. The MPIDR register defines
1181 affinity between processors which is then used to describe the cpu
1182 topology of an ARM System.
1185 bool "Multi-core scheduler support"
1186 depends on ARM_CPU_TOPOLOGY
1188 Multi-core scheduler support improves the CPU scheduler's decision
1189 making when dealing with multi-core CPU chips at a cost of slightly
1190 increased overhead in some places. If unsure say N here.
1193 bool "SMT scheduler support"
1194 depends on ARM_CPU_TOPOLOGY
1196 Improves the CPU scheduler's decision making when dealing with
1197 MultiThreading at a cost of slightly increased overhead in some
1198 places. If unsure say N here.
1203 This option enables support for the ARM snoop control unit
1205 config HAVE_ARM_ARCH_TIMER
1206 bool "Architected timer support"
1208 select ARM_ARCH_TIMER
1210 This option enables support for the ARM architected timer
1215 This options enables support for the ARM timer and watchdog unit
1218 bool "Multi-Cluster Power Management"
1219 depends on CPU_V7 && SMP
1221 This option provides the common power management infrastructure
1222 for (multi-)cluster based systems, such as big.LITTLE based
1225 config MCPM_QUAD_CLUSTER
1229 To avoid wasting resources unnecessarily, MCPM only supports up
1230 to 2 clusters by default.
1231 Platforms with 3 or 4 clusters that use MCPM must select this
1232 option to allow the additional clusters to be managed.
1235 bool "big.LITTLE support (Experimental)"
1236 depends on CPU_V7 && SMP
1239 This option enables support selections for the big.LITTLE
1240 system architecture.
1243 bool "big.LITTLE switcher support"
1244 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1247 The big.LITTLE "switcher" provides the core functionality to
1248 transparently handle transition between a cluster of A15's
1249 and a cluster of A7's in a big.LITTLE system.
1251 config BL_SWITCHER_DUMMY_IF
1252 tristate "Simple big.LITTLE switcher user interface"
1253 depends on BL_SWITCHER && DEBUG_KERNEL
1255 This is a simple and dummy char dev interface to control
1256 the big.LITTLE switcher core code. It is meant for
1257 debugging purposes only.
1260 prompt "Memory split"
1264 Select the desired split between kernel and user memory.
1266 If you are not absolutely sure what you are doing, leave this
1270 bool "3G/1G user/kernel split"
1271 config VMSPLIT_3G_OPT
1272 depends on !ARM_LPAE
1273 bool "3G/1G user/kernel split (for full 1G low memory)"
1275 bool "2G/2G user/kernel split"
1277 bool "1G/3G user/kernel split"
1282 default PHYS_OFFSET if !MMU
1283 default 0x40000000 if VMSPLIT_1G
1284 default 0x80000000 if VMSPLIT_2G
1285 default 0xB0000000 if VMSPLIT_3G_OPT
1288 config KASAN_SHADOW_OFFSET
1291 default 0x1f000000 if PAGE_OFFSET=0x40000000
1292 default 0x5f000000 if PAGE_OFFSET=0x80000000
1293 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1294 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1298 int "Maximum number of CPUs (2-32)"
1299 range 2 16 if DEBUG_KMAP_LOCAL
1300 range 2 32 if !DEBUG_KMAP_LOCAL
1304 The maximum number of CPUs that the kernel can support.
1305 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1306 debugging is enabled, which uses half of the per-CPU fixmap
1307 slots as guard regions.
1310 bool "Support for hot-pluggable CPUs"
1312 select GENERIC_IRQ_MIGRATION
1314 Say Y here to experiment with turning CPUs off and on. CPUs
1315 can be controlled through /sys/devices/system/cpu.
1318 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1319 depends on HAVE_ARM_SMCCC
1322 Say Y here if you want Linux to communicate with system firmware
1323 implementing the PSCI specification for CPU-centric power
1324 management operations described in ARM document number ARM DEN
1325 0022A ("Power State Coordination Interface System Software on
1328 # The GPIO number here must be sorted by descending number. In case of
1329 # a multiplatform kernel, we just want the highest value required by the
1330 # selected platforms.
1333 default 2048 if ARCH_INTEL_SOCFPGA
1334 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1335 ARCH_ZYNQ || ARCH_ASPEED
1336 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1337 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1338 default 416 if ARCH_SUNXI
1339 default 392 if ARCH_U8500
1340 default 352 if ARCH_VT8500
1341 default 288 if ARCH_ROCKCHIP
1342 default 264 if MACH_H4700
1345 Maximum number of GPIOs in the system.
1347 If unsure, leave the default value.
1351 default 128 if SOC_AT91RM9200
1355 depends on HZ_FIXED = 0
1356 prompt "Timer frequency"
1380 default HZ_FIXED if HZ_FIXED != 0
1381 default 100 if HZ_100
1382 default 200 if HZ_200
1383 default 250 if HZ_250
1384 default 300 if HZ_300
1385 default 500 if HZ_500
1389 def_bool HIGH_RES_TIMERS
1391 config THUMB2_KERNEL
1392 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1393 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1394 default y if CPU_THUMBONLY
1397 By enabling this option, the kernel will be compiled in
1402 config ARM_PATCH_IDIV
1403 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1404 depends on CPU_32v7 && !XIP_KERNEL
1407 The ARM compiler inserts calls to __aeabi_idiv() and
1408 __aeabi_uidiv() when it needs to perform division on signed
1409 and unsigned integers. Some v7 CPUs have support for the sdiv
1410 and udiv instructions that can be used to implement those
1413 Enabling this option allows the kernel to modify itself to
1414 replace the first two instructions of these library functions
1415 with the sdiv or udiv plus "bx lr" instructions when the CPU
1416 it is running on supports them. Typically this will be faster
1417 and less power intensive than running the original library
1418 code to do integer division.
1421 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1422 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1423 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1425 This option allows for the kernel to be compiled using the latest
1426 ARM ABI (aka EABI). This is only useful if you are using a user
1427 space environment that is also compiled with EABI.
1429 Since there are major incompatibilities between the legacy ABI and
1430 EABI, especially with regard to structure member alignment, this
1431 option also changes the kernel syscall calling convention to
1432 disambiguate both ABIs and allow for backward compatibility support
1433 (selected with CONFIG_OABI_COMPAT).
1435 To use this you need GCC version 4.0.0 or later.
1438 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1439 depends on AEABI && !THUMB2_KERNEL
1441 This option preserves the old syscall interface along with the
1442 new (ARM EABI) one. It also provides a compatibility layer to
1443 intercept syscalls that have structure arguments which layout
1444 in memory differs between the legacy ABI and the new ARM EABI
1445 (only for non "thumb" binaries). This option adds a tiny
1446 overhead to all syscalls and produces a slightly larger kernel.
1448 The seccomp filter system will not be available when this is
1449 selected, since there is no way yet to sensibly distinguish
1450 between calling conventions during filtering.
1452 If you know you'll be using only pure EABI user space then you
1453 can say N here. If this option is not selected and you attempt
1454 to execute a legacy ABI binary then the result will be
1455 UNPREDICTABLE (in fact it can be predicted that it won't work
1456 at all). If in doubt say N.
1458 config ARCH_SELECT_MEMORY_MODEL
1461 config ARCH_FLATMEM_ENABLE
1464 config ARCH_SPARSEMEM_ENABLE
1466 select SPARSEMEM_STATIC if SPARSEMEM
1469 bool "High Memory Support"
1473 The address space of ARM processors is only 4 Gigabytes large
1474 and it has to accommodate user address space, kernel address
1475 space as well as some memory mapped IO. That means that, if you
1476 have a large amount of physical memory and/or IO, not all of the
1477 memory can be "permanently mapped" by the kernel. The physical
1478 memory that is not permanently mapped is called "high memory".
1480 Depending on the selected kernel/user memory split, minimum
1481 vmalloc space and actual amount of RAM, you may not need this
1482 option which should result in a slightly faster kernel.
1487 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1491 The VM uses one page of physical memory for each page table.
1492 For systems with a lot of processes, this can use a lot of
1493 precious low memory, eventually leading to low memory being
1494 consumed by page tables. Setting this option will allow
1495 user-space 2nd level page tables to reside in high memory.
1497 config CPU_SW_DOMAIN_PAN
1498 bool "Enable use of CPU domains to implement privileged no-access"
1499 depends on MMU && !ARM_LPAE
1502 Increase kernel security by ensuring that normal kernel accesses
1503 are unable to access userspace addresses. This can help prevent
1504 use-after-free bugs becoming an exploitable privilege escalation
1505 by ensuring that magic values (such as LIST_POISON) will always
1506 fault when dereferenced.
1508 CPUs with low-vector mappings use a best-efforts implementation.
1509 Their lower 1MB needs to remain accessible for the vectors, but
1510 the remainder of userspace will become appropriately inaccessible.
1512 config HW_PERF_EVENTS
1516 config ARCH_WANT_GENERAL_HUGETLB
1519 config ARM_MODULE_PLTS
1520 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1524 Allocate PLTs when loading modules so that jumps and calls whose
1525 targets are too far away for their relative offsets to be encoded
1526 in the instructions themselves can be bounced via veneers in the
1527 module's PLT. This allows modules to be allocated in the generic
1528 vmalloc area after the dedicated module memory area has been
1529 exhausted. The modules will use slightly more memory, but after
1530 rounding up to page size, the actual memory footprint is usually
1533 Disabling this is usually safe for small single-platform
1534 configurations. If unsure, say y.
1536 config FORCE_MAX_ZONEORDER
1537 int "Maximum zone order"
1538 default "12" if SOC_AM33XX
1539 default "9" if SA1111
1542 The kernel memory allocator divides physically contiguous memory
1543 blocks into "zones", where each zone is a power of two number of
1544 pages. This option selects the largest power of two that the kernel
1545 keeps in the memory allocator. If you need to allocate very large
1546 blocks of physically contiguous memory, then you may need to
1547 increase this value.
1549 This config option is actually maximum order plus one. For example,
1550 a value of 11 means that the largest free memory block is 2^10 pages.
1552 config ALIGNMENT_TRAP
1553 def_bool CPU_CP15_MMU
1554 select HAVE_PROC_CPU if PROC_FS
1556 ARM processors cannot fetch/store information which is not
1557 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1558 address divisible by 4. On 32-bit ARM processors, these non-aligned
1559 fetch/store instructions will be emulated in software if you say
1560 here, which has a severe performance impact. This is necessary for
1561 correct operation of some network protocols. With an IP-only
1562 configuration it is safe to say N, otherwise say Y.
1564 config UACCESS_WITH_MEMCPY
1565 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1567 default y if CPU_FEROCEON
1569 Implement faster copy_to_user and clear_user methods for CPU
1570 cores where a 8-word STM instruction give significantly higher
1571 memory write throughput than a sequence of individual 32bit stores.
1573 A possible side effect is a slight increase in scheduling latency
1574 between threads sharing the same address space if they invoke
1575 such copy operations with large buffers.
1577 However, if the CPU data cache is using a write-allocate mode,
1578 this option is unlikely to provide any performance gain.
1581 bool "Enable paravirtualization code"
1583 This changes the kernel so it can modify itself when it is run
1584 under a hypervisor, potentially improving performance significantly
1585 over full virtualization.
1587 config PARAVIRT_TIME_ACCOUNTING
1588 bool "Paravirtual steal time accounting"
1591 Select this option to enable fine granularity task steal time
1592 accounting. Time spent executing other tasks in parallel with
1593 the current vCPU is discounted from the vCPU power. To account for
1594 that, there can be a small performance impact.
1596 If in doubt, say N here.
1603 bool "Xen guest support on ARM"
1604 depends on ARM && AEABI && OF
1605 depends on CPU_V7 && !CPU_V6
1606 depends on !GENERIC_ATOMIC64
1608 select ARCH_DMA_ADDR_T_64BIT
1614 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1616 config STACKPROTECTOR_PER_TASK
1617 bool "Use a unique stack canary value for each task"
1618 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1619 select GCC_PLUGIN_ARM_SSP_PER_TASK
1622 Due to the fact that GCC uses an ordinary symbol reference from
1623 which to load the value of the stack canary, this value can only
1624 change at reboot time on SMP systems, and all tasks running in the
1625 kernel's address space are forced to use the same canary value for
1626 the entire duration that the system is up.
1628 Enable this option to switch to a different method that uses a
1629 different canary value for each task.
1636 bool "Flattened Device Tree support"
1640 Include support for flattened device tree machine descriptions.
1643 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1646 This is the traditional way of passing data to the kernel at boot
1647 time. If you are solely relying on the flattened device tree (or
1648 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1649 to remove ATAGS support from your kernel binary. If unsure,
1652 config DEPRECATED_PARAM_STRUCT
1653 bool "Provide old way to pass kernel parameters"
1656 This was deprecated in 2001 and announced to live on for 5 years.
1657 Some old boot loaders still use this way.
1659 # Compressed boot loader in ROM. Yes, we really want to ask about
1660 # TEXT and BSS so we preserve their values in the config files.
1661 config ZBOOT_ROM_TEXT
1662 hex "Compressed ROM boot loader base address"
1665 The physical address at which the ROM-able zImage is to be
1666 placed in the target. Platforms which normally make use of
1667 ROM-able zImage formats normally set this to a suitable
1668 value in their defconfig file.
1670 If ZBOOT_ROM is not enabled, this has no effect.
1672 config ZBOOT_ROM_BSS
1673 hex "Compressed ROM boot loader BSS address"
1676 The base address of an area of read/write memory in the target
1677 for the ROM-able zImage which must be available while the
1678 decompressor is running. It must be large enough to hold the
1679 entire decompressed kernel plus an additional 128 KiB.
1680 Platforms which normally make use of ROM-able zImage formats
1681 normally set this to a suitable value in their defconfig file.
1683 If ZBOOT_ROM is not enabled, this has no effect.
1686 bool "Compressed boot loader in ROM/flash"
1687 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1688 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1690 Say Y here if you intend to execute your compressed kernel image
1691 (zImage) directly from ROM or flash. If unsure, say N.
1693 config ARM_APPENDED_DTB
1694 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1697 With this option, the boot code will look for a device tree binary
1698 (DTB) appended to zImage
1699 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1701 This is meant as a backward compatibility convenience for those
1702 systems with a bootloader that can't be upgraded to accommodate
1703 the documented boot protocol using a device tree.
1705 Beware that there is very little in terms of protection against
1706 this option being confused by leftover garbage in memory that might
1707 look like a DTB header after a reboot if no actual DTB is appended
1708 to zImage. Do not leave this option active in a production kernel
1709 if you don't intend to always append a DTB. Proper passing of the
1710 location into r2 of a bootloader provided DTB is always preferable
1713 config ARM_ATAG_DTB_COMPAT
1714 bool "Supplement the appended DTB with traditional ATAG information"
1715 depends on ARM_APPENDED_DTB
1717 Some old bootloaders can't be updated to a DTB capable one, yet
1718 they provide ATAGs with memory configuration, the ramdisk address,
1719 the kernel cmdline string, etc. Such information is dynamically
1720 provided by the bootloader and can't always be stored in a static
1721 DTB. To allow a device tree enabled kernel to be used with such
1722 bootloaders, this option allows zImage to extract the information
1723 from the ATAG list and store it at run time into the appended DTB.
1726 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1727 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1729 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1730 bool "Use bootloader kernel arguments if available"
1732 Uses the command-line options passed by the boot loader instead of
1733 the device tree bootargs property. If the boot loader doesn't provide
1734 any, the device tree bootargs property will be used.
1736 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1737 bool "Extend with bootloader kernel arguments"
1739 The command-line arguments provided by the boot loader will be
1740 appended to the the device tree bootargs property.
1745 string "Default kernel command string"
1748 On some architectures (e.g. CATS), there is currently no way
1749 for the boot loader to pass arguments to the kernel. For these
1750 architectures, you should supply some command-line options at build
1751 time by entering them here. As a minimum, you should specify the
1752 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1755 prompt "Kernel command line type" if CMDLINE != ""
1756 default CMDLINE_FROM_BOOTLOADER
1759 config CMDLINE_FROM_BOOTLOADER
1760 bool "Use bootloader kernel arguments if available"
1762 Uses the command-line options passed by the boot loader. If
1763 the boot loader doesn't provide any, the default kernel command
1764 string provided in CMDLINE will be used.
1766 config CMDLINE_EXTEND
1767 bool "Extend bootloader kernel arguments"
1769 The command-line arguments provided by the boot loader will be
1770 appended to the default kernel command string.
1772 config CMDLINE_FORCE
1773 bool "Always use the default kernel command string"
1775 Always use the default kernel command string, even if the boot
1776 loader passes other arguments to the kernel.
1777 This is useful if you cannot or don't want to change the
1778 command-line options your boot loader passes to the kernel.
1782 bool "Kernel Execute-In-Place from ROM"
1783 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1785 Execute-In-Place allows the kernel to run from non-volatile storage
1786 directly addressable by the CPU, such as NOR flash. This saves RAM
1787 space since the text section of the kernel is not loaded from flash
1788 to RAM. Read-write sections, such as the data section and stack,
1789 are still copied to RAM. The XIP kernel is not compressed since
1790 it has to run directly from flash, so it will take more space to
1791 store it. The flash address used to link the kernel object files,
1792 and for storing it, is configuration dependent. Therefore, if you
1793 say Y here, you must know the proper physical address where to
1794 store the kernel image depending on your own flash memory usage.
1796 Also note that the make target becomes "make xipImage" rather than
1797 "make zImage" or "make Image". The final kernel binary to put in
1798 ROM memory will be arch/arm/boot/xipImage.
1802 config XIP_PHYS_ADDR
1803 hex "XIP Kernel Physical Location"
1804 depends on XIP_KERNEL
1805 default "0x00080000"
1807 This is the physical address in your flash memory the kernel will
1808 be linked for and stored to. This address is dependent on your
1811 config XIP_DEFLATED_DATA
1812 bool "Store kernel .data section compressed in ROM"
1813 depends on XIP_KERNEL
1816 Before the kernel is actually executed, its .data section has to be
1817 copied to RAM from ROM. This option allows for storing that data
1818 in compressed form and decompressed to RAM rather than merely being
1819 copied, saving some precious ROM space. A possible drawback is a
1820 slightly longer boot delay.
1823 bool "Kexec system call (EXPERIMENTAL)"
1824 depends on (!SMP || PM_SLEEP_SMP)
1828 kexec is a system call that implements the ability to shutdown your
1829 current kernel, and to start another kernel. It is like a reboot
1830 but it is independent of the system firmware. And like a reboot
1831 you can start any kernel with it, not just Linux.
1833 It is an ongoing process to be certain the hardware in a machine
1834 is properly shutdown, so do not be surprised if this code does not
1835 initially work for you.
1838 bool "Export atags in procfs"
1839 depends on ATAGS && KEXEC
1842 Should the atags used to boot the kernel be exported in an "atags"
1843 file in procfs. Useful with kexec.
1846 bool "Build kdump crash kernel (EXPERIMENTAL)"
1848 Generate crash dump after being started by kexec. This should
1849 be normally only set in special crash dump kernels which are
1850 loaded in the main kernel with kexec-tools into a specially
1851 reserved region and then later executed after a crash by
1852 kdump/kexec. The crash dump kernel must be compiled to a
1853 memory address not used by the main kernel
1855 For more details see Documentation/admin-guide/kdump/kdump.rst
1857 config AUTO_ZRELADDR
1858 bool "Auto calculation of the decompressed kernel image address"
1860 ZRELADDR is the physical address where the decompressed kernel
1861 image will be placed. If AUTO_ZRELADDR is selected, the address
1862 will be determined at run-time, either by masking the current IP
1863 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1864 This assumes the zImage being placed in the first 128MB from
1871 bool "UEFI runtime support"
1872 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1874 select EFI_PARAMS_FROM_FDT
1876 select EFI_GENERIC_STUB
1877 select EFI_RUNTIME_WRAPPERS
1879 This option provides support for runtime services provided
1880 by UEFI firmware (such as non-volatile variables, realtime
1881 clock, and platform reset). A UEFI stub is also provided to
1882 allow the kernel to be booted as an EFI application. This
1883 is only useful for kernels that may run on systems that have
1887 bool "Enable support for SMBIOS (DMI) tables"
1891 This enables SMBIOS/DMI feature for systems.
1893 This option is only useful on systems that have UEFI firmware.
1894 However, even with this option, the resultant kernel should
1895 continue to boot on existing non-UEFI platforms.
1897 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1898 i.e., the the practice of identifying the platform via DMI to
1899 decide whether certain workarounds for buggy hardware and/or
1900 firmware need to be enabled. This would require the DMI subsystem
1901 to be enabled much earlier than we do on ARM, which is non-trivial.
1905 menu "CPU Power Management"
1907 source "drivers/cpufreq/Kconfig"
1909 source "drivers/cpuidle/Kconfig"
1913 menu "Floating point emulation"
1915 comment "At least one emulation must be selected"
1918 bool "NWFPE math emulation"
1919 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1921 Say Y to include the NWFPE floating point emulator in the kernel.
1922 This is necessary to run most binaries. Linux does not currently
1923 support floating point hardware so you need to say Y here even if
1924 your machine has an FPA or floating point co-processor podule.
1926 You may say N here if you are going to load the Acorn FPEmulator
1927 early in the bootup.
1930 bool "Support extended precision"
1931 depends on FPE_NWFPE
1933 Say Y to include 80-bit support in the kernel floating-point
1934 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1935 Note that gcc does not generate 80-bit operations by default,
1936 so in most cases this option only enlarges the size of the
1937 floating point emulator without any good reason.
1939 You almost surely want to say N here.
1942 bool "FastFPE math emulation (EXPERIMENTAL)"
1943 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1945 Say Y here to include the FAST floating point emulator in the kernel.
1946 This is an experimental much faster emulator which now also has full
1947 precision for the mantissa. It does not support any exceptions.
1948 It is very simple, and approximately 3-6 times faster than NWFPE.
1950 It should be sufficient for most programs. It may be not suitable
1951 for scientific calculations, but you have to check this for yourself.
1952 If you do not feel you need a faster FP emulation you should better
1956 bool "VFP-format floating point maths"
1957 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1959 Say Y to include VFP support code in the kernel. This is needed
1960 if your hardware includes a VFP unit.
1962 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1963 release notes and additional status information.
1965 Say N if your target does not have VFP hardware.
1973 bool "Advanced SIMD (NEON) Extension support"
1974 depends on VFPv3 && CPU_V7
1976 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1979 config KERNEL_MODE_NEON
1980 bool "Support for NEON in kernel mode"
1981 depends on NEON && AEABI
1983 Say Y to include support for NEON in kernel mode.
1987 menu "Power management options"
1989 source "kernel/power/Kconfig"
1991 config ARCH_SUSPEND_POSSIBLE
1992 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1993 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1996 config ARM_CPU_SUSPEND
1997 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1998 depends on ARCH_SUSPEND_POSSIBLE
2000 config ARCH_HIBERNATION_POSSIBLE
2003 default y if ARCH_SUSPEND_POSSIBLE
2007 source "drivers/firmware/Kconfig"
2010 source "arch/arm/crypto/Kconfig"
2013 source "arch/arm/Kconfig.assembler"