1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_USE_BUILTIN_BSWAP
35 select ARCH_USE_CMPXCHG_LOCKREF
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
39 select BUILDTIME_TABLE_SORT if MMU
40 select CLONE_BACKWARDS
41 select CPU_PM if SUSPEND || CPU_IDLE
42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
43 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_IRQ_IPI if SMP
53 select GENERIC_CPU_AUTOPROBE
54 select GENERIC_EARLY_IOREMAP
55 select GENERIC_IDLE_POLL_SETUP
56 select GENERIC_IRQ_PROBE
57 select GENERIC_IRQ_SHOW
58 select GENERIC_IRQ_SHOW_LEVEL
59 select GENERIC_PCI_IOMAP
60 select GENERIC_SCHED_CLOCK
61 select GENERIC_SMP_IDLE_THREAD
62 select GENERIC_STRNCPY_FROM_USER
63 select GENERIC_STRNLEN_USER
64 select HANDLE_DOMAIN_IRQ
65 select HARDIRQS_SW_RESEND
66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
70 select HAVE_ARCH_MMAP_RND_BITS if MMU
71 select HAVE_ARCH_SECCOMP
72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
74 select HAVE_ARCH_TRACEHOOK
75 select HAVE_ARM_SMCCC if CPU_V7
76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
77 select HAVE_CONTEXT_TRACKING
78 select HAVE_C_RECORDMCOUNT
79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
80 select HAVE_DMA_CONTIGUOUS if MMU
81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
84 select HAVE_EXIT_THREAD
85 select HAVE_FAST_GUP if ARM_LPAE
86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
89 select HAVE_GCC_PLUGINS
90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
91 select HAVE_IDE if PCI || ISA || PCMCIA
92 select HAVE_IRQ_TIME_ACCOUNTING
93 select HAVE_KERNEL_GZIP
94 select HAVE_KERNEL_LZ4
95 select HAVE_KERNEL_LZMA
96 select HAVE_KERNEL_LZO
98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
99 select HAVE_KRETPROBES if HAVE_KPROBES
100 select HAVE_MOD_ARCH_SPECIFIC
102 select HAVE_OPROFILE if HAVE_PERF_EVENTS
103 select HAVE_OPTPROBES if !THUMB2_KERNEL
104 select HAVE_PERF_EVENTS
105 select HAVE_PERF_REGS
106 select HAVE_PERF_USER_STACK_DUMP
107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
108 select HAVE_REGS_AND_STACK_ACCESS_API
110 select HAVE_STACKPROTECTOR
111 select HAVE_SYSCALL_TRACEPOINTS
113 select HAVE_VIRT_CPU_ACCOUNTING_GEN
114 select IRQ_FORCED_THREADING
115 select MODULES_USE_ELF_REL
116 select NEED_DMA_MAP_STATE
117 select OF_EARLY_FLATTREE if OF
119 select OLD_SIGSUSPEND3
120 select PCI_SYSCALL if PCI
121 select PERF_USE_VMALLOC
124 select SYS_SUPPORTS_APM_EMULATION
125 # Above selects are sorted alphabetically; please add new ones
126 # according to that. Thanks.
128 The ARM series is a line of low-power-consumption RISC chip designs
129 licensed by ARM Ltd and targeted at embedded applications and
130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
131 manufactured, but legacy ARM-based PC hardware remains popular in
132 Europe. There is an ARM Linux project with a web page at
133 <http://www.arm.linux.org.uk/>.
135 config ARM_HAS_SG_CHAIN
138 config ARM_DMA_USE_IOMMU
140 select ARM_HAS_SG_CHAIN
141 select NEED_SG_DMA_LENGTH
145 config ARM_DMA_IOMMU_ALIGNMENT
146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
150 DMA mapping framework by default aligns all buffers to the smallest
151 PAGE_SIZE order which is greater than or equal to the requested buffer
152 size. This works well for buffers up to a few hundreds kilobytes, but
153 for larger buffers it just a waste of address space. Drivers which has
154 relatively small addressing window (like 64Mib) might run out of
155 virtual space with just a few allocations.
157 With this parameter you can specify the maximum PAGE_SIZE order for
158 DMA IOMMU buffers. Larger buffers will be aligned only to this
159 specified order. The order is expressed as a power of two multiplied
164 config SYS_SUPPORTS_APM_EMULATION
169 select GENERIC_ALLOCATOR
180 config STACKTRACE_SUPPORT
184 config LOCKDEP_SUPPORT
188 config TRACE_IRQFLAGS_SUPPORT
192 config ARCH_HAS_ILOG2_U32
195 config ARCH_HAS_ILOG2_U64
198 config ARCH_HAS_BANDGAP
201 config FIX_EARLYCON_MEM
204 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
212 config ARCH_MAY_HAVE_PC_FDC
218 config ARCH_SUPPORTS_UPROBES
221 config ARCH_HAS_DMA_SET_COHERENT_MASK
224 config GENERIC_ISA_DMA
230 config NEED_RET_TO_USER
236 config ARM_PATCH_PHYS_VIRT
237 bool "Patch physical to virtual translations at runtime" if EMBEDDED
239 depends on !XIP_KERNEL && MMU
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT
269 default DRAM_BASE if !MMU
270 default 0x00000000 if ARCH_EBSA110 || \
272 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
273 default 0x20000000 if ARCH_S5PV210
274 default 0xc0000000 if ARCH_SA1100
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 config PGTABLE_LEVELS
285 default 3 if ARM_LPAE
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
297 config ARCH_MMAP_RND_BITS_MIN
300 config ARCH_MMAP_RND_BITS_MAX
301 default 14 if PAGE_OFFSET=0x40000000
302 default 15 if PAGE_OFFSET=0x80000000
306 # The "ARM system type" choice list is ordered alphabetically by option
307 # text. Please add new entries in the option alphabetic order.
310 prompt "ARM system type"
311 default ARM_SINGLE_ARMV7M if !MMU
312 default ARCH_MULTIPLATFORM if MMU
314 config ARCH_MULTIPLATFORM
315 bool "Allow multiple platforms to be selected"
317 select ARCH_FLATMEM_ENABLE
318 select ARCH_SPARSEMEM_ENABLE
319 select ARCH_SELECT_MEMORY_MODEL
320 select ARM_HAS_SG_CHAIN
321 select ARM_PATCH_PHYS_VIRT
325 select GENERIC_CLOCKEVENTS
326 select GENERIC_IRQ_MULTI_HANDLER
328 select PCI_DOMAINS_GENERIC if PCI
332 config ARM_SINGLE_ARMV7M
333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
340 select GENERIC_CLOCKEVENTS
347 select ARCH_USES_GETTIMEOFFSET
350 select NEED_MACH_IO_H
351 select NEED_MACH_MEMORY_H
354 This is an evaluation board for the StrongARM processor available
355 from Digital. It has limited hardware on-board, including an
356 Ethernet interface, two PCMCIA sockets, two serial ports and a
361 select ARCH_SPARSEMEM_ENABLE
363 imply ARM_PATCH_PHYS_VIRT
369 select GENERIC_CLOCKEVENTS
371 select HAVE_LEGACY_CLK
373 This enables support for the Cirrus EP93xx series of CPUs.
375 config ARCH_FOOTBRIDGE
379 select GENERIC_CLOCKEVENTS
381 select NEED_MACH_IO_H if !MMU
382 select NEED_MACH_MEMORY_H
384 Support for systems based on the DC21285 companion chip
385 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
393 select NEED_RET_TO_USER
397 Support for Intel's 80219 and IOP32X (XScale) family of
403 select ARCH_HAS_DMA_SET_COHERENT_MASK
404 select ARCH_SUPPORTS_BIG_ENDIAN
406 select DMABOUNCE if PCI
407 select GENERIC_CLOCKEVENTS
408 select GENERIC_IRQ_MULTI_HANDLER
414 select NEED_MACH_IO_H
415 select USB_EHCI_BIG_ENDIAN_DESC
416 select USB_EHCI_BIG_ENDIAN_MMIO
418 Support for Intel's IXP4XX (XScale) family of processors.
423 select GENERIC_CLOCKEVENTS
424 select GENERIC_IRQ_MULTI_HANDLER
430 select PLAT_ORION_LEGACY
432 select PM_GENERIC_DOMAINS if PM
434 Support for the Marvell Dove SoC 88AP510
437 bool "PXA2xx/PXA3xx-based"
440 select ARM_CPU_SUSPEND if PM
446 select CPU_XSCALE if !CPU_XSC3
447 select GENERIC_CLOCKEVENTS
448 select GENERIC_IRQ_MULTI_HANDLER
456 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
462 select ARCH_MAY_HAVE_PC_FDC
463 select ARCH_SPARSEMEM_ENABLE
464 select ARM_HAS_SG_CHAIN
468 select HAVE_PATA_PLATFORM
470 select NEED_MACH_IO_H
471 select NEED_MACH_MEMORY_H
474 On the Acorn Risc-PC, Linux can support the internal IDE disk and
475 CD-ROM interface, serial and parallel port, and the floppy drive.
480 select ARCH_SPARSEMEM_ENABLE
483 select TIMER_OF if OF
487 select GENERIC_CLOCKEVENTS
488 select GENERIC_IRQ_MULTI_HANDLER
493 select NEED_MACH_MEMORY_H
496 Support for StrongARM 11x0 based boards.
499 bool "Samsung S3C24XX SoCs"
501 select CLKSRC_SAMSUNG_PWM
502 select GENERIC_CLOCKEVENTS
505 select GENERIC_IRQ_MULTI_HANDLER
506 select HAVE_S3C2410_I2C if I2C
507 select HAVE_S3C_RTC if RTC_CLASS
508 select NEED_MACH_IO_H
509 select S3C2410_WATCHDOG
514 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
515 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
516 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
517 Samsung SMDK2410 development board (and derivatives).
522 select ARCH_HAS_HOLES_MEMORYMODEL
526 select GENERIC_CLOCKEVENTS
527 select GENERIC_IRQ_CHIP
528 select GENERIC_IRQ_MULTI_HANDLER
531 select HAVE_LEGACY_CLK
533 select NEED_MACH_IO_H if PCCARD
534 select NEED_MACH_MEMORY_H
537 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
541 menu "Multiple platform selection"
542 depends on ARCH_MULTIPLATFORM
544 comment "CPU Core family selection"
547 bool "ARMv4 based platforms (FA526)"
548 depends on !ARCH_MULTI_V6_V7
549 select ARCH_MULTI_V4_V5
552 config ARCH_MULTI_V4T
553 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
554 depends on !ARCH_MULTI_V6_V7
555 select ARCH_MULTI_V4_V5
556 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
557 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
558 CPU_ARM925T || CPU_ARM940T)
561 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
562 depends on !ARCH_MULTI_V6_V7
563 select ARCH_MULTI_V4_V5
564 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
565 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
566 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
568 config ARCH_MULTI_V4_V5
572 bool "ARMv6 based platforms (ARM11)"
573 select ARCH_MULTI_V6_V7
577 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
579 select ARCH_MULTI_V6_V7
583 config ARCH_MULTI_V6_V7
585 select MIGHT_HAVE_CACHE_L2X0
587 config ARCH_MULTI_CPU_AUTO
588 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
594 bool "Dummy Virtual Machine"
595 depends on ARCH_MULTI_V7
598 select ARM_GIC_V2M if PCI
600 select ARM_GIC_V3_ITS if PCI
602 select HAVE_ARM_ARCH_TIMER
603 select ARCH_SUPPORTS_BIG_ENDIAN
606 # This is sorted alphabetically by mach-* pathname. However, plat-*
607 # Kconfigs may be included either alphabetically (according to the
608 # plat- suffix) or along side the corresponding mach-* source.
610 source "arch/arm/mach-actions/Kconfig"
612 source "arch/arm/mach-alpine/Kconfig"
614 source "arch/arm/mach-artpec/Kconfig"
616 source "arch/arm/mach-asm9260/Kconfig"
618 source "arch/arm/mach-aspeed/Kconfig"
620 source "arch/arm/mach-at91/Kconfig"
622 source "arch/arm/mach-axxia/Kconfig"
624 source "arch/arm/mach-bcm/Kconfig"
626 source "arch/arm/mach-berlin/Kconfig"
628 source "arch/arm/mach-clps711x/Kconfig"
630 source "arch/arm/mach-cns3xxx/Kconfig"
632 source "arch/arm/mach-davinci/Kconfig"
634 source "arch/arm/mach-digicolor/Kconfig"
636 source "arch/arm/mach-dove/Kconfig"
638 source "arch/arm/mach-ep93xx/Kconfig"
640 source "arch/arm/mach-exynos/Kconfig"
642 source "arch/arm/mach-footbridge/Kconfig"
644 source "arch/arm/mach-gemini/Kconfig"
646 source "arch/arm/mach-highbank/Kconfig"
648 source "arch/arm/mach-hisi/Kconfig"
650 source "arch/arm/mach-imx/Kconfig"
652 source "arch/arm/mach-integrator/Kconfig"
654 source "arch/arm/mach-iop32x/Kconfig"
656 source "arch/arm/mach-ixp4xx/Kconfig"
658 source "arch/arm/mach-keystone/Kconfig"
660 source "arch/arm/mach-lpc32xx/Kconfig"
662 source "arch/arm/mach-mediatek/Kconfig"
664 source "arch/arm/mach-meson/Kconfig"
666 source "arch/arm/mach-milbeaut/Kconfig"
668 source "arch/arm/mach-mmp/Kconfig"
670 source "arch/arm/mach-moxart/Kconfig"
672 source "arch/arm/mach-mstar/Kconfig"
674 source "arch/arm/mach-mv78xx0/Kconfig"
676 source "arch/arm/mach-mvebu/Kconfig"
678 source "arch/arm/mach-mxs/Kconfig"
680 source "arch/arm/mach-nomadik/Kconfig"
682 source "arch/arm/mach-npcm/Kconfig"
684 source "arch/arm/mach-nspire/Kconfig"
686 source "arch/arm/plat-omap/Kconfig"
688 source "arch/arm/mach-omap1/Kconfig"
690 source "arch/arm/mach-omap2/Kconfig"
692 source "arch/arm/mach-orion5x/Kconfig"
694 source "arch/arm/mach-oxnas/Kconfig"
696 source "arch/arm/mach-picoxcell/Kconfig"
698 source "arch/arm/mach-prima2/Kconfig"
700 source "arch/arm/mach-pxa/Kconfig"
701 source "arch/arm/plat-pxa/Kconfig"
703 source "arch/arm/mach-qcom/Kconfig"
705 source "arch/arm/mach-rda/Kconfig"
707 source "arch/arm/mach-realtek/Kconfig"
709 source "arch/arm/mach-realview/Kconfig"
711 source "arch/arm/mach-rockchip/Kconfig"
713 source "arch/arm/mach-s3c/Kconfig"
715 source "arch/arm/mach-s5pv210/Kconfig"
717 source "arch/arm/mach-sa1100/Kconfig"
719 source "arch/arm/mach-shmobile/Kconfig"
721 source "arch/arm/mach-socfpga/Kconfig"
723 source "arch/arm/mach-spear/Kconfig"
725 source "arch/arm/mach-sti/Kconfig"
727 source "arch/arm/mach-stm32/Kconfig"
729 source "arch/arm/mach-sunxi/Kconfig"
731 source "arch/arm/mach-tango/Kconfig"
733 source "arch/arm/mach-tegra/Kconfig"
735 source "arch/arm/mach-u300/Kconfig"
737 source "arch/arm/mach-uniphier/Kconfig"
739 source "arch/arm/mach-ux500/Kconfig"
741 source "arch/arm/mach-versatile/Kconfig"
743 source "arch/arm/mach-vexpress/Kconfig"
745 source "arch/arm/mach-vt8500/Kconfig"
747 source "arch/arm/mach-zx/Kconfig"
749 source "arch/arm/mach-zynq/Kconfig"
751 # ARMv7-M architecture
753 bool "Energy Micro efm32"
754 depends on ARM_SINGLE_ARMV7M
757 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
761 bool "NXP LPC18xx/LPC43xx"
762 depends on ARM_SINGLE_ARMV7M
763 select ARCH_HAS_RESET_CONTROLLER
765 select CLKSRC_LPC32XX
768 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
769 high performance microcontrollers.
772 bool "ARM MPS2 platform"
773 depends on ARM_SINGLE_ARMV7M
777 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
778 with a range of available cores like Cortex-M3/M4/M7.
780 Please, note that depends which Application Note is used memory map
781 for the platform may vary, so adjustment of RAM base might be needed.
783 # Definitions to make life easier
789 select GENERIC_CLOCKEVENTS
795 select GENERIC_IRQ_CHIP
798 config PLAT_ORION_LEGACY
805 config PLAT_VERSATILE
808 source "arch/arm/mm/Kconfig"
811 bool "Enable iWMMXt support"
812 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
813 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
815 Enable support for iWMMXt context switching at run time if
816 running on a CPU that supports it.
819 source "arch/arm/Kconfig-nommu"
822 config PJ4B_ERRATA_4742
823 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
824 depends on CPU_PJ4B && MACH_ARMADA_370
827 When coming out of either a Wait for Interrupt (WFI) or a Wait for
828 Event (WFE) IDLE states, a specific timing sensitivity exists between
829 the retiring WFI/WFE instructions and the newly issued subsequent
830 instructions. This sensitivity can result in a CPU hang scenario.
832 The software must insert either a Data Synchronization Barrier (DSB)
833 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
836 config ARM_ERRATA_326103
837 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
840 Executing a SWP instruction to read-only memory does not set bit 11
841 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
842 treat the access as a read, preventing a COW from occurring and
843 causing the faulting task to livelock.
845 config ARM_ERRATA_411920
846 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
847 depends on CPU_V6 || CPU_V6K
849 Invalidation of the Instruction Cache operation can
850 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
851 It does not affect the MPCore. This option enables the ARM Ltd.
852 recommended workaround.
854 config ARM_ERRATA_430973
855 bool "ARM errata: Stale prediction on replaced interworking branch"
858 This option enables the workaround for the 430973 Cortex-A8
859 r1p* erratum. If a code sequence containing an ARM/Thumb
860 interworking branch is replaced with another code sequence at the
861 same virtual address, whether due to self-modifying code or virtual
862 to physical address re-mapping, Cortex-A8 does not recover from the
863 stale interworking branch prediction. This results in Cortex-A8
864 executing the new code sequence in the incorrect ARM or Thumb state.
865 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
866 and also flushes the branch target cache at every context switch.
867 Note that setting specific bits in the ACTLR register may not be
868 available in non-secure mode.
870 config ARM_ERRATA_458693
871 bool "ARM errata: Processor deadlock when a false hazard is created"
873 depends on !ARCH_MULTIPLATFORM
875 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
876 erratum. For very specific sequences of memory operations, it is
877 possible for a hazard condition intended for a cache line to instead
878 be incorrectly associated with a different cache line. This false
879 hazard might then cause a processor deadlock. The workaround enables
880 the L1 caching of the NEON accesses and disables the PLD instruction
881 in the ACTLR register. Note that setting specific bits in the ACTLR
882 register may not be available in non-secure mode.
884 config ARM_ERRATA_460075
885 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
887 depends on !ARCH_MULTIPLATFORM
889 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
890 erratum. Any asynchronous access to the L2 cache may encounter a
891 situation in which recent store transactions to the L2 cache are lost
892 and overwritten with stale memory contents from external memory. The
893 workaround disables the write-allocate mode for the L2 cache via the
894 ACTLR register. Note that setting specific bits in the ACTLR register
895 may not be available in non-secure mode.
897 config ARM_ERRATA_742230
898 bool "ARM errata: DMB operation may be faulty"
899 depends on CPU_V7 && SMP
900 depends on !ARCH_MULTIPLATFORM
902 This option enables the workaround for the 742230 Cortex-A9
903 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
904 between two write operations may not ensure the correct visibility
905 ordering of the two writes. This workaround sets a specific bit in
906 the diagnostic register of the Cortex-A9 which causes the DMB
907 instruction to behave as a DSB, ensuring the correct behaviour of
910 config ARM_ERRATA_742231
911 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
912 depends on CPU_V7 && SMP
913 depends on !ARCH_MULTIPLATFORM
915 This option enables the workaround for the 742231 Cortex-A9
916 (r2p0..r2p2) erratum. Under certain conditions, specific to the
917 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
918 accessing some data located in the same cache line, may get corrupted
919 data due to bad handling of the address hazard when the line gets
920 replaced from one of the CPUs at the same time as another CPU is
921 accessing it. This workaround sets specific bits in the diagnostic
922 register of the Cortex-A9 which reduces the linefill issuing
923 capabilities of the processor.
925 config ARM_ERRATA_643719
926 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
927 depends on CPU_V7 && SMP
930 This option enables the workaround for the 643719 Cortex-A9 (prior to
931 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
932 register returns zero when it should return one. The workaround
933 corrects this value, ensuring cache maintenance operations which use
934 it behave as intended and avoiding data corruption.
936 config ARM_ERRATA_720789
937 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
940 This option enables the workaround for the 720789 Cortex-A9 (prior to
941 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
942 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
943 As a consequence of this erratum, some TLB entries which should be
944 invalidated are not, resulting in an incoherency in the system page
945 tables. The workaround changes the TLB flushing routines to invalidate
946 entries regardless of the ASID.
948 config ARM_ERRATA_743622
949 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
951 depends on !ARCH_MULTIPLATFORM
953 This option enables the workaround for the 743622 Cortex-A9
954 (r2p*) erratum. Under very rare conditions, a faulty
955 optimisation in the Cortex-A9 Store Buffer may lead to data
956 corruption. This workaround sets a specific bit in the diagnostic
957 register of the Cortex-A9 which disables the Store Buffer
958 optimisation, preventing the defect from occurring. This has no
959 visible impact on the overall performance or power consumption of the
962 config ARM_ERRATA_751472
963 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
965 depends on !ARCH_MULTIPLATFORM
967 This option enables the workaround for the 751472 Cortex-A9 (prior
968 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
969 completion of a following broadcasted operation if the second
970 operation is received by a CPU before the ICIALLUIS has completed,
971 potentially leading to corrupted entries in the cache or TLB.
973 config ARM_ERRATA_754322
974 bool "ARM errata: possible faulty MMU translations following an ASID switch"
977 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
978 r3p*) erratum. A speculative memory access may cause a page table walk
979 which starts prior to an ASID switch but completes afterwards. This
980 can populate the micro-TLB with a stale entry which may be hit with
981 the new ASID. This workaround places two dsb instructions in the mm
982 switching code so that no page table walks can cross the ASID switch.
984 config ARM_ERRATA_754327
985 bool "ARM errata: no automatic Store Buffer drain"
986 depends on CPU_V7 && SMP
988 This option enables the workaround for the 754327 Cortex-A9 (prior to
989 r2p0) erratum. The Store Buffer does not have any automatic draining
990 mechanism and therefore a livelock may occur if an external agent
991 continuously polls a memory location waiting to observe an update.
992 This workaround defines cpu_relax() as smp_mb(), preventing correctly
993 written polling loops from denying visibility of updates to memory.
995 config ARM_ERRATA_364296
996 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
999 This options enables the workaround for the 364296 ARM1136
1000 r0p2 erratum (possible cache data corruption with
1001 hit-under-miss enabled). It sets the undocumented bit 31 in
1002 the auxiliary control register and the FI bit in the control
1003 register, thus disabling hit-under-miss without putting the
1004 processor into full low interrupt latency mode. ARM11MPCore
1007 config ARM_ERRATA_764369
1008 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1009 depends on CPU_V7 && SMP
1011 This option enables the workaround for erratum 764369
1012 affecting Cortex-A9 MPCore with two or more processors (all
1013 current revisions). Under certain timing circumstances, a data
1014 cache line maintenance operation by MVA targeting an Inner
1015 Shareable memory region may fail to proceed up to either the
1016 Point of Coherency or to the Point of Unification of the
1017 system. This workaround adds a DSB instruction before the
1018 relevant cache maintenance functions and sets a specific bit
1019 in the diagnostic control register of the SCU.
1021 config ARM_ERRATA_775420
1022 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1025 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1026 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1027 operation aborts with MMU exception, it might cause the processor
1028 to deadlock. This workaround puts DSB before executing ISB if
1029 an abort may occur on cache maintenance.
1031 config ARM_ERRATA_798181
1032 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1033 depends on CPU_V7 && SMP
1035 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1036 adequately shooting down all use of the old entries. This
1037 option enables the Linux kernel workaround for this erratum
1038 which sends an IPI to the CPUs that are running the same ASID
1039 as the one being invalidated.
1041 config ARM_ERRATA_773022
1042 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1045 This option enables the workaround for the 773022 Cortex-A15
1046 (up to r0p4) erratum. In certain rare sequences of code, the
1047 loop buffer may deliver incorrect instructions. This
1048 workaround disables the loop buffer to avoid the erratum.
1050 config ARM_ERRATA_818325_852422
1051 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1054 This option enables the workaround for:
1055 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1056 instruction might deadlock. Fixed in r0p1.
1057 - Cortex-A12 852422: Execution of a sequence of instructions might
1058 lead to either a data corruption or a CPU deadlock. Not fixed in
1059 any Cortex-A12 cores yet.
1060 This workaround for all both errata involves setting bit[12] of the
1061 Feature Register. This bit disables an optimisation applied to a
1062 sequence of 2 instructions that use opposing condition codes.
1064 config ARM_ERRATA_821420
1065 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1068 This option enables the workaround for the 821420 Cortex-A12
1069 (all revs) erratum. In very rare timing conditions, a sequence
1070 of VMOV to Core registers instructions, for which the second
1071 one is in the shadow of a branch or abort, can lead to a
1072 deadlock when the VMOV instructions are issued out-of-order.
1074 config ARM_ERRATA_825619
1075 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1078 This option enables the workaround for the 825619 Cortex-A12
1079 (all revs) erratum. Within rare timing constraints, executing a
1080 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1081 and Device/Strongly-Ordered loads and stores might cause deadlock
1083 config ARM_ERRATA_857271
1084 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1087 This option enables the workaround for the 857271 Cortex-A12
1088 (all revs) erratum. Under very rare timing conditions, the CPU might
1089 hang. The workaround is expected to have a < 1% performance impact.
1091 config ARM_ERRATA_852421
1092 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1095 This option enables the workaround for the 852421 Cortex-A17
1096 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1097 execution of a DMB ST instruction might fail to properly order
1098 stores from GroupA and stores from GroupB.
1100 config ARM_ERRATA_852423
1101 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1104 This option enables the workaround for:
1105 - Cortex-A17 852423: Execution of a sequence of instructions might
1106 lead to either a data corruption or a CPU deadlock. Not fixed in
1107 any Cortex-A17 cores yet.
1108 This is identical to Cortex-A12 erratum 852422. It is a separate
1109 config option from the A12 erratum due to the way errata are checked
1112 config ARM_ERRATA_857272
1113 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1116 This option enables the workaround for the 857272 Cortex-A17 erratum.
1117 This erratum is not known to be fixed in any A17 revision.
1118 This is identical to Cortex-A12 erratum 857271. It is a separate
1119 config option from the A12 erratum due to the way errata are checked
1124 source "arch/arm/common/Kconfig"
1131 Find out whether you have ISA slots on your motherboard. ISA is the
1132 name of a bus system, i.e. the way the CPU talks to the other stuff
1133 inside your box. Other bus systems are PCI, EISA, MicroChannel
1134 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1135 newer boards don't support it. If you have ISA, say Y, otherwise N.
1137 # Select ISA DMA controller support
1142 # Select ISA DMA interface
1146 config PCI_NANOENGINE
1147 bool "BSE nanoEngine PCI support"
1148 depends on SA1100_NANOENGINE
1150 Enable PCI on the BSE nanoEngine board.
1152 config ARM_ERRATA_814220
1153 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1156 The v7 ARM states that all cache and branch predictor maintenance
1157 operations that do not specify an address execute, relative to
1158 each other, in program order.
1159 However, because of this erratum, an L2 set/way cache maintenance
1160 operation can overtake an L1 set/way cache maintenance operation.
1161 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1166 menu "Kernel Features"
1171 This option should be selected by machines which have an SMP-
1174 The only effect of this option is to make the SMP-related
1175 options available to the user for configuration.
1178 bool "Symmetric Multi-Processing"
1179 depends on CPU_V6K || CPU_V7
1180 depends on GENERIC_CLOCKEVENTS
1182 depends on MMU || ARM_MPU
1185 This enables support for systems with more than one CPU. If you have
1186 a system with only one CPU, say N. If you have a system with more
1187 than one CPU, say Y.
1189 If you say N here, the kernel will run on uni- and multiprocessor
1190 machines, but will use only one CPU of a multiprocessor machine. If
1191 you say Y here, the kernel will run on many, but not all,
1192 uniprocessor machines. On a uniprocessor machine, the kernel
1193 will run faster if you say N here.
1195 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1196 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1197 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1199 If you don't know what to do here, say N.
1202 bool "Allow booting SMP kernel on uniprocessor systems"
1203 depends on SMP && !XIP_KERNEL && MMU
1206 SMP kernels contain instructions which fail on non-SMP processors.
1207 Enabling this option allows the kernel to modify itself to make
1208 these instructions safe. Disabling it allows about 1K of space
1211 If you don't know what to do here, say Y.
1213 config ARM_CPU_TOPOLOGY
1214 bool "Support cpu topology definition"
1215 depends on SMP && CPU_V7
1218 Support ARM cpu topology definition. The MPIDR register defines
1219 affinity between processors which is then used to describe the cpu
1220 topology of an ARM System.
1223 bool "Multi-core scheduler support"
1224 depends on ARM_CPU_TOPOLOGY
1226 Multi-core scheduler support improves the CPU scheduler's decision
1227 making when dealing with multi-core CPU chips at a cost of slightly
1228 increased overhead in some places. If unsure say N here.
1231 bool "SMT scheduler support"
1232 depends on ARM_CPU_TOPOLOGY
1234 Improves the CPU scheduler's decision making when dealing with
1235 MultiThreading at a cost of slightly increased overhead in some
1236 places. If unsure say N here.
1241 This option enables support for the ARM snoop control unit
1243 config HAVE_ARM_ARCH_TIMER
1244 bool "Architected timer support"
1246 select ARM_ARCH_TIMER
1248 This option enables support for the ARM architected timer
1253 This options enables support for the ARM timer and watchdog unit
1256 bool "Multi-Cluster Power Management"
1257 depends on CPU_V7 && SMP
1259 This option provides the common power management infrastructure
1260 for (multi-)cluster based systems, such as big.LITTLE based
1263 config MCPM_QUAD_CLUSTER
1267 To avoid wasting resources unnecessarily, MCPM only supports up
1268 to 2 clusters by default.
1269 Platforms with 3 or 4 clusters that use MCPM must select this
1270 option to allow the additional clusters to be managed.
1273 bool "big.LITTLE support (Experimental)"
1274 depends on CPU_V7 && SMP
1277 This option enables support selections for the big.LITTLE
1278 system architecture.
1281 bool "big.LITTLE switcher support"
1282 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1285 The big.LITTLE "switcher" provides the core functionality to
1286 transparently handle transition between a cluster of A15's
1287 and a cluster of A7's in a big.LITTLE system.
1289 config BL_SWITCHER_DUMMY_IF
1290 tristate "Simple big.LITTLE switcher user interface"
1291 depends on BL_SWITCHER && DEBUG_KERNEL
1293 This is a simple and dummy char dev interface to control
1294 the big.LITTLE switcher core code. It is meant for
1295 debugging purposes only.
1298 prompt "Memory split"
1302 Select the desired split between kernel and user memory.
1304 If you are not absolutely sure what you are doing, leave this
1308 bool "3G/1G user/kernel split"
1309 config VMSPLIT_3G_OPT
1310 depends on !ARM_LPAE
1311 bool "3G/1G user/kernel split (for full 1G low memory)"
1313 bool "2G/2G user/kernel split"
1315 bool "1G/3G user/kernel split"
1320 default PHYS_OFFSET if !MMU
1321 default 0x40000000 if VMSPLIT_1G
1322 default 0x80000000 if VMSPLIT_2G
1323 default 0xB0000000 if VMSPLIT_3G_OPT
1327 int "Maximum number of CPUs (2-32)"
1333 bool "Support for hot-pluggable CPUs"
1335 select GENERIC_IRQ_MIGRATION
1337 Say Y here to experiment with turning CPUs off and on. CPUs
1338 can be controlled through /sys/devices/system/cpu.
1341 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1342 depends on HAVE_ARM_SMCCC
1345 Say Y here if you want Linux to communicate with system firmware
1346 implementing the PSCI specification for CPU-centric power
1347 management operations described in ARM document number ARM DEN
1348 0022A ("Power State Coordination Interface System Software on
1351 # The GPIO number here must be sorted by descending number. In case of
1352 # a multiplatform kernel, we just want the highest value required by the
1353 # selected platforms.
1356 default 2048 if ARCH_SOCFPGA
1357 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1358 ARCH_ZYNQ || ARCH_ASPEED
1359 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1360 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1361 default 416 if ARCH_SUNXI
1362 default 392 if ARCH_U8500
1363 default 352 if ARCH_VT8500
1364 default 288 if ARCH_ROCKCHIP
1365 default 264 if MACH_H4700
1368 Maximum number of GPIOs in the system.
1370 If unsure, leave the default value.
1374 default 200 if ARCH_EBSA110
1375 default 128 if SOC_AT91RM9200
1379 depends on HZ_FIXED = 0
1380 prompt "Timer frequency"
1404 default HZ_FIXED if HZ_FIXED != 0
1405 default 100 if HZ_100
1406 default 200 if HZ_200
1407 default 250 if HZ_250
1408 default 300 if HZ_300
1409 default 500 if HZ_500
1413 def_bool HIGH_RES_TIMERS
1415 config THUMB2_KERNEL
1416 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1417 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1418 default y if CPU_THUMBONLY
1421 By enabling this option, the kernel will be compiled in
1426 config ARM_PATCH_IDIV
1427 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1428 depends on CPU_32v7 && !XIP_KERNEL
1431 The ARM compiler inserts calls to __aeabi_idiv() and
1432 __aeabi_uidiv() when it needs to perform division on signed
1433 and unsigned integers. Some v7 CPUs have support for the sdiv
1434 and udiv instructions that can be used to implement those
1437 Enabling this option allows the kernel to modify itself to
1438 replace the first two instructions of these library functions
1439 with the sdiv or udiv plus "bx lr" instructions when the CPU
1440 it is running on supports them. Typically this will be faster
1441 and less power intensive than running the original library
1442 code to do integer division.
1445 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1446 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1447 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1449 This option allows for the kernel to be compiled using the latest
1450 ARM ABI (aka EABI). This is only useful if you are using a user
1451 space environment that is also compiled with EABI.
1453 Since there are major incompatibilities between the legacy ABI and
1454 EABI, especially with regard to structure member alignment, this
1455 option also changes the kernel syscall calling convention to
1456 disambiguate both ABIs and allow for backward compatibility support
1457 (selected with CONFIG_OABI_COMPAT).
1459 To use this you need GCC version 4.0.0 or later.
1462 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1463 depends on AEABI && !THUMB2_KERNEL
1465 This option preserves the old syscall interface along with the
1466 new (ARM EABI) one. It also provides a compatibility layer to
1467 intercept syscalls that have structure arguments which layout
1468 in memory differs between the legacy ABI and the new ARM EABI
1469 (only for non "thumb" binaries). This option adds a tiny
1470 overhead to all syscalls and produces a slightly larger kernel.
1472 The seccomp filter system will not be available when this is
1473 selected, since there is no way yet to sensibly distinguish
1474 between calling conventions during filtering.
1476 If you know you'll be using only pure EABI user space then you
1477 can say N here. If this option is not selected and you attempt
1478 to execute a legacy ABI binary then the result will be
1479 UNPREDICTABLE (in fact it can be predicted that it won't work
1480 at all). If in doubt say N.
1482 config ARCH_HAS_HOLES_MEMORYMODEL
1485 config ARCH_SELECT_MEMORY_MODEL
1488 config ARCH_FLATMEM_ENABLE
1491 config ARCH_SPARSEMEM_ENABLE
1493 select SPARSEMEM_STATIC if SPARSEMEM
1495 config HAVE_ARCH_PFN_VALID
1496 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1499 bool "High Memory Support"
1502 The address space of ARM processors is only 4 Gigabytes large
1503 and it has to accommodate user address space, kernel address
1504 space as well as some memory mapped IO. That means that, if you
1505 have a large amount of physical memory and/or IO, not all of the
1506 memory can be "permanently mapped" by the kernel. The physical
1507 memory that is not permanently mapped is called "high memory".
1509 Depending on the selected kernel/user memory split, minimum
1510 vmalloc space and actual amount of RAM, you may not need this
1511 option which should result in a slightly faster kernel.
1516 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1520 The VM uses one page of physical memory for each page table.
1521 For systems with a lot of processes, this can use a lot of
1522 precious low memory, eventually leading to low memory being
1523 consumed by page tables. Setting this option will allow
1524 user-space 2nd level page tables to reside in high memory.
1526 config CPU_SW_DOMAIN_PAN
1527 bool "Enable use of CPU domains to implement privileged no-access"
1528 depends on MMU && !ARM_LPAE
1531 Increase kernel security by ensuring that normal kernel accesses
1532 are unable to access userspace addresses. This can help prevent
1533 use-after-free bugs becoming an exploitable privilege escalation
1534 by ensuring that magic values (such as LIST_POISON) will always
1535 fault when dereferenced.
1537 CPUs with low-vector mappings use a best-efforts implementation.
1538 Their lower 1MB needs to remain accessible for the vectors, but
1539 the remainder of userspace will become appropriately inaccessible.
1541 config HW_PERF_EVENTS
1545 config SYS_SUPPORTS_HUGETLBFS
1549 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1553 config ARCH_WANT_GENERAL_HUGETLB
1556 config ARM_MODULE_PLTS
1557 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1561 Allocate PLTs when loading modules so that jumps and calls whose
1562 targets are too far away for their relative offsets to be encoded
1563 in the instructions themselves can be bounced via veneers in the
1564 module's PLT. This allows modules to be allocated in the generic
1565 vmalloc area after the dedicated module memory area has been
1566 exhausted. The modules will use slightly more memory, but after
1567 rounding up to page size, the actual memory footprint is usually
1570 Disabling this is usually safe for small single-platform
1571 configurations. If unsure, say y.
1573 config FORCE_MAX_ZONEORDER
1574 int "Maximum zone order"
1575 default "12" if SOC_AM33XX
1576 default "9" if SA1111 || ARCH_EFM32
1579 The kernel memory allocator divides physically contiguous memory
1580 blocks into "zones", where each zone is a power of two number of
1581 pages. This option selects the largest power of two that the kernel
1582 keeps in the memory allocator. If you need to allocate very large
1583 blocks of physically contiguous memory, then you may need to
1584 increase this value.
1586 This config option is actually maximum order plus one. For example,
1587 a value of 11 means that the largest free memory block is 2^10 pages.
1589 config ALIGNMENT_TRAP
1591 depends on CPU_CP15_MMU
1592 default y if !ARCH_EBSA110
1593 select HAVE_PROC_CPU if PROC_FS
1595 ARM processors cannot fetch/store information which is not
1596 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1597 address divisible by 4. On 32-bit ARM processors, these non-aligned
1598 fetch/store instructions will be emulated in software if you say
1599 here, which has a severe performance impact. This is necessary for
1600 correct operation of some network protocols. With an IP-only
1601 configuration it is safe to say N, otherwise say Y.
1603 config UACCESS_WITH_MEMCPY
1604 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1606 default y if CPU_FEROCEON
1608 Implement faster copy_to_user and clear_user methods for CPU
1609 cores where a 8-word STM instruction give significantly higher
1610 memory write throughput than a sequence of individual 32bit stores.
1612 A possible side effect is a slight increase in scheduling latency
1613 between threads sharing the same address space if they invoke
1614 such copy operations with large buffers.
1616 However, if the CPU data cache is using a write-allocate mode,
1617 this option is unlikely to provide any performance gain.
1620 bool "Enable paravirtualization code"
1622 This changes the kernel so it can modify itself when it is run
1623 under a hypervisor, potentially improving performance significantly
1624 over full virtualization.
1626 config PARAVIRT_TIME_ACCOUNTING
1627 bool "Paravirtual steal time accounting"
1630 Select this option to enable fine granularity task steal time
1631 accounting. Time spent executing other tasks in parallel with
1632 the current vCPU is discounted from the vCPU power. To account for
1633 that, there can be a small performance impact.
1635 If in doubt, say N here.
1642 bool "Xen guest support on ARM"
1643 depends on ARM && AEABI && OF
1644 depends on CPU_V7 && !CPU_V6
1645 depends on !GENERIC_ATOMIC64
1647 select ARCH_DMA_ADDR_T_64BIT
1653 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1655 config STACKPROTECTOR_PER_TASK
1656 bool "Use a unique stack canary value for each task"
1657 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1658 select GCC_PLUGIN_ARM_SSP_PER_TASK
1661 Due to the fact that GCC uses an ordinary symbol reference from
1662 which to load the value of the stack canary, this value can only
1663 change at reboot time on SMP systems, and all tasks running in the
1664 kernel's address space are forced to use the same canary value for
1665 the entire duration that the system is up.
1667 Enable this option to switch to a different method that uses a
1668 different canary value for each task.
1675 bool "Flattened Device Tree support"
1679 Include support for flattened device tree machine descriptions.
1682 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1685 This is the traditional way of passing data to the kernel at boot
1686 time. If you are solely relying on the flattened device tree (or
1687 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1688 to remove ATAGS support from your kernel binary. If unsure,
1691 config DEPRECATED_PARAM_STRUCT
1692 bool "Provide old way to pass kernel parameters"
1695 This was deprecated in 2001 and announced to live on for 5 years.
1696 Some old boot loaders still use this way.
1698 # Compressed boot loader in ROM. Yes, we really want to ask about
1699 # TEXT and BSS so we preserve their values in the config files.
1700 config ZBOOT_ROM_TEXT
1701 hex "Compressed ROM boot loader base address"
1704 The physical address at which the ROM-able zImage is to be
1705 placed in the target. Platforms which normally make use of
1706 ROM-able zImage formats normally set this to a suitable
1707 value in their defconfig file.
1709 If ZBOOT_ROM is not enabled, this has no effect.
1711 config ZBOOT_ROM_BSS
1712 hex "Compressed ROM boot loader BSS address"
1715 The base address of an area of read/write memory in the target
1716 for the ROM-able zImage which must be available while the
1717 decompressor is running. It must be large enough to hold the
1718 entire decompressed kernel plus an additional 128 KiB.
1719 Platforms which normally make use of ROM-able zImage formats
1720 normally set this to a suitable value in their defconfig file.
1722 If ZBOOT_ROM is not enabled, this has no effect.
1725 bool "Compressed boot loader in ROM/flash"
1726 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1727 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1729 Say Y here if you intend to execute your compressed kernel image
1730 (zImage) directly from ROM or flash. If unsure, say N.
1732 config ARM_APPENDED_DTB
1733 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1736 With this option, the boot code will look for a device tree binary
1737 (DTB) appended to zImage
1738 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1740 This is meant as a backward compatibility convenience for those
1741 systems with a bootloader that can't be upgraded to accommodate
1742 the documented boot protocol using a device tree.
1744 Beware that there is very little in terms of protection against
1745 this option being confused by leftover garbage in memory that might
1746 look like a DTB header after a reboot if no actual DTB is appended
1747 to zImage. Do not leave this option active in a production kernel
1748 if you don't intend to always append a DTB. Proper passing of the
1749 location into r2 of a bootloader provided DTB is always preferable
1752 config ARM_ATAG_DTB_COMPAT
1753 bool "Supplement the appended DTB with traditional ATAG information"
1754 depends on ARM_APPENDED_DTB
1756 Some old bootloaders can't be updated to a DTB capable one, yet
1757 they provide ATAGs with memory configuration, the ramdisk address,
1758 the kernel cmdline string, etc. Such information is dynamically
1759 provided by the bootloader and can't always be stored in a static
1760 DTB. To allow a device tree enabled kernel to be used with such
1761 bootloaders, this option allows zImage to extract the information
1762 from the ATAG list and store it at run time into the appended DTB.
1765 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1766 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1768 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1769 bool "Use bootloader kernel arguments if available"
1771 Uses the command-line options passed by the boot loader instead of
1772 the device tree bootargs property. If the boot loader doesn't provide
1773 any, the device tree bootargs property will be used.
1775 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1776 bool "Extend with bootloader kernel arguments"
1778 The command-line arguments provided by the boot loader will be
1779 appended to the the device tree bootargs property.
1784 string "Default kernel command string"
1787 On some architectures (EBSA110 and CATS), there is currently no way
1788 for the boot loader to pass arguments to the kernel. For these
1789 architectures, you should supply some command-line options at build
1790 time by entering them here. As a minimum, you should specify the
1791 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1794 prompt "Kernel command line type" if CMDLINE != ""
1795 default CMDLINE_FROM_BOOTLOADER
1798 config CMDLINE_FROM_BOOTLOADER
1799 bool "Use bootloader kernel arguments if available"
1801 Uses the command-line options passed by the boot loader. If
1802 the boot loader doesn't provide any, the default kernel command
1803 string provided in CMDLINE will be used.
1805 config CMDLINE_EXTEND
1806 bool "Extend bootloader kernel arguments"
1808 The command-line arguments provided by the boot loader will be
1809 appended to the default kernel command string.
1811 config CMDLINE_FORCE
1812 bool "Always use the default kernel command string"
1814 Always use the default kernel command string, even if the boot
1815 loader passes other arguments to the kernel.
1816 This is useful if you cannot or don't want to change the
1817 command-line options your boot loader passes to the kernel.
1821 bool "Kernel Execute-In-Place from ROM"
1822 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1824 Execute-In-Place allows the kernel to run from non-volatile storage
1825 directly addressable by the CPU, such as NOR flash. This saves RAM
1826 space since the text section of the kernel is not loaded from flash
1827 to RAM. Read-write sections, such as the data section and stack,
1828 are still copied to RAM. The XIP kernel is not compressed since
1829 it has to run directly from flash, so it will take more space to
1830 store it. The flash address used to link the kernel object files,
1831 and for storing it, is configuration dependent. Therefore, if you
1832 say Y here, you must know the proper physical address where to
1833 store the kernel image depending on your own flash memory usage.
1835 Also note that the make target becomes "make xipImage" rather than
1836 "make zImage" or "make Image". The final kernel binary to put in
1837 ROM memory will be arch/arm/boot/xipImage.
1841 config XIP_PHYS_ADDR
1842 hex "XIP Kernel Physical Location"
1843 depends on XIP_KERNEL
1844 default "0x00080000"
1846 This is the physical address in your flash memory the kernel will
1847 be linked for and stored to. This address is dependent on your
1850 config XIP_DEFLATED_DATA
1851 bool "Store kernel .data section compressed in ROM"
1852 depends on XIP_KERNEL
1855 Before the kernel is actually executed, its .data section has to be
1856 copied to RAM from ROM. This option allows for storing that data
1857 in compressed form and decompressed to RAM rather than merely being
1858 copied, saving some precious ROM space. A possible drawback is a
1859 slightly longer boot delay.
1862 bool "Kexec system call (EXPERIMENTAL)"
1863 depends on (!SMP || PM_SLEEP_SMP)
1867 kexec is a system call that implements the ability to shutdown your
1868 current kernel, and to start another kernel. It is like a reboot
1869 but it is independent of the system firmware. And like a reboot
1870 you can start any kernel with it, not just Linux.
1872 It is an ongoing process to be certain the hardware in a machine
1873 is properly shutdown, so do not be surprised if this code does not
1874 initially work for you.
1877 bool "Export atags in procfs"
1878 depends on ATAGS && KEXEC
1881 Should the atags used to boot the kernel be exported in an "atags"
1882 file in procfs. Useful with kexec.
1885 bool "Build kdump crash kernel (EXPERIMENTAL)"
1887 Generate crash dump after being started by kexec. This should
1888 be normally only set in special crash dump kernels which are
1889 loaded in the main kernel with kexec-tools into a specially
1890 reserved region and then later executed after a crash by
1891 kdump/kexec. The crash dump kernel must be compiled to a
1892 memory address not used by the main kernel
1894 For more details see Documentation/admin-guide/kdump/kdump.rst
1896 config AUTO_ZRELADDR
1897 bool "Auto calculation of the decompressed kernel image address"
1899 ZRELADDR is the physical address where the decompressed kernel
1900 image will be placed. If AUTO_ZRELADDR is selected, the address
1901 will be determined at run-time by masking the current IP with
1902 0xf8000000. This assumes the zImage being placed in the first 128MB
1903 from start of memory.
1909 bool "UEFI runtime support"
1910 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1912 select EFI_PARAMS_FROM_FDT
1914 select EFI_GENERIC_STUB
1915 select EFI_RUNTIME_WRAPPERS
1917 This option provides support for runtime services provided
1918 by UEFI firmware (such as non-volatile variables, realtime
1919 clock, and platform reset). A UEFI stub is also provided to
1920 allow the kernel to be booted as an EFI application. This
1921 is only useful for kernels that may run on systems that have
1925 bool "Enable support for SMBIOS (DMI) tables"
1929 This enables SMBIOS/DMI feature for systems.
1931 This option is only useful on systems that have UEFI firmware.
1932 However, even with this option, the resultant kernel should
1933 continue to boot on existing non-UEFI platforms.
1935 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1936 i.e., the the practice of identifying the platform via DMI to
1937 decide whether certain workarounds for buggy hardware and/or
1938 firmware need to be enabled. This would require the DMI subsystem
1939 to be enabled much earlier than we do on ARM, which is non-trivial.
1943 menu "CPU Power Management"
1945 source "drivers/cpufreq/Kconfig"
1947 source "drivers/cpuidle/Kconfig"
1951 menu "Floating point emulation"
1953 comment "At least one emulation must be selected"
1956 bool "NWFPE math emulation"
1957 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1959 Say Y to include the NWFPE floating point emulator in the kernel.
1960 This is necessary to run most binaries. Linux does not currently
1961 support floating point hardware so you need to say Y here even if
1962 your machine has an FPA or floating point co-processor podule.
1964 You may say N here if you are going to load the Acorn FPEmulator
1965 early in the bootup.
1968 bool "Support extended precision"
1969 depends on FPE_NWFPE
1971 Say Y to include 80-bit support in the kernel floating-point
1972 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1973 Note that gcc does not generate 80-bit operations by default,
1974 so in most cases this option only enlarges the size of the
1975 floating point emulator without any good reason.
1977 You almost surely want to say N here.
1980 bool "FastFPE math emulation (EXPERIMENTAL)"
1981 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1983 Say Y here to include the FAST floating point emulator in the kernel.
1984 This is an experimental much faster emulator which now also has full
1985 precision for the mantissa. It does not support any exceptions.
1986 It is very simple, and approximately 3-6 times faster than NWFPE.
1988 It should be sufficient for most programs. It may be not suitable
1989 for scientific calculations, but you have to check this for yourself.
1990 If you do not feel you need a faster FP emulation you should better
1994 bool "VFP-format floating point maths"
1995 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1997 Say Y to include VFP support code in the kernel. This is needed
1998 if your hardware includes a VFP unit.
2000 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2001 release notes and additional status information.
2003 Say N if your target does not have VFP hardware.
2011 bool "Advanced SIMD (NEON) Extension support"
2012 depends on VFPv3 && CPU_V7
2014 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2017 config KERNEL_MODE_NEON
2018 bool "Support for NEON in kernel mode"
2019 depends on NEON && AEABI
2021 Say Y to include support for NEON in kernel mode.
2025 menu "Power management options"
2027 source "kernel/power/Kconfig"
2029 config ARCH_SUSPEND_POSSIBLE
2030 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2031 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2034 config ARM_CPU_SUSPEND
2035 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2036 depends on ARCH_SUSPEND_POSSIBLE
2038 config ARCH_HIBERNATION_POSSIBLE
2041 default y if ARCH_SUSPEND_POSSIBLE
2045 source "drivers/firmware/Kconfig"
2048 source "arch/arm/crypto/Kconfig"
2051 source "arch/arm/Kconfig.assembler"