1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
48 select DMA_REMAP if MMU
50 select EDAC_ATOMIC_SCRUB
51 select GENERIC_ALLOCATOR
52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
55 select GENERIC_IRQ_IPI if SMP
56 select GENERIC_CPU_AUTOPROBE
57 select GENERIC_EARLY_IOREMAP
58 select GENERIC_IDLE_POLL_SETUP
59 select GENERIC_IRQ_PROBE
60 select GENERIC_IRQ_SHOW
61 select GENERIC_IRQ_SHOW_LEVEL
62 select GENERIC_LIB_DEVMEM_IS_ALLOWED
63 select GENERIC_PCI_IOMAP
64 select GENERIC_SCHED_CLOCK
65 select GENERIC_SMP_IDLE_THREAD
66 select GENERIC_STRNCPY_FROM_USER
67 select GENERIC_STRNLEN_USER
68 select HANDLE_DOMAIN_IRQ
69 select HARDIRQS_SW_RESEND
70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
75 select HAVE_ARCH_MMAP_RND_BITS if MMU
76 select HAVE_ARCH_PFN_VALID
77 select HAVE_ARCH_SECCOMP
78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
80 select HAVE_ARCH_TRACEHOOK
81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
82 select HAVE_ARM_SMCCC if CPU_V7
83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
84 select HAVE_CONTEXT_TRACKING
85 select HAVE_C_RECORDMCOUNT
86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
87 select HAVE_DMA_CONTIGUOUS if MMU
88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
91 select HAVE_EXIT_THREAD
92 select HAVE_FAST_GUP if ARM_LPAE
93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
96 select HAVE_GCC_PLUGINS
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
98 select HAVE_IDE if PCI || ISA || PCMCIA
99 select HAVE_IRQ_TIME_ACCOUNTING
100 select HAVE_KERNEL_GZIP
101 select HAVE_KERNEL_LZ4
102 select HAVE_KERNEL_LZMA
103 select HAVE_KERNEL_LZO
104 select HAVE_KERNEL_XZ
105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
106 select HAVE_KRETPROBES if HAVE_KPROBES
107 select HAVE_MOD_ARCH_SPECIFIC
109 select HAVE_OPTPROBES if !THUMB2_KERNEL
110 select HAVE_PERF_EVENTS
111 select HAVE_PERF_REGS
112 select HAVE_PERF_USER_STACK_DUMP
113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
114 select HAVE_REGS_AND_STACK_ACCESS_API
116 select HAVE_STACKPROTECTOR
117 select HAVE_SYSCALL_TRACEPOINTS
119 select HAVE_VIRT_CPU_ACCOUNTING_GEN
120 select IRQ_FORCED_THREADING
121 select MODULES_USE_ELF_REL
122 select NEED_DMA_MAP_STATE
123 select OF_EARLY_FLATTREE if OF
125 select OLD_SIGSUSPEND3
126 select PCI_SYSCALL if PCI
127 select PERF_USE_VMALLOC
130 select SYS_SUPPORTS_APM_EMULATION
131 # Above selects are sorted alphabetically; please add new ones
132 # according to that. Thanks.
134 The ARM series is a line of low-power-consumption RISC chip designs
135 licensed by ARM Ltd and targeted at embedded applications and
136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
137 manufactured, but legacy ARM-based PC hardware remains popular in
138 Europe. There is an ARM Linux project with a web page at
139 <http://www.arm.linux.org.uk/>.
141 config ARM_HAS_SG_CHAIN
144 config ARM_DMA_USE_IOMMU
146 select ARM_HAS_SG_CHAIN
147 select NEED_SG_DMA_LENGTH
151 config ARM_DMA_IOMMU_ALIGNMENT
152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
156 DMA mapping framework by default aligns all buffers to the smallest
157 PAGE_SIZE order which is greater than or equal to the requested buffer
158 size. This works well for buffers up to a few hundreds kilobytes, but
159 for larger buffers it just a waste of address space. Drivers which has
160 relatively small addressing window (like 64Mib) might run out of
161 virtual space with just a few allocations.
163 With this parameter you can specify the maximum PAGE_SIZE order for
164 DMA IOMMU buffers. Larger buffers will be aligned only to this
165 specified order. The order is expressed as a power of two multiplied
170 config SYS_SUPPORTS_APM_EMULATION
175 select GENERIC_ALLOCATOR
186 config STACKTRACE_SUPPORT
190 config LOCKDEP_SUPPORT
194 config TRACE_IRQFLAGS_SUPPORT
198 config ARCH_HAS_ILOG2_U32
201 config ARCH_HAS_ILOG2_U64
204 config ARCH_HAS_BANDGAP
207 config FIX_EARLYCON_MEM
210 config GENERIC_HWEIGHT
214 config GENERIC_CALIBRATE_DELAY
218 config ARCH_MAY_HAVE_PC_FDC
221 config ARCH_SUPPORTS_UPROBES
224 config ARCH_HAS_DMA_SET_COHERENT_MASK
227 config GENERIC_ISA_DMA
233 config NEED_RET_TO_USER
239 config ARM_PATCH_PHYS_VIRT
240 bool "Patch physical to virtual translations at runtime" if EMBEDDED
242 depends on !XIP_KERNEL && MMU
244 Patch phys-to-virt and virt-to-phys translation functions at
245 boot and module load time according to the position of the
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 2 MiB boundary.
251 Only disable this option if you know that you do not require
252 this feature (eg, building a kernel for a single machine) and
253 you need to shrink the kernel to the minimal size.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT
272 default DRAM_BASE if !MMU
273 default 0x00000000 if ARCH_FOOTBRIDGE
274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
275 default 0x20000000 if ARCH_S5PV210
276 default 0xc0000000 if ARCH_SA1100
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 config PGTABLE_LEVELS
287 default 3 if ARM_LPAE
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
299 config ARCH_MMAP_RND_BITS_MIN
302 config ARCH_MMAP_RND_BITS_MAX
303 default 14 if PAGE_OFFSET=0x40000000
304 default 15 if PAGE_OFFSET=0x80000000
308 # The "ARM system type" choice list is ordered alphabetically by option
309 # text. Please add new entries in the option alphabetic order.
312 prompt "ARM system type"
313 default ARM_SINGLE_ARMV7M if !MMU
314 default ARCH_MULTIPLATFORM if MMU
316 config ARCH_MULTIPLATFORM
317 bool "Allow multiple platforms to be selected"
319 select ARCH_FLATMEM_ENABLE
320 select ARCH_SPARSEMEM_ENABLE
321 select ARCH_SELECT_MEMORY_MODEL
322 select ARM_HAS_SG_CHAIN
323 select ARM_PATCH_PHYS_VIRT
327 select GENERIC_IRQ_MULTI_HANDLER
329 select PCI_DOMAINS_GENERIC if PCI
333 config ARM_SINGLE_ARMV7M
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 select ARCH_SPARSEMEM_ENABLE
349 imply ARM_PATCH_PHYS_VIRT
351 select GENERIC_IRQ_MULTI_HANDLER
356 select HAVE_LEGACY_CLK
358 This enables support for the Cirrus EP93xx series of CPUs.
360 config ARCH_FOOTBRIDGE
365 select NEED_MACH_IO_H if !MMU
366 select NEED_MACH_MEMORY_H
368 Support for systems based on the DC21285 companion chip
369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
377 select NEED_RET_TO_USER
381 Support for Intel's 80219 and IOP32X (XScale) family of
387 select ARCH_HAS_DMA_SET_COHERENT_MASK
388 select ARCH_SUPPORTS_BIG_ENDIAN
390 select DMABOUNCE if PCI
391 select GENERIC_IRQ_MULTI_HANDLER
397 select NEED_MACH_IO_H
398 select USB_EHCI_BIG_ENDIAN_DESC
399 select USB_EHCI_BIG_ENDIAN_MMIO
401 Support for Intel's IXP4XX (XScale) family of processors.
406 select GENERIC_IRQ_MULTI_HANDLER
412 select PLAT_ORION_LEGACY
414 select PM_GENERIC_DOMAINS if PM
416 Support for the Marvell Dove SoC 88AP510
419 bool "PXA2xx/PXA3xx-based"
422 select ARM_CPU_SUSPEND if PM
428 select CPU_XSCALE if !CPU_XSC3
429 select GENERIC_IRQ_MULTI_HANDLER
437 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
443 select ARCH_MAY_HAVE_PC_FDC
444 select ARCH_SPARSEMEM_ENABLE
445 select ARM_HAS_SG_CHAIN
449 select HAVE_PATA_PLATFORM
451 select LEGACY_TIMER_TICK
452 select NEED_MACH_IO_H
453 select NEED_MACH_MEMORY_H
456 On the Acorn Risc-PC, Linux can support the internal IDE disk and
457 CD-ROM interface, serial and parallel port, and the floppy drive.
462 select ARCH_SPARSEMEM_ENABLE
465 select TIMER_OF if OF
469 select GENERIC_IRQ_MULTI_HANDLER
474 select NEED_MACH_MEMORY_H
477 Support for StrongARM 11x0 based boards.
480 bool "Samsung S3C24XX SoCs"
482 select CLKSRC_SAMSUNG_PWM
485 select GENERIC_IRQ_MULTI_HANDLER
486 select HAVE_S3C2410_I2C if I2C
487 select HAVE_S3C_RTC if RTC_CLASS
488 select NEED_MACH_IO_H
489 select S3C2410_WATCHDOG
494 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
495 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
496 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
497 Samsung SMDK2410 development board (and derivatives).
504 select GENERIC_IRQ_CHIP
505 select GENERIC_IRQ_MULTI_HANDLER
508 select HAVE_LEGACY_CLK
510 select NEED_MACH_IO_H if PCCARD
511 select NEED_MACH_MEMORY_H
514 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
518 menu "Multiple platform selection"
519 depends on ARCH_MULTIPLATFORM
521 comment "CPU Core family selection"
524 bool "ARMv4 based platforms (FA526)"
525 depends on !ARCH_MULTI_V6_V7
526 select ARCH_MULTI_V4_V5
529 config ARCH_MULTI_V4T
530 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
531 depends on !ARCH_MULTI_V6_V7
532 select ARCH_MULTI_V4_V5
533 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
534 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
535 CPU_ARM925T || CPU_ARM940T)
538 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
539 depends on !ARCH_MULTI_V6_V7
540 select ARCH_MULTI_V4_V5
541 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
542 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
543 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
545 config ARCH_MULTI_V4_V5
549 bool "ARMv6 based platforms (ARM11)"
550 select ARCH_MULTI_V6_V7
554 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
556 select ARCH_MULTI_V6_V7
560 config ARCH_MULTI_V6_V7
562 select MIGHT_HAVE_CACHE_L2X0
564 config ARCH_MULTI_CPU_AUTO
565 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
571 bool "Dummy Virtual Machine"
572 depends on ARCH_MULTI_V7
575 select ARM_GIC_V2M if PCI
577 select ARM_GIC_V3_ITS if PCI
579 select HAVE_ARM_ARCH_TIMER
580 select ARCH_SUPPORTS_BIG_ENDIAN
583 # This is sorted alphabetically by mach-* pathname. However, plat-*
584 # Kconfigs may be included either alphabetically (according to the
585 # plat- suffix) or along side the corresponding mach-* source.
587 source "arch/arm/mach-actions/Kconfig"
589 source "arch/arm/mach-alpine/Kconfig"
591 source "arch/arm/mach-artpec/Kconfig"
593 source "arch/arm/mach-asm9260/Kconfig"
595 source "arch/arm/mach-aspeed/Kconfig"
597 source "arch/arm/mach-at91/Kconfig"
599 source "arch/arm/mach-axxia/Kconfig"
601 source "arch/arm/mach-bcm/Kconfig"
603 source "arch/arm/mach-berlin/Kconfig"
605 source "arch/arm/mach-clps711x/Kconfig"
607 source "arch/arm/mach-cns3xxx/Kconfig"
609 source "arch/arm/mach-davinci/Kconfig"
611 source "arch/arm/mach-digicolor/Kconfig"
613 source "arch/arm/mach-dove/Kconfig"
615 source "arch/arm/mach-ep93xx/Kconfig"
617 source "arch/arm/mach-exynos/Kconfig"
619 source "arch/arm/mach-footbridge/Kconfig"
621 source "arch/arm/mach-gemini/Kconfig"
623 source "arch/arm/mach-highbank/Kconfig"
625 source "arch/arm/mach-hisi/Kconfig"
627 source "arch/arm/mach-imx/Kconfig"
629 source "arch/arm/mach-integrator/Kconfig"
631 source "arch/arm/mach-iop32x/Kconfig"
633 source "arch/arm/mach-ixp4xx/Kconfig"
635 source "arch/arm/mach-keystone/Kconfig"
637 source "arch/arm/mach-lpc32xx/Kconfig"
639 source "arch/arm/mach-mediatek/Kconfig"
641 source "arch/arm/mach-meson/Kconfig"
643 source "arch/arm/mach-milbeaut/Kconfig"
645 source "arch/arm/mach-mmp/Kconfig"
647 source "arch/arm/mach-moxart/Kconfig"
649 source "arch/arm/mach-mstar/Kconfig"
651 source "arch/arm/mach-mv78xx0/Kconfig"
653 source "arch/arm/mach-mvebu/Kconfig"
655 source "arch/arm/mach-mxs/Kconfig"
657 source "arch/arm/mach-nomadik/Kconfig"
659 source "arch/arm/mach-npcm/Kconfig"
661 source "arch/arm/mach-nspire/Kconfig"
663 source "arch/arm/plat-omap/Kconfig"
665 source "arch/arm/mach-omap1/Kconfig"
667 source "arch/arm/mach-omap2/Kconfig"
669 source "arch/arm/mach-orion5x/Kconfig"
671 source "arch/arm/mach-oxnas/Kconfig"
673 source "arch/arm/mach-pxa/Kconfig"
674 source "arch/arm/plat-pxa/Kconfig"
676 source "arch/arm/mach-qcom/Kconfig"
678 source "arch/arm/mach-rda/Kconfig"
680 source "arch/arm/mach-realtek/Kconfig"
682 source "arch/arm/mach-realview/Kconfig"
684 source "arch/arm/mach-rockchip/Kconfig"
686 source "arch/arm/mach-s3c/Kconfig"
688 source "arch/arm/mach-s5pv210/Kconfig"
690 source "arch/arm/mach-sa1100/Kconfig"
692 source "arch/arm/mach-shmobile/Kconfig"
694 source "arch/arm/mach-socfpga/Kconfig"
696 source "arch/arm/mach-spear/Kconfig"
698 source "arch/arm/mach-sti/Kconfig"
700 source "arch/arm/mach-stm32/Kconfig"
702 source "arch/arm/mach-sunxi/Kconfig"
704 source "arch/arm/mach-tegra/Kconfig"
706 source "arch/arm/mach-uniphier/Kconfig"
708 source "arch/arm/mach-ux500/Kconfig"
710 source "arch/arm/mach-versatile/Kconfig"
712 source "arch/arm/mach-vexpress/Kconfig"
714 source "arch/arm/mach-vt8500/Kconfig"
716 source "arch/arm/mach-zynq/Kconfig"
718 # ARMv7-M architecture
720 bool "NXP LPC18xx/LPC43xx"
721 depends on ARM_SINGLE_ARMV7M
722 select ARCH_HAS_RESET_CONTROLLER
724 select CLKSRC_LPC32XX
727 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
728 high performance microcontrollers.
731 bool "ARM MPS2 platform"
732 depends on ARM_SINGLE_ARMV7M
736 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
737 with a range of available cores like Cortex-M3/M4/M7.
739 Please, note that depends which Application Note is used memory map
740 for the platform may vary, so adjustment of RAM base might be needed.
742 # Definitions to make life easier
753 select GENERIC_IRQ_CHIP
756 config PLAT_ORION_LEGACY
763 config PLAT_VERSATILE
766 source "arch/arm/mm/Kconfig"
769 bool "Enable iWMMXt support"
770 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
771 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
773 Enable support for iWMMXt context switching at run time if
774 running on a CPU that supports it.
777 source "arch/arm/Kconfig-nommu"
780 config PJ4B_ERRATA_4742
781 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
782 depends on CPU_PJ4B && MACH_ARMADA_370
785 When coming out of either a Wait for Interrupt (WFI) or a Wait for
786 Event (WFE) IDLE states, a specific timing sensitivity exists between
787 the retiring WFI/WFE instructions and the newly issued subsequent
788 instructions. This sensitivity can result in a CPU hang scenario.
790 The software must insert either a Data Synchronization Barrier (DSB)
791 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
794 config ARM_ERRATA_326103
795 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
798 Executing a SWP instruction to read-only memory does not set bit 11
799 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
800 treat the access as a read, preventing a COW from occurring and
801 causing the faulting task to livelock.
803 config ARM_ERRATA_411920
804 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
805 depends on CPU_V6 || CPU_V6K
807 Invalidation of the Instruction Cache operation can
808 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
809 It does not affect the MPCore. This option enables the ARM Ltd.
810 recommended workaround.
812 config ARM_ERRATA_430973
813 bool "ARM errata: Stale prediction on replaced interworking branch"
816 This option enables the workaround for the 430973 Cortex-A8
817 r1p* erratum. If a code sequence containing an ARM/Thumb
818 interworking branch is replaced with another code sequence at the
819 same virtual address, whether due to self-modifying code or virtual
820 to physical address re-mapping, Cortex-A8 does not recover from the
821 stale interworking branch prediction. This results in Cortex-A8
822 executing the new code sequence in the incorrect ARM or Thumb state.
823 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
824 and also flushes the branch target cache at every context switch.
825 Note that setting specific bits in the ACTLR register may not be
826 available in non-secure mode.
828 config ARM_ERRATA_458693
829 bool "ARM errata: Processor deadlock when a false hazard is created"
831 depends on !ARCH_MULTIPLATFORM
833 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
834 erratum. For very specific sequences of memory operations, it is
835 possible for a hazard condition intended for a cache line to instead
836 be incorrectly associated with a different cache line. This false
837 hazard might then cause a processor deadlock. The workaround enables
838 the L1 caching of the NEON accesses and disables the PLD instruction
839 in the ACTLR register. Note that setting specific bits in the ACTLR
840 register may not be available in non-secure mode.
842 config ARM_ERRATA_460075
843 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
845 depends on !ARCH_MULTIPLATFORM
847 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
848 erratum. Any asynchronous access to the L2 cache may encounter a
849 situation in which recent store transactions to the L2 cache are lost
850 and overwritten with stale memory contents from external memory. The
851 workaround disables the write-allocate mode for the L2 cache via the
852 ACTLR register. Note that setting specific bits in the ACTLR register
853 may not be available in non-secure mode.
855 config ARM_ERRATA_742230
856 bool "ARM errata: DMB operation may be faulty"
857 depends on CPU_V7 && SMP
858 depends on !ARCH_MULTIPLATFORM
860 This option enables the workaround for the 742230 Cortex-A9
861 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
862 between two write operations may not ensure the correct visibility
863 ordering of the two writes. This workaround sets a specific bit in
864 the diagnostic register of the Cortex-A9 which causes the DMB
865 instruction to behave as a DSB, ensuring the correct behaviour of
868 config ARM_ERRATA_742231
869 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
870 depends on CPU_V7 && SMP
871 depends on !ARCH_MULTIPLATFORM
873 This option enables the workaround for the 742231 Cortex-A9
874 (r2p0..r2p2) erratum. Under certain conditions, specific to the
875 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
876 accessing some data located in the same cache line, may get corrupted
877 data due to bad handling of the address hazard when the line gets
878 replaced from one of the CPUs at the same time as another CPU is
879 accessing it. This workaround sets specific bits in the diagnostic
880 register of the Cortex-A9 which reduces the linefill issuing
881 capabilities of the processor.
883 config ARM_ERRATA_643719
884 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
885 depends on CPU_V7 && SMP
888 This option enables the workaround for the 643719 Cortex-A9 (prior to
889 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
890 register returns zero when it should return one. The workaround
891 corrects this value, ensuring cache maintenance operations which use
892 it behave as intended and avoiding data corruption.
894 config ARM_ERRATA_720789
895 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
898 This option enables the workaround for the 720789 Cortex-A9 (prior to
899 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
900 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
901 As a consequence of this erratum, some TLB entries which should be
902 invalidated are not, resulting in an incoherency in the system page
903 tables. The workaround changes the TLB flushing routines to invalidate
904 entries regardless of the ASID.
906 config ARM_ERRATA_743622
907 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
909 depends on !ARCH_MULTIPLATFORM
911 This option enables the workaround for the 743622 Cortex-A9
912 (r2p*) erratum. Under very rare conditions, a faulty
913 optimisation in the Cortex-A9 Store Buffer may lead to data
914 corruption. This workaround sets a specific bit in the diagnostic
915 register of the Cortex-A9 which disables the Store Buffer
916 optimisation, preventing the defect from occurring. This has no
917 visible impact on the overall performance or power consumption of the
920 config ARM_ERRATA_751472
921 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
923 depends on !ARCH_MULTIPLATFORM
925 This option enables the workaround for the 751472 Cortex-A9 (prior
926 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
927 completion of a following broadcasted operation if the second
928 operation is received by a CPU before the ICIALLUIS has completed,
929 potentially leading to corrupted entries in the cache or TLB.
931 config ARM_ERRATA_754322
932 bool "ARM errata: possible faulty MMU translations following an ASID switch"
935 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
936 r3p*) erratum. A speculative memory access may cause a page table walk
937 which starts prior to an ASID switch but completes afterwards. This
938 can populate the micro-TLB with a stale entry which may be hit with
939 the new ASID. This workaround places two dsb instructions in the mm
940 switching code so that no page table walks can cross the ASID switch.
942 config ARM_ERRATA_754327
943 bool "ARM errata: no automatic Store Buffer drain"
944 depends on CPU_V7 && SMP
946 This option enables the workaround for the 754327 Cortex-A9 (prior to
947 r2p0) erratum. The Store Buffer does not have any automatic draining
948 mechanism and therefore a livelock may occur if an external agent
949 continuously polls a memory location waiting to observe an update.
950 This workaround defines cpu_relax() as smp_mb(), preventing correctly
951 written polling loops from denying visibility of updates to memory.
953 config ARM_ERRATA_364296
954 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
957 This options enables the workaround for the 364296 ARM1136
958 r0p2 erratum (possible cache data corruption with
959 hit-under-miss enabled). It sets the undocumented bit 31 in
960 the auxiliary control register and the FI bit in the control
961 register, thus disabling hit-under-miss without putting the
962 processor into full low interrupt latency mode. ARM11MPCore
965 config ARM_ERRATA_764369
966 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
967 depends on CPU_V7 && SMP
969 This option enables the workaround for erratum 764369
970 affecting Cortex-A9 MPCore with two or more processors (all
971 current revisions). Under certain timing circumstances, a data
972 cache line maintenance operation by MVA targeting an Inner
973 Shareable memory region may fail to proceed up to either the
974 Point of Coherency or to the Point of Unification of the
975 system. This workaround adds a DSB instruction before the
976 relevant cache maintenance functions and sets a specific bit
977 in the diagnostic control register of the SCU.
979 config ARM_ERRATA_775420
980 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
983 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
984 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
985 operation aborts with MMU exception, it might cause the processor
986 to deadlock. This workaround puts DSB before executing ISB if
987 an abort may occur on cache maintenance.
989 config ARM_ERRATA_798181
990 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
991 depends on CPU_V7 && SMP
993 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
994 adequately shooting down all use of the old entries. This
995 option enables the Linux kernel workaround for this erratum
996 which sends an IPI to the CPUs that are running the same ASID
997 as the one being invalidated.
999 config ARM_ERRATA_773022
1000 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1003 This option enables the workaround for the 773022 Cortex-A15
1004 (up to r0p4) erratum. In certain rare sequences of code, the
1005 loop buffer may deliver incorrect instructions. This
1006 workaround disables the loop buffer to avoid the erratum.
1008 config ARM_ERRATA_818325_852422
1009 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1012 This option enables the workaround for:
1013 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1014 instruction might deadlock. Fixed in r0p1.
1015 - Cortex-A12 852422: Execution of a sequence of instructions might
1016 lead to either a data corruption or a CPU deadlock. Not fixed in
1017 any Cortex-A12 cores yet.
1018 This workaround for all both errata involves setting bit[12] of the
1019 Feature Register. This bit disables an optimisation applied to a
1020 sequence of 2 instructions that use opposing condition codes.
1022 config ARM_ERRATA_821420
1023 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1026 This option enables the workaround for the 821420 Cortex-A12
1027 (all revs) erratum. In very rare timing conditions, a sequence
1028 of VMOV to Core registers instructions, for which the second
1029 one is in the shadow of a branch or abort, can lead to a
1030 deadlock when the VMOV instructions are issued out-of-order.
1032 config ARM_ERRATA_825619
1033 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1036 This option enables the workaround for the 825619 Cortex-A12
1037 (all revs) erratum. Within rare timing constraints, executing a
1038 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1039 and Device/Strongly-Ordered loads and stores might cause deadlock
1041 config ARM_ERRATA_857271
1042 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1045 This option enables the workaround for the 857271 Cortex-A12
1046 (all revs) erratum. Under very rare timing conditions, the CPU might
1047 hang. The workaround is expected to have a < 1% performance impact.
1049 config ARM_ERRATA_852421
1050 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1053 This option enables the workaround for the 852421 Cortex-A17
1054 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1055 execution of a DMB ST instruction might fail to properly order
1056 stores from GroupA and stores from GroupB.
1058 config ARM_ERRATA_852423
1059 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1062 This option enables the workaround for:
1063 - Cortex-A17 852423: Execution of a sequence of instructions might
1064 lead to either a data corruption or a CPU deadlock. Not fixed in
1065 any Cortex-A17 cores yet.
1066 This is identical to Cortex-A12 erratum 852422. It is a separate
1067 config option from the A12 erratum due to the way errata are checked
1070 config ARM_ERRATA_857272
1071 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1074 This option enables the workaround for the 857272 Cortex-A17 erratum.
1075 This erratum is not known to be fixed in any A17 revision.
1076 This is identical to Cortex-A12 erratum 857271. It is a separate
1077 config option from the A12 erratum due to the way errata are checked
1082 source "arch/arm/common/Kconfig"
1089 Find out whether you have ISA slots on your motherboard. ISA is the
1090 name of a bus system, i.e. the way the CPU talks to the other stuff
1091 inside your box. Other bus systems are PCI, EISA, MicroChannel
1092 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1093 newer boards don't support it. If you have ISA, say Y, otherwise N.
1095 # Select ISA DMA controller support
1100 # Select ISA DMA interface
1104 config PCI_NANOENGINE
1105 bool "BSE nanoEngine PCI support"
1106 depends on SA1100_NANOENGINE
1108 Enable PCI on the BSE nanoEngine board.
1110 config ARM_ERRATA_814220
1111 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1114 The v7 ARM states that all cache and branch predictor maintenance
1115 operations that do not specify an address execute, relative to
1116 each other, in program order.
1117 However, because of this erratum, an L2 set/way cache maintenance
1118 operation can overtake an L1 set/way cache maintenance operation.
1119 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1124 menu "Kernel Features"
1129 This option should be selected by machines which have an SMP-
1132 The only effect of this option is to make the SMP-related
1133 options available to the user for configuration.
1136 bool "Symmetric Multi-Processing"
1137 depends on CPU_V6K || CPU_V7
1139 depends on MMU || ARM_MPU
1142 This enables support for systems with more than one CPU. If you have
1143 a system with only one CPU, say N. If you have a system with more
1144 than one CPU, say Y.
1146 If you say N here, the kernel will run on uni- and multiprocessor
1147 machines, but will use only one CPU of a multiprocessor machine. If
1148 you say Y here, the kernel will run on many, but not all,
1149 uniprocessor machines. On a uniprocessor machine, the kernel
1150 will run faster if you say N here.
1152 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1153 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1154 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1156 If you don't know what to do here, say N.
1159 bool "Allow booting SMP kernel on uniprocessor systems"
1160 depends on SMP && !XIP_KERNEL && MMU
1163 SMP kernels contain instructions which fail on non-SMP processors.
1164 Enabling this option allows the kernel to modify itself to make
1165 these instructions safe. Disabling it allows about 1K of space
1168 If you don't know what to do here, say Y.
1170 config ARM_CPU_TOPOLOGY
1171 bool "Support cpu topology definition"
1172 depends on SMP && CPU_V7
1175 Support ARM cpu topology definition. The MPIDR register defines
1176 affinity between processors which is then used to describe the cpu
1177 topology of an ARM System.
1180 bool "Multi-core scheduler support"
1181 depends on ARM_CPU_TOPOLOGY
1183 Multi-core scheduler support improves the CPU scheduler's decision
1184 making when dealing with multi-core CPU chips at a cost of slightly
1185 increased overhead in some places. If unsure say N here.
1188 bool "SMT scheduler support"
1189 depends on ARM_CPU_TOPOLOGY
1191 Improves the CPU scheduler's decision making when dealing with
1192 MultiThreading at a cost of slightly increased overhead in some
1193 places. If unsure say N here.
1198 This option enables support for the ARM snoop control unit
1200 config HAVE_ARM_ARCH_TIMER
1201 bool "Architected timer support"
1203 select ARM_ARCH_TIMER
1205 This option enables support for the ARM architected timer
1210 This options enables support for the ARM timer and watchdog unit
1213 bool "Multi-Cluster Power Management"
1214 depends on CPU_V7 && SMP
1216 This option provides the common power management infrastructure
1217 for (multi-)cluster based systems, such as big.LITTLE based
1220 config MCPM_QUAD_CLUSTER
1224 To avoid wasting resources unnecessarily, MCPM only supports up
1225 to 2 clusters by default.
1226 Platforms with 3 or 4 clusters that use MCPM must select this
1227 option to allow the additional clusters to be managed.
1230 bool "big.LITTLE support (Experimental)"
1231 depends on CPU_V7 && SMP
1234 This option enables support selections for the big.LITTLE
1235 system architecture.
1238 bool "big.LITTLE switcher support"
1239 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1242 The big.LITTLE "switcher" provides the core functionality to
1243 transparently handle transition between a cluster of A15's
1244 and a cluster of A7's in a big.LITTLE system.
1246 config BL_SWITCHER_DUMMY_IF
1247 tristate "Simple big.LITTLE switcher user interface"
1248 depends on BL_SWITCHER && DEBUG_KERNEL
1250 This is a simple and dummy char dev interface to control
1251 the big.LITTLE switcher core code. It is meant for
1252 debugging purposes only.
1255 prompt "Memory split"
1259 Select the desired split between kernel and user memory.
1261 If you are not absolutely sure what you are doing, leave this
1265 bool "3G/1G user/kernel split"
1266 config VMSPLIT_3G_OPT
1267 depends on !ARM_LPAE
1268 bool "3G/1G user/kernel split (for full 1G low memory)"
1270 bool "2G/2G user/kernel split"
1272 bool "1G/3G user/kernel split"
1277 default PHYS_OFFSET if !MMU
1278 default 0x40000000 if VMSPLIT_1G
1279 default 0x80000000 if VMSPLIT_2G
1280 default 0xB0000000 if VMSPLIT_3G_OPT
1283 config KASAN_SHADOW_OFFSET
1286 default 0x1f000000 if PAGE_OFFSET=0x40000000
1287 default 0x5f000000 if PAGE_OFFSET=0x80000000
1288 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1289 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1293 int "Maximum number of CPUs (2-32)"
1294 range 2 16 if DEBUG_KMAP_LOCAL
1295 range 2 32 if !DEBUG_KMAP_LOCAL
1299 The maximum number of CPUs that the kernel can support.
1300 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1301 debugging is enabled, which uses half of the per-CPU fixmap
1302 slots as guard regions.
1305 bool "Support for hot-pluggable CPUs"
1307 select GENERIC_IRQ_MIGRATION
1309 Say Y here to experiment with turning CPUs off and on. CPUs
1310 can be controlled through /sys/devices/system/cpu.
1313 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1314 depends on HAVE_ARM_SMCCC
1317 Say Y here if you want Linux to communicate with system firmware
1318 implementing the PSCI specification for CPU-centric power
1319 management operations described in ARM document number ARM DEN
1320 0022A ("Power State Coordination Interface System Software on
1323 # The GPIO number here must be sorted by descending number. In case of
1324 # a multiplatform kernel, we just want the highest value required by the
1325 # selected platforms.
1328 default 2048 if ARCH_INTEL_SOCFPGA
1329 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1330 ARCH_ZYNQ || ARCH_ASPEED
1331 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1332 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1333 default 416 if ARCH_SUNXI
1334 default 392 if ARCH_U8500
1335 default 352 if ARCH_VT8500
1336 default 288 if ARCH_ROCKCHIP
1337 default 264 if MACH_H4700
1340 Maximum number of GPIOs in the system.
1342 If unsure, leave the default value.
1346 default 128 if SOC_AT91RM9200
1350 depends on HZ_FIXED = 0
1351 prompt "Timer frequency"
1375 default HZ_FIXED if HZ_FIXED != 0
1376 default 100 if HZ_100
1377 default 200 if HZ_200
1378 default 250 if HZ_250
1379 default 300 if HZ_300
1380 default 500 if HZ_500
1384 def_bool HIGH_RES_TIMERS
1386 config THUMB2_KERNEL
1387 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1388 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1389 default y if CPU_THUMBONLY
1392 By enabling this option, the kernel will be compiled in
1397 config ARM_PATCH_IDIV
1398 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1399 depends on CPU_32v7 && !XIP_KERNEL
1402 The ARM compiler inserts calls to __aeabi_idiv() and
1403 __aeabi_uidiv() when it needs to perform division on signed
1404 and unsigned integers. Some v7 CPUs have support for the sdiv
1405 and udiv instructions that can be used to implement those
1408 Enabling this option allows the kernel to modify itself to
1409 replace the first two instructions of these library functions
1410 with the sdiv or udiv plus "bx lr" instructions when the CPU
1411 it is running on supports them. Typically this will be faster
1412 and less power intensive than running the original library
1413 code to do integer division.
1416 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1417 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1418 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1420 This option allows for the kernel to be compiled using the latest
1421 ARM ABI (aka EABI). This is only useful if you are using a user
1422 space environment that is also compiled with EABI.
1424 Since there are major incompatibilities between the legacy ABI and
1425 EABI, especially with regard to structure member alignment, this
1426 option also changes the kernel syscall calling convention to
1427 disambiguate both ABIs and allow for backward compatibility support
1428 (selected with CONFIG_OABI_COMPAT).
1430 To use this you need GCC version 4.0.0 or later.
1433 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1434 depends on AEABI && !THUMB2_KERNEL
1436 This option preserves the old syscall interface along with the
1437 new (ARM EABI) one. It also provides a compatibility layer to
1438 intercept syscalls that have structure arguments which layout
1439 in memory differs between the legacy ABI and the new ARM EABI
1440 (only for non "thumb" binaries). This option adds a tiny
1441 overhead to all syscalls and produces a slightly larger kernel.
1443 The seccomp filter system will not be available when this is
1444 selected, since there is no way yet to sensibly distinguish
1445 between calling conventions during filtering.
1447 If you know you'll be using only pure EABI user space then you
1448 can say N here. If this option is not selected and you attempt
1449 to execute a legacy ABI binary then the result will be
1450 UNPREDICTABLE (in fact it can be predicted that it won't work
1451 at all). If in doubt say N.
1453 config ARCH_SELECT_MEMORY_MODEL
1456 config ARCH_FLATMEM_ENABLE
1459 config ARCH_SPARSEMEM_ENABLE
1461 select SPARSEMEM_STATIC if SPARSEMEM
1464 bool "High Memory Support"
1468 The address space of ARM processors is only 4 Gigabytes large
1469 and it has to accommodate user address space, kernel address
1470 space as well as some memory mapped IO. That means that, if you
1471 have a large amount of physical memory and/or IO, not all of the
1472 memory can be "permanently mapped" by the kernel. The physical
1473 memory that is not permanently mapped is called "high memory".
1475 Depending on the selected kernel/user memory split, minimum
1476 vmalloc space and actual amount of RAM, you may not need this
1477 option which should result in a slightly faster kernel.
1482 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1486 The VM uses one page of physical memory for each page table.
1487 For systems with a lot of processes, this can use a lot of
1488 precious low memory, eventually leading to low memory being
1489 consumed by page tables. Setting this option will allow
1490 user-space 2nd level page tables to reside in high memory.
1492 config CPU_SW_DOMAIN_PAN
1493 bool "Enable use of CPU domains to implement privileged no-access"
1494 depends on MMU && !ARM_LPAE
1497 Increase kernel security by ensuring that normal kernel accesses
1498 are unable to access userspace addresses. This can help prevent
1499 use-after-free bugs becoming an exploitable privilege escalation
1500 by ensuring that magic values (such as LIST_POISON) will always
1501 fault when dereferenced.
1503 CPUs with low-vector mappings use a best-efforts implementation.
1504 Their lower 1MB needs to remain accessible for the vectors, but
1505 the remainder of userspace will become appropriately inaccessible.
1507 config HW_PERF_EVENTS
1511 config ARCH_WANT_GENERAL_HUGETLB
1514 config ARM_MODULE_PLTS
1515 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1519 Allocate PLTs when loading modules so that jumps and calls whose
1520 targets are too far away for their relative offsets to be encoded
1521 in the instructions themselves can be bounced via veneers in the
1522 module's PLT. This allows modules to be allocated in the generic
1523 vmalloc area after the dedicated module memory area has been
1524 exhausted. The modules will use slightly more memory, but after
1525 rounding up to page size, the actual memory footprint is usually
1528 Disabling this is usually safe for small single-platform
1529 configurations. If unsure, say y.
1531 config FORCE_MAX_ZONEORDER
1532 int "Maximum zone order"
1533 default "12" if SOC_AM33XX
1534 default "9" if SA1111
1537 The kernel memory allocator divides physically contiguous memory
1538 blocks into "zones", where each zone is a power of two number of
1539 pages. This option selects the largest power of two that the kernel
1540 keeps in the memory allocator. If you need to allocate very large
1541 blocks of physically contiguous memory, then you may need to
1542 increase this value.
1544 This config option is actually maximum order plus one. For example,
1545 a value of 11 means that the largest free memory block is 2^10 pages.
1547 config ALIGNMENT_TRAP
1548 def_bool CPU_CP15_MMU
1549 select HAVE_PROC_CPU if PROC_FS
1551 ARM processors cannot fetch/store information which is not
1552 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1553 address divisible by 4. On 32-bit ARM processors, these non-aligned
1554 fetch/store instructions will be emulated in software if you say
1555 here, which has a severe performance impact. This is necessary for
1556 correct operation of some network protocols. With an IP-only
1557 configuration it is safe to say N, otherwise say Y.
1559 config UACCESS_WITH_MEMCPY
1560 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1562 default y if CPU_FEROCEON
1564 Implement faster copy_to_user and clear_user methods for CPU
1565 cores where a 8-word STM instruction give significantly higher
1566 memory write throughput than a sequence of individual 32bit stores.
1568 A possible side effect is a slight increase in scheduling latency
1569 between threads sharing the same address space if they invoke
1570 such copy operations with large buffers.
1572 However, if the CPU data cache is using a write-allocate mode,
1573 this option is unlikely to provide any performance gain.
1576 bool "Enable paravirtualization code"
1578 This changes the kernel so it can modify itself when it is run
1579 under a hypervisor, potentially improving performance significantly
1580 over full virtualization.
1582 config PARAVIRT_TIME_ACCOUNTING
1583 bool "Paravirtual steal time accounting"
1586 Select this option to enable fine granularity task steal time
1587 accounting. Time spent executing other tasks in parallel with
1588 the current vCPU is discounted from the vCPU power. To account for
1589 that, there can be a small performance impact.
1591 If in doubt, say N here.
1598 bool "Xen guest support on ARM"
1599 depends on ARM && AEABI && OF
1600 depends on CPU_V7 && !CPU_V6
1601 depends on !GENERIC_ATOMIC64
1603 select ARCH_DMA_ADDR_T_64BIT
1609 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1611 config STACKPROTECTOR_PER_TASK
1612 bool "Use a unique stack canary value for each task"
1613 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1614 select GCC_PLUGIN_ARM_SSP_PER_TASK
1617 Due to the fact that GCC uses an ordinary symbol reference from
1618 which to load the value of the stack canary, this value can only
1619 change at reboot time on SMP systems, and all tasks running in the
1620 kernel's address space are forced to use the same canary value for
1621 the entire duration that the system is up.
1623 Enable this option to switch to a different method that uses a
1624 different canary value for each task.
1631 bool "Flattened Device Tree support"
1635 Include support for flattened device tree machine descriptions.
1638 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1641 This is the traditional way of passing data to the kernel at boot
1642 time. If you are solely relying on the flattened device tree (or
1643 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1644 to remove ATAGS support from your kernel binary. If unsure,
1647 config DEPRECATED_PARAM_STRUCT
1648 bool "Provide old way to pass kernel parameters"
1651 This was deprecated in 2001 and announced to live on for 5 years.
1652 Some old boot loaders still use this way.
1654 # Compressed boot loader in ROM. Yes, we really want to ask about
1655 # TEXT and BSS so we preserve their values in the config files.
1656 config ZBOOT_ROM_TEXT
1657 hex "Compressed ROM boot loader base address"
1660 The physical address at which the ROM-able zImage is to be
1661 placed in the target. Platforms which normally make use of
1662 ROM-able zImage formats normally set this to a suitable
1663 value in their defconfig file.
1665 If ZBOOT_ROM is not enabled, this has no effect.
1667 config ZBOOT_ROM_BSS
1668 hex "Compressed ROM boot loader BSS address"
1671 The base address of an area of read/write memory in the target
1672 for the ROM-able zImage which must be available while the
1673 decompressor is running. It must be large enough to hold the
1674 entire decompressed kernel plus an additional 128 KiB.
1675 Platforms which normally make use of ROM-able zImage formats
1676 normally set this to a suitable value in their defconfig file.
1678 If ZBOOT_ROM is not enabled, this has no effect.
1681 bool "Compressed boot loader in ROM/flash"
1682 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1683 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1685 Say Y here if you intend to execute your compressed kernel image
1686 (zImage) directly from ROM or flash. If unsure, say N.
1688 config ARM_APPENDED_DTB
1689 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1692 With this option, the boot code will look for a device tree binary
1693 (DTB) appended to zImage
1694 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1696 This is meant as a backward compatibility convenience for those
1697 systems with a bootloader that can't be upgraded to accommodate
1698 the documented boot protocol using a device tree.
1700 Beware that there is very little in terms of protection against
1701 this option being confused by leftover garbage in memory that might
1702 look like a DTB header after a reboot if no actual DTB is appended
1703 to zImage. Do not leave this option active in a production kernel
1704 if you don't intend to always append a DTB. Proper passing of the
1705 location into r2 of a bootloader provided DTB is always preferable
1708 config ARM_ATAG_DTB_COMPAT
1709 bool "Supplement the appended DTB with traditional ATAG information"
1710 depends on ARM_APPENDED_DTB
1712 Some old bootloaders can't be updated to a DTB capable one, yet
1713 they provide ATAGs with memory configuration, the ramdisk address,
1714 the kernel cmdline string, etc. Such information is dynamically
1715 provided by the bootloader and can't always be stored in a static
1716 DTB. To allow a device tree enabled kernel to be used with such
1717 bootloaders, this option allows zImage to extract the information
1718 from the ATAG list and store it at run time into the appended DTB.
1721 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1722 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1724 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1725 bool "Use bootloader kernel arguments if available"
1727 Uses the command-line options passed by the boot loader instead of
1728 the device tree bootargs property. If the boot loader doesn't provide
1729 any, the device tree bootargs property will be used.
1731 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1732 bool "Extend with bootloader kernel arguments"
1734 The command-line arguments provided by the boot loader will be
1735 appended to the the device tree bootargs property.
1740 string "Default kernel command string"
1743 On some architectures (e.g. CATS), there is currently no way
1744 for the boot loader to pass arguments to the kernel. For these
1745 architectures, you should supply some command-line options at build
1746 time by entering them here. As a minimum, you should specify the
1747 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1750 prompt "Kernel command line type" if CMDLINE != ""
1751 default CMDLINE_FROM_BOOTLOADER
1754 config CMDLINE_FROM_BOOTLOADER
1755 bool "Use bootloader kernel arguments if available"
1757 Uses the command-line options passed by the boot loader. If
1758 the boot loader doesn't provide any, the default kernel command
1759 string provided in CMDLINE will be used.
1761 config CMDLINE_EXTEND
1762 bool "Extend bootloader kernel arguments"
1764 The command-line arguments provided by the boot loader will be
1765 appended to the default kernel command string.
1767 config CMDLINE_FORCE
1768 bool "Always use the default kernel command string"
1770 Always use the default kernel command string, even if the boot
1771 loader passes other arguments to the kernel.
1772 This is useful if you cannot or don't want to change the
1773 command-line options your boot loader passes to the kernel.
1777 bool "Kernel Execute-In-Place from ROM"
1778 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1780 Execute-In-Place allows the kernel to run from non-volatile storage
1781 directly addressable by the CPU, such as NOR flash. This saves RAM
1782 space since the text section of the kernel is not loaded from flash
1783 to RAM. Read-write sections, such as the data section and stack,
1784 are still copied to RAM. The XIP kernel is not compressed since
1785 it has to run directly from flash, so it will take more space to
1786 store it. The flash address used to link the kernel object files,
1787 and for storing it, is configuration dependent. Therefore, if you
1788 say Y here, you must know the proper physical address where to
1789 store the kernel image depending on your own flash memory usage.
1791 Also note that the make target becomes "make xipImage" rather than
1792 "make zImage" or "make Image". The final kernel binary to put in
1793 ROM memory will be arch/arm/boot/xipImage.
1797 config XIP_PHYS_ADDR
1798 hex "XIP Kernel Physical Location"
1799 depends on XIP_KERNEL
1800 default "0x00080000"
1802 This is the physical address in your flash memory the kernel will
1803 be linked for and stored to. This address is dependent on your
1806 config XIP_DEFLATED_DATA
1807 bool "Store kernel .data section compressed in ROM"
1808 depends on XIP_KERNEL
1811 Before the kernel is actually executed, its .data section has to be
1812 copied to RAM from ROM. This option allows for storing that data
1813 in compressed form and decompressed to RAM rather than merely being
1814 copied, saving some precious ROM space. A possible drawback is a
1815 slightly longer boot delay.
1818 bool "Kexec system call (EXPERIMENTAL)"
1819 depends on (!SMP || PM_SLEEP_SMP)
1823 kexec is a system call that implements the ability to shutdown your
1824 current kernel, and to start another kernel. It is like a reboot
1825 but it is independent of the system firmware. And like a reboot
1826 you can start any kernel with it, not just Linux.
1828 It is an ongoing process to be certain the hardware in a machine
1829 is properly shutdown, so do not be surprised if this code does not
1830 initially work for you.
1833 bool "Export atags in procfs"
1834 depends on ATAGS && KEXEC
1837 Should the atags used to boot the kernel be exported in an "atags"
1838 file in procfs. Useful with kexec.
1841 bool "Build kdump crash kernel (EXPERIMENTAL)"
1843 Generate crash dump after being started by kexec. This should
1844 be normally only set in special crash dump kernels which are
1845 loaded in the main kernel with kexec-tools into a specially
1846 reserved region and then later executed after a crash by
1847 kdump/kexec. The crash dump kernel must be compiled to a
1848 memory address not used by the main kernel
1850 For more details see Documentation/admin-guide/kdump/kdump.rst
1852 config AUTO_ZRELADDR
1853 bool "Auto calculation of the decompressed kernel image address"
1855 ZRELADDR is the physical address where the decompressed kernel
1856 image will be placed. If AUTO_ZRELADDR is selected, the address
1857 will be determined at run-time, either by masking the current IP
1858 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1859 This assumes the zImage being placed in the first 128MB from
1866 bool "UEFI runtime support"
1867 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1869 select EFI_PARAMS_FROM_FDT
1871 select EFI_GENERIC_STUB
1872 select EFI_RUNTIME_WRAPPERS
1874 This option provides support for runtime services provided
1875 by UEFI firmware (such as non-volatile variables, realtime
1876 clock, and platform reset). A UEFI stub is also provided to
1877 allow the kernel to be booted as an EFI application. This
1878 is only useful for kernels that may run on systems that have
1882 bool "Enable support for SMBIOS (DMI) tables"
1886 This enables SMBIOS/DMI feature for systems.
1888 This option is only useful on systems that have UEFI firmware.
1889 However, even with this option, the resultant kernel should
1890 continue to boot on existing non-UEFI platforms.
1892 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1893 i.e., the the practice of identifying the platform via DMI to
1894 decide whether certain workarounds for buggy hardware and/or
1895 firmware need to be enabled. This would require the DMI subsystem
1896 to be enabled much earlier than we do on ARM, which is non-trivial.
1900 menu "CPU Power Management"
1902 source "drivers/cpufreq/Kconfig"
1904 source "drivers/cpuidle/Kconfig"
1908 menu "Floating point emulation"
1910 comment "At least one emulation must be selected"
1913 bool "NWFPE math emulation"
1914 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1916 Say Y to include the NWFPE floating point emulator in the kernel.
1917 This is necessary to run most binaries. Linux does not currently
1918 support floating point hardware so you need to say Y here even if
1919 your machine has an FPA or floating point co-processor podule.
1921 You may say N here if you are going to load the Acorn FPEmulator
1922 early in the bootup.
1925 bool "Support extended precision"
1926 depends on FPE_NWFPE
1928 Say Y to include 80-bit support in the kernel floating-point
1929 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1930 Note that gcc does not generate 80-bit operations by default,
1931 so in most cases this option only enlarges the size of the
1932 floating point emulator without any good reason.
1934 You almost surely want to say N here.
1937 bool "FastFPE math emulation (EXPERIMENTAL)"
1938 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1940 Say Y here to include the FAST floating point emulator in the kernel.
1941 This is an experimental much faster emulator which now also has full
1942 precision for the mantissa. It does not support any exceptions.
1943 It is very simple, and approximately 3-6 times faster than NWFPE.
1945 It should be sufficient for most programs. It may be not suitable
1946 for scientific calculations, but you have to check this for yourself.
1947 If you do not feel you need a faster FP emulation you should better
1951 bool "VFP-format floating point maths"
1952 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1954 Say Y to include VFP support code in the kernel. This is needed
1955 if your hardware includes a VFP unit.
1957 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1958 release notes and additional status information.
1960 Say N if your target does not have VFP hardware.
1968 bool "Advanced SIMD (NEON) Extension support"
1969 depends on VFPv3 && CPU_V7
1971 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1974 config KERNEL_MODE_NEON
1975 bool "Support for NEON in kernel mode"
1976 depends on NEON && AEABI
1978 Say Y to include support for NEON in kernel mode.
1982 menu "Power management options"
1984 source "kernel/power/Kconfig"
1986 config ARCH_SUSPEND_POSSIBLE
1987 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1988 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1991 config ARM_CPU_SUSPEND
1992 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1993 depends on ARCH_SUSPEND_POSSIBLE
1995 config ARCH_HIBERNATION_POSSIBLE
1998 default y if ARCH_SUSPEND_POSSIBLE
2002 source "drivers/firmware/Kconfig"
2005 source "arch/arm/crypto/Kconfig"
2008 source "arch/arm/Kconfig.assembler"