1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_MEMBARRIER_SYNC_CORE
13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
14 select ARCH_HAS_PHYS_TO_DMA
15 select ARCH_HAS_SET_MEMORY
16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
17 select ARCH_HAS_STRICT_MODULE_RWX if MMU
18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAVE_CUSTOM_GPIO_H
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_MIGHT_HAVE_PC_PARPORT
22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
24 select ARCH_SUPPORTS_ATOMIC_RMW
25 select ARCH_USE_BUILTIN_BSWAP
26 select ARCH_USE_CMPXCHG_LOCKREF
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select BUILDTIME_EXTABLE_SORT if MMU
29 select CLONE_BACKWARDS
30 select CPU_PM if (SUSPEND || CPU_IDLE)
31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
32 select DMA_DIRECT_OPS if !MMU
34 select EDAC_ATOMIC_SCRUB
35 select GENERIC_ALLOCATOR
36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select HANDLE_DOMAIN_IRQ
51 select HARDIRQS_SW_RESEND
52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
56 select HAVE_ARCH_MMAP_RND_BITS if MMU
57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
59 select HAVE_ARCH_TRACEHOOK
60 select HAVE_ARM_SMCCC if CPU_V7
61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
62 select HAVE_CONTEXT_TRACKING
63 select HAVE_C_RECORDMCOUNT
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DMA_CONTIGUOUS if MMU
66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
69 select HAVE_EXIT_THREAD
70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
73 select HAVE_GCC_PLUGINS
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
76 select HAVE_IDE if PCI || ISA || PCMCIA
77 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_KERNEL_GZIP
79 select HAVE_KERNEL_LZ4
80 select HAVE_KERNEL_LZMA
81 select HAVE_KERNEL_LZO
83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
84 select HAVE_KRETPROBES if (HAVE_KPROBES)
86 select HAVE_MOD_ARCH_SPECIFIC
88 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
89 select HAVE_OPTPROBES if !THUMB2_KERNEL
90 select HAVE_PERF_EVENTS
92 select HAVE_PERF_USER_STACK_DUMP
93 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
94 select HAVE_REGS_AND_STACK_ACCESS_API
96 select HAVE_STACKPROTECTOR
97 select HAVE_SYSCALL_TRACEPOINTS
99 select HAVE_VIRT_CPU_ACCOUNTING_GEN
100 select IRQ_FORCED_THREADING
101 select MODULES_USE_ELF_REL
102 select NEED_DMA_MAP_STATE
104 select OF_EARLY_FLATTREE if OF
105 select OF_RESERVED_MEM if OF
107 select OLD_SIGSUSPEND3
108 select PERF_USE_VMALLOC
111 select SYS_SUPPORTS_APM_EMULATION
112 # Above selects are sorted alphabetically; please add new ones
113 # according to that. Thanks.
115 The ARM series is a line of low-power-consumption RISC chip designs
116 licensed by ARM Ltd and targeted at embedded applications and
117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
118 manufactured, but legacy ARM-based PC hardware remains popular in
119 Europe. There is an ARM Linux project with a web page at
120 <http://www.arm.linux.org.uk/>.
122 config ARM_HAS_SG_CHAIN
123 select ARCH_HAS_SG_CHAIN
126 config ARM_DMA_USE_IOMMU
128 select ARM_HAS_SG_CHAIN
129 select NEED_SG_DMA_LENGTH
133 config ARM_DMA_IOMMU_ALIGNMENT
134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
138 DMA mapping framework by default aligns all buffers to the smallest
139 PAGE_SIZE order which is greater than or equal to the requested buffer
140 size. This works well for buffers up to a few hundreds kilobytes, but
141 for larger buffers it just a waste of address space. Drivers which has
142 relatively small addressing window (like 64Mib) might run out of
143 virtual space with just a few allocations.
145 With this parameter you can specify the maximum PAGE_SIZE order for
146 DMA IOMMU buffers. Larger buffers will be aligned only to this
147 specified order. The order is expressed as a power of two multiplied
152 config MIGHT_HAVE_PCI
155 config SYS_SUPPORTS_APM_EMULATION
160 select GENERIC_ALLOCATOR
171 The Extended Industry Standard Architecture (EISA) bus was
172 developed as an open alternative to the IBM MicroChannel bus.
174 The EISA bus provided some of the features of the IBM MicroChannel
175 bus while maintaining backward compatibility with cards made for
176 the older ISA bus. The EISA bus saw limited use between 1988 and
177 1995 when it was made obsolete by the PCI bus.
179 Say Y here if you are building a kernel for an EISA-based machine.
186 config STACKTRACE_SUPPORT
190 config LOCKDEP_SUPPORT
194 config TRACE_IRQFLAGS_SUPPORT
198 config RWSEM_XCHGADD_ALGORITHM
202 config ARCH_HAS_ILOG2_U32
205 config ARCH_HAS_ILOG2_U64
208 config ARCH_HAS_BANDGAP
211 config FIX_EARLYCON_MEM
214 config GENERIC_HWEIGHT
218 config GENERIC_CALIBRATE_DELAY
222 config ARCH_MAY_HAVE_PC_FDC
228 config ARCH_SUPPORTS_UPROBES
231 config ARCH_HAS_DMA_SET_COHERENT_MASK
234 config GENERIC_ISA_DMA
240 config NEED_RET_TO_USER
246 config ARM_PATCH_PHYS_VIRT
247 bool "Patch physical to virtual translations at runtime" if EMBEDDED
249 depends on !XIP_KERNEL && MMU
251 Patch phys-to-virt and virt-to-phys translation functions at
252 boot and module load time according to the position of the
253 kernel in system memory.
255 This can only be used with non-XIP MMU kernels where the base
256 of physical memory is at a 16MB boundary.
258 Only disable this option if you know that you do not require
259 this feature (eg, building a kernel for a single machine) and
260 you need to shrink the kernel to the minimal size.
262 config NEED_MACH_IO_H
265 Select this when mach/io.h is required to provide special
266 definitions for this platform. The need for mach/io.h should
267 be avoided when possible.
269 config NEED_MACH_MEMORY_H
272 Select this when mach/memory.h is required to provide special
273 definitions for this platform. The need for mach/memory.h should
274 be avoided when possible.
277 hex "Physical address of main memory" if MMU
278 depends on !ARM_PATCH_PHYS_VIRT
279 default DRAM_BASE if !MMU
280 default 0x00000000 if ARCH_EBSA110 || \
286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
287 default 0x20000000 if ARCH_S5PV210
288 default 0xc0000000 if ARCH_SA1100
290 Please provide the physical address corresponding to the
291 location of main memory in your system.
297 config PGTABLE_LEVELS
299 default 3 if ARM_LPAE
305 bool "MMU-based Paged Memory Management Support"
308 Select if you want MMU-based virtualised addressing space
309 support by paged memory management. If unsure, say 'Y'.
311 config ARCH_MMAP_RND_BITS_MIN
314 config ARCH_MMAP_RND_BITS_MAX
315 default 14 if PAGE_OFFSET=0x40000000
316 default 15 if PAGE_OFFSET=0x80000000
320 # The "ARM system type" choice list is ordered alphabetically by option
321 # text. Please add new entries in the option alphabetic order.
324 prompt "ARM system type"
325 default ARM_SINGLE_ARMV7M if !MMU
326 default ARCH_MULTIPLATFORM if MMU
328 config ARCH_MULTIPLATFORM
329 bool "Allow multiple platforms to be selected"
331 select ARM_HAS_SG_CHAIN
332 select ARM_PATCH_PHYS_VIRT
336 select GENERIC_CLOCKEVENTS
337 select GENERIC_IRQ_MULTI_HANDLER
338 select MIGHT_HAVE_PCI
339 select PCI_DOMAINS if PCI
343 config ARM_SINGLE_ARMV7M
344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
351 select GENERIC_CLOCKEVENTS
358 select ARCH_USES_GETTIMEOFFSET
361 select NEED_MACH_IO_H
362 select NEED_MACH_MEMORY_H
365 This is an evaluation board for the StrongARM processor available
366 from Digital. It has limited hardware on-board, including an
367 Ethernet interface, two PCMCIA sockets, two serial ports and a
372 select ARCH_SPARSEMEM_ENABLE
374 imply ARM_PATCH_PHYS_VIRT
380 select GENERIC_CLOCKEVENTS
383 This enables support for the Cirrus EP93xx series of CPUs.
385 config ARCH_FOOTBRIDGE
389 select GENERIC_CLOCKEVENTS
391 select NEED_MACH_IO_H if !MMU
392 select NEED_MACH_MEMORY_H
394 Support for systems based on the DC21285 companion chip
395 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
398 bool "Hilscher NetX based"
402 select GENERIC_CLOCKEVENTS
404 This enables support for systems based on the Hilscher NetX Soc
410 select NEED_MACH_MEMORY_H
411 select NEED_RET_TO_USER
417 Support for Intel's IOP13XX (XScale) family of processors.
425 select NEED_RET_TO_USER
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select NEED_RET_TO_USER
442 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_HAS_DMA_SET_COHERENT_MASK
448 select ARCH_SUPPORTS_BIG_ENDIAN
451 select DMABOUNCE if PCI
452 select GENERIC_CLOCKEVENTS
454 select MIGHT_HAVE_PCI
455 select NEED_MACH_IO_H
456 select USB_EHCI_BIG_ENDIAN_DESC
457 select USB_EHCI_BIG_ENDIAN_MMIO
459 Support for Intel's IXP4XX (XScale) family of processors.
464 select GENERIC_CLOCKEVENTS
465 select GENERIC_IRQ_MULTI_HANDLER
467 select MIGHT_HAVE_PCI
471 select PLAT_ORION_LEGACY
473 select PM_GENERIC_DOMAINS if PM
475 Support for the Marvell Dove SoC 88AP510
478 bool "Micrel/Kendin KS8695"
481 select GENERIC_CLOCKEVENTS
483 select NEED_MACH_MEMORY_H
485 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
486 System-on-Chip devices.
489 bool "Nuvoton W90X900 CPU"
493 select GENERIC_CLOCKEVENTS
496 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
497 At present, the w90x900 has been renamed nuc900, regarding
498 the ARM series product line, you can login the following
499 link address to know more.
501 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
502 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
508 select CLKSRC_LPC32XX
511 select GENERIC_CLOCKEVENTS
512 select GENERIC_IRQ_MULTI_HANDLER
517 Support for the NXP LPC32XX family of processors
520 bool "PXA2xx/PXA3xx-based"
523 select ARM_CPU_SUSPEND if PM
530 select CPU_XSCALE if !CPU_XSC3
531 select GENERIC_CLOCKEVENTS
532 select GENERIC_IRQ_MULTI_HANDLER
540 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
546 select ARCH_MAY_HAVE_PC_FDC
547 select ARCH_SPARSEMEM_ENABLE
548 select ARCH_USES_GETTIMEOFFSET
552 select HAVE_PATA_PLATFORM
554 select NEED_MACH_IO_H
555 select NEED_MACH_MEMORY_H
558 On the Acorn Risc-PC, Linux can support the internal IDE disk and
559 CD-ROM interface, serial and parallel port, and the floppy drive.
564 select ARCH_SPARSEMEM_ENABLE
568 select TIMER_OF if OF
571 select GENERIC_CLOCKEVENTS
572 select GENERIC_IRQ_MULTI_HANDLER
577 select NEED_MACH_MEMORY_H
580 Support for StrongARM 11x0 based boards.
583 bool "Samsung S3C24XX SoCs"
586 select CLKSRC_SAMSUNG_PWM
587 select GENERIC_CLOCKEVENTS
590 select GENERIC_IRQ_MULTI_HANDLER
591 select HAVE_S3C2410_I2C if I2C
592 select HAVE_S3C2410_WATCHDOG if WATCHDOG
593 select HAVE_S3C_RTC if RTC_CLASS
594 select NEED_MACH_IO_H
598 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
599 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
600 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
601 Samsung SMDK2410 development board (and derivatives).
605 select ARCH_HAS_HOLES_MEMORYMODEL
608 select GENERIC_ALLOCATOR
609 select GENERIC_CLOCKEVENTS
610 select GENERIC_IRQ_CHIP
613 select PM_GENERIC_DOMAINS if PM
614 select PM_GENERIC_DOMAINS_OF if PM && OF
615 select RESET_CONTROLLER
619 Support for TI's DaVinci platform.
624 select ARCH_HAS_HOLES_MEMORYMODEL
628 select GENERIC_CLOCKEVENTS
629 select GENERIC_IRQ_CHIP
630 select GENERIC_IRQ_MULTI_HANDLER
634 select NEED_MACH_IO_H if PCCARD
635 select NEED_MACH_MEMORY_H
638 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
642 menu "Multiple platform selection"
643 depends on ARCH_MULTIPLATFORM
645 comment "CPU Core family selection"
648 bool "ARMv4 based platforms (FA526)"
649 depends on !ARCH_MULTI_V6_V7
650 select ARCH_MULTI_V4_V5
653 config ARCH_MULTI_V4T
654 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
655 depends on !ARCH_MULTI_V6_V7
656 select ARCH_MULTI_V4_V5
657 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
658 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
659 CPU_ARM925T || CPU_ARM940T)
662 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
663 depends on !ARCH_MULTI_V6_V7
664 select ARCH_MULTI_V4_V5
665 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
666 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
667 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
669 config ARCH_MULTI_V4_V5
673 bool "ARMv6 based platforms (ARM11)"
674 select ARCH_MULTI_V6_V7
678 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
680 select ARCH_MULTI_V6_V7
684 config ARCH_MULTI_V6_V7
686 select MIGHT_HAVE_CACHE_L2X0
688 config ARCH_MULTI_CPU_AUTO
689 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
695 bool "Dummy Virtual Machine"
696 depends on ARCH_MULTI_V7
699 select ARM_GIC_V2M if PCI
701 select ARM_GIC_V3_ITS if PCI
703 select HAVE_ARM_ARCH_TIMER
704 select ARCH_SUPPORTS_BIG_ENDIAN
707 # This is sorted alphabetically by mach-* pathname. However, plat-*
708 # Kconfigs may be included either alphabetically (according to the
709 # plat- suffix) or along side the corresponding mach-* source.
711 source "arch/arm/mach-actions/Kconfig"
713 source "arch/arm/mach-alpine/Kconfig"
715 source "arch/arm/mach-artpec/Kconfig"
717 source "arch/arm/mach-asm9260/Kconfig"
719 source "arch/arm/mach-aspeed/Kconfig"
721 source "arch/arm/mach-at91/Kconfig"
723 source "arch/arm/mach-axxia/Kconfig"
725 source "arch/arm/mach-bcm/Kconfig"
727 source "arch/arm/mach-berlin/Kconfig"
729 source "arch/arm/mach-clps711x/Kconfig"
731 source "arch/arm/mach-cns3xxx/Kconfig"
733 source "arch/arm/mach-davinci/Kconfig"
735 source "arch/arm/mach-digicolor/Kconfig"
737 source "arch/arm/mach-dove/Kconfig"
739 source "arch/arm/mach-ep93xx/Kconfig"
741 source "arch/arm/mach-exynos/Kconfig"
742 source "arch/arm/plat-samsung/Kconfig"
744 source "arch/arm/mach-footbridge/Kconfig"
746 source "arch/arm/mach-gemini/Kconfig"
748 source "arch/arm/mach-highbank/Kconfig"
750 source "arch/arm/mach-hisi/Kconfig"
752 source "arch/arm/mach-imx/Kconfig"
754 source "arch/arm/mach-integrator/Kconfig"
756 source "arch/arm/mach-iop13xx/Kconfig"
758 source "arch/arm/mach-iop32x/Kconfig"
760 source "arch/arm/mach-iop33x/Kconfig"
762 source "arch/arm/mach-ixp4xx/Kconfig"
764 source "arch/arm/mach-keystone/Kconfig"
766 source "arch/arm/mach-ks8695/Kconfig"
768 source "arch/arm/mach-mediatek/Kconfig"
770 source "arch/arm/mach-meson/Kconfig"
772 source "arch/arm/mach-mmp/Kconfig"
774 source "arch/arm/mach-moxart/Kconfig"
776 source "arch/arm/mach-mv78xx0/Kconfig"
778 source "arch/arm/mach-mvebu/Kconfig"
780 source "arch/arm/mach-mxs/Kconfig"
782 source "arch/arm/mach-netx/Kconfig"
784 source "arch/arm/mach-nomadik/Kconfig"
786 source "arch/arm/mach-npcm/Kconfig"
788 source "arch/arm/mach-nspire/Kconfig"
790 source "arch/arm/plat-omap/Kconfig"
792 source "arch/arm/mach-omap1/Kconfig"
794 source "arch/arm/mach-omap2/Kconfig"
796 source "arch/arm/mach-orion5x/Kconfig"
798 source "arch/arm/mach-oxnas/Kconfig"
800 source "arch/arm/mach-picoxcell/Kconfig"
802 source "arch/arm/mach-prima2/Kconfig"
804 source "arch/arm/mach-pxa/Kconfig"
805 source "arch/arm/plat-pxa/Kconfig"
807 source "arch/arm/mach-qcom/Kconfig"
809 source "arch/arm/mach-realview/Kconfig"
811 source "arch/arm/mach-rockchip/Kconfig"
813 source "arch/arm/mach-s3c24xx/Kconfig"
815 source "arch/arm/mach-s3c64xx/Kconfig"
817 source "arch/arm/mach-s5pv210/Kconfig"
819 source "arch/arm/mach-sa1100/Kconfig"
821 source "arch/arm/mach-shmobile/Kconfig"
823 source "arch/arm/mach-socfpga/Kconfig"
825 source "arch/arm/mach-spear/Kconfig"
827 source "arch/arm/mach-sti/Kconfig"
829 source "arch/arm/mach-stm32/Kconfig"
831 source "arch/arm/mach-sunxi/Kconfig"
833 source "arch/arm/mach-tango/Kconfig"
835 source "arch/arm/mach-tegra/Kconfig"
837 source "arch/arm/mach-u300/Kconfig"
839 source "arch/arm/mach-uniphier/Kconfig"
841 source "arch/arm/mach-ux500/Kconfig"
843 source "arch/arm/mach-versatile/Kconfig"
845 source "arch/arm/mach-vexpress/Kconfig"
846 source "arch/arm/plat-versatile/Kconfig"
848 source "arch/arm/mach-vt8500/Kconfig"
850 source "arch/arm/mach-w90x900/Kconfig"
852 source "arch/arm/mach-zx/Kconfig"
854 source "arch/arm/mach-zynq/Kconfig"
856 # ARMv7-M architecture
858 bool "Energy Micro efm32"
859 depends on ARM_SINGLE_ARMV7M
862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
866 bool "NXP LPC18xx/LPC43xx"
867 depends on ARM_SINGLE_ARMV7M
868 select ARCH_HAS_RESET_CONTROLLER
870 select CLKSRC_LPC32XX
873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
874 high performance microcontrollers.
877 bool "ARM MPS2 platform"
878 depends on ARM_SINGLE_ARMV7M
882 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
883 with a range of available cores like Cortex-M3/M4/M7.
885 Please, note that depends which Application Note is used memory map
886 for the platform may vary, so adjustment of RAM base might be needed.
888 # Definitions to make life easier
894 select GENERIC_CLOCKEVENTS
900 select GENERIC_IRQ_CHIP
903 config PLAT_ORION_LEGACY
910 config PLAT_VERSATILE
913 source "arch/arm/firmware/Kconfig"
915 source arch/arm/mm/Kconfig
918 bool "Enable iWMMXt support"
919 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
920 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
922 Enable support for iWMMXt context switching at run time if
923 running on a CPU that supports it.
926 source "arch/arm/Kconfig-nommu"
929 config PJ4B_ERRATA_4742
930 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
931 depends on CPU_PJ4B && MACH_ARMADA_370
934 When coming out of either a Wait for Interrupt (WFI) or a Wait for
935 Event (WFE) IDLE states, a specific timing sensitivity exists between
936 the retiring WFI/WFE instructions and the newly issued subsequent
937 instructions. This sensitivity can result in a CPU hang scenario.
939 The software must insert either a Data Synchronization Barrier (DSB)
940 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
943 config ARM_ERRATA_326103
944 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
947 Executing a SWP instruction to read-only memory does not set bit 11
948 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
949 treat the access as a read, preventing a COW from occurring and
950 causing the faulting task to livelock.
952 config ARM_ERRATA_411920
953 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
954 depends on CPU_V6 || CPU_V6K
956 Invalidation of the Instruction Cache operation can
957 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
958 It does not affect the MPCore. This option enables the ARM Ltd.
959 recommended workaround.
961 config ARM_ERRATA_430973
962 bool "ARM errata: Stale prediction on replaced interworking branch"
965 This option enables the workaround for the 430973 Cortex-A8
966 r1p* erratum. If a code sequence containing an ARM/Thumb
967 interworking branch is replaced with another code sequence at the
968 same virtual address, whether due to self-modifying code or virtual
969 to physical address re-mapping, Cortex-A8 does not recover from the
970 stale interworking branch prediction. This results in Cortex-A8
971 executing the new code sequence in the incorrect ARM or Thumb state.
972 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
973 and also flushes the branch target cache at every context switch.
974 Note that setting specific bits in the ACTLR register may not be
975 available in non-secure mode.
977 config ARM_ERRATA_458693
978 bool "ARM errata: Processor deadlock when a false hazard is created"
980 depends on !ARCH_MULTIPLATFORM
982 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
983 erratum. For very specific sequences of memory operations, it is
984 possible for a hazard condition intended for a cache line to instead
985 be incorrectly associated with a different cache line. This false
986 hazard might then cause a processor deadlock. The workaround enables
987 the L1 caching of the NEON accesses and disables the PLD instruction
988 in the ACTLR register. Note that setting specific bits in the ACTLR
989 register may not be available in non-secure mode.
991 config ARM_ERRATA_460075
992 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
994 depends on !ARCH_MULTIPLATFORM
996 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
997 erratum. Any asynchronous access to the L2 cache may encounter a
998 situation in which recent store transactions to the L2 cache are lost
999 and overwritten with stale memory contents from external memory. The
1000 workaround disables the write-allocate mode for the L2 cache via the
1001 ACTLR register. Note that setting specific bits in the ACTLR register
1002 may not be available in non-secure mode.
1004 config ARM_ERRATA_742230
1005 bool "ARM errata: DMB operation may be faulty"
1006 depends on CPU_V7 && SMP
1007 depends on !ARCH_MULTIPLATFORM
1009 This option enables the workaround for the 742230 Cortex-A9
1010 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1011 between two write operations may not ensure the correct visibility
1012 ordering of the two writes. This workaround sets a specific bit in
1013 the diagnostic register of the Cortex-A9 which causes the DMB
1014 instruction to behave as a DSB, ensuring the correct behaviour of
1017 config ARM_ERRATA_742231
1018 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1019 depends on CPU_V7 && SMP
1020 depends on !ARCH_MULTIPLATFORM
1022 This option enables the workaround for the 742231 Cortex-A9
1023 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1024 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1025 accessing some data located in the same cache line, may get corrupted
1026 data due to bad handling of the address hazard when the line gets
1027 replaced from one of the CPUs at the same time as another CPU is
1028 accessing it. This workaround sets specific bits in the diagnostic
1029 register of the Cortex-A9 which reduces the linefill issuing
1030 capabilities of the processor.
1032 config ARM_ERRATA_643719
1033 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1034 depends on CPU_V7 && SMP
1037 This option enables the workaround for the 643719 Cortex-A9 (prior to
1038 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1039 register returns zero when it should return one. The workaround
1040 corrects this value, ensuring cache maintenance operations which use
1041 it behave as intended and avoiding data corruption.
1043 config ARM_ERRATA_720789
1044 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1047 This option enables the workaround for the 720789 Cortex-A9 (prior to
1048 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1049 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1050 As a consequence of this erratum, some TLB entries which should be
1051 invalidated are not, resulting in an incoherency in the system page
1052 tables. The workaround changes the TLB flushing routines to invalidate
1053 entries regardless of the ASID.
1055 config ARM_ERRATA_743622
1056 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1058 depends on !ARCH_MULTIPLATFORM
1060 This option enables the workaround for the 743622 Cortex-A9
1061 (r2p*) erratum. Under very rare conditions, a faulty
1062 optimisation in the Cortex-A9 Store Buffer may lead to data
1063 corruption. This workaround sets a specific bit in the diagnostic
1064 register of the Cortex-A9 which disables the Store Buffer
1065 optimisation, preventing the defect from occurring. This has no
1066 visible impact on the overall performance or power consumption of the
1069 config ARM_ERRATA_751472
1070 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 751472 Cortex-A9 (prior
1075 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1076 completion of a following broadcasted operation if the second
1077 operation is received by a CPU before the ICIALLUIS has completed,
1078 potentially leading to corrupted entries in the cache or TLB.
1080 config ARM_ERRATA_754322
1081 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1084 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1085 r3p*) erratum. A speculative memory access may cause a page table walk
1086 which starts prior to an ASID switch but completes afterwards. This
1087 can populate the micro-TLB with a stale entry which may be hit with
1088 the new ASID. This workaround places two dsb instructions in the mm
1089 switching code so that no page table walks can cross the ASID switch.
1091 config ARM_ERRATA_754327
1092 bool "ARM errata: no automatic Store Buffer drain"
1093 depends on CPU_V7 && SMP
1095 This option enables the workaround for the 754327 Cortex-A9 (prior to
1096 r2p0) erratum. The Store Buffer does not have any automatic draining
1097 mechanism and therefore a livelock may occur if an external agent
1098 continuously polls a memory location waiting to observe an update.
1099 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1100 written polling loops from denying visibility of updates to memory.
1102 config ARM_ERRATA_364296
1103 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1106 This options enables the workaround for the 364296 ARM1136
1107 r0p2 erratum (possible cache data corruption with
1108 hit-under-miss enabled). It sets the undocumented bit 31 in
1109 the auxiliary control register and the FI bit in the control
1110 register, thus disabling hit-under-miss without putting the
1111 processor into full low interrupt latency mode. ARM11MPCore
1114 config ARM_ERRATA_764369
1115 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1116 depends on CPU_V7 && SMP
1118 This option enables the workaround for erratum 764369
1119 affecting Cortex-A9 MPCore with two or more processors (all
1120 current revisions). Under certain timing circumstances, a data
1121 cache line maintenance operation by MVA targeting an Inner
1122 Shareable memory region may fail to proceed up to either the
1123 Point of Coherency or to the Point of Unification of the
1124 system. This workaround adds a DSB instruction before the
1125 relevant cache maintenance functions and sets a specific bit
1126 in the diagnostic control register of the SCU.
1128 config ARM_ERRATA_775420
1129 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1132 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1133 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1134 operation aborts with MMU exception, it might cause the processor
1135 to deadlock. This workaround puts DSB before executing ISB if
1136 an abort may occur on cache maintenance.
1138 config ARM_ERRATA_798181
1139 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1140 depends on CPU_V7 && SMP
1142 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1143 adequately shooting down all use of the old entries. This
1144 option enables the Linux kernel workaround for this erratum
1145 which sends an IPI to the CPUs that are running the same ASID
1146 as the one being invalidated.
1148 config ARM_ERRATA_773022
1149 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1152 This option enables the workaround for the 773022 Cortex-A15
1153 (up to r0p4) erratum. In certain rare sequences of code, the
1154 loop buffer may deliver incorrect instructions. This
1155 workaround disables the loop buffer to avoid the erratum.
1157 config ARM_ERRATA_818325_852422
1158 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1161 This option enables the workaround for:
1162 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1163 instruction might deadlock. Fixed in r0p1.
1164 - Cortex-A12 852422: Execution of a sequence of instructions might
1165 lead to either a data corruption or a CPU deadlock. Not fixed in
1166 any Cortex-A12 cores yet.
1167 This workaround for all both errata involves setting bit[12] of the
1168 Feature Register. This bit disables an optimisation applied to a
1169 sequence of 2 instructions that use opposing condition codes.
1171 config ARM_ERRATA_821420
1172 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1175 This option enables the workaround for the 821420 Cortex-A12
1176 (all revs) erratum. In very rare timing conditions, a sequence
1177 of VMOV to Core registers instructions, for which the second
1178 one is in the shadow of a branch or abort, can lead to a
1179 deadlock when the VMOV instructions are issued out-of-order.
1181 config ARM_ERRATA_825619
1182 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1185 This option enables the workaround for the 825619 Cortex-A12
1186 (all revs) erratum. Within rare timing constraints, executing a
1187 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1188 and Device/Strongly-Ordered loads and stores might cause deadlock
1190 config ARM_ERRATA_852421
1191 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1194 This option enables the workaround for the 852421 Cortex-A17
1195 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1196 execution of a DMB ST instruction might fail to properly order
1197 stores from GroupA and stores from GroupB.
1199 config ARM_ERRATA_852423
1200 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1203 This option enables the workaround for:
1204 - Cortex-A17 852423: Execution of a sequence of instructions might
1205 lead to either a data corruption or a CPU deadlock. Not fixed in
1206 any Cortex-A17 cores yet.
1207 This is identical to Cortex-A12 erratum 852422. It is a separate
1208 config option from the A12 erratum due to the way errata are checked
1213 source "arch/arm/common/Kconfig"
1220 Find out whether you have ISA slots on your motherboard. ISA is the
1221 name of a bus system, i.e. the way the CPU talks to the other stuff
1222 inside your box. Other bus systems are PCI, EISA, MicroChannel
1223 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1224 newer boards don't support it. If you have ISA, say Y, otherwise N.
1226 # Select ISA DMA controller support
1231 # Select ISA DMA interface
1236 bool "PCI support" if MIGHT_HAVE_PCI
1238 Find out whether you have a PCI motherboard. PCI is the name of a
1239 bus system, i.e. the way the CPU talks to the other stuff inside
1240 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1241 VESA. If you have PCI, say Y, otherwise N.
1244 bool "Support for multiple PCI domains"
1247 Enable PCI domains kernel management. Say Y if your machine
1248 has a PCI bus hierarchy that requires more than one PCI
1249 domain (aka segment) to be correctly managed. Say N otherwise.
1251 If you don't know what to do here, say N.
1253 config PCI_DOMAINS_GENERIC
1254 def_bool PCI_DOMAINS
1256 config PCI_NANOENGINE
1257 bool "BSE nanoEngine PCI support"
1258 depends on SA1100_NANOENGINE
1260 Enable PCI on the BSE nanoEngine board.
1265 config PCI_HOST_ITE8152
1267 depends on PCI && MACH_ARMCORE
1271 source "drivers/pci/Kconfig"
1273 source "drivers/pcmcia/Kconfig"
1277 menu "Kernel Features"
1282 This option should be selected by machines which have an SMP-
1285 The only effect of this option is to make the SMP-related
1286 options available to the user for configuration.
1289 bool "Symmetric Multi-Processing"
1290 depends on CPU_V6K || CPU_V7
1291 depends on GENERIC_CLOCKEVENTS
1293 depends on MMU || ARM_MPU
1296 This enables support for systems with more than one CPU. If you have
1297 a system with only one CPU, say N. If you have a system with more
1298 than one CPU, say Y.
1300 If you say N here, the kernel will run on uni- and multiprocessor
1301 machines, but will use only one CPU of a multiprocessor machine. If
1302 you say Y here, the kernel will run on many, but not all,
1303 uniprocessor machines. On a uniprocessor machine, the kernel
1304 will run faster if you say N here.
1306 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1307 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1308 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1310 If you don't know what to do here, say N.
1313 bool "Allow booting SMP kernel on uniprocessor systems"
1314 depends on SMP && !XIP_KERNEL && MMU
1317 SMP kernels contain instructions which fail on non-SMP processors.
1318 Enabling this option allows the kernel to modify itself to make
1319 these instructions safe. Disabling it allows about 1K of space
1322 If you don't know what to do here, say Y.
1324 config ARM_CPU_TOPOLOGY
1325 bool "Support cpu topology definition"
1326 depends on SMP && CPU_V7
1329 Support ARM cpu topology definition. The MPIDR register defines
1330 affinity between processors which is then used to describe the cpu
1331 topology of an ARM System.
1334 bool "Multi-core scheduler support"
1335 depends on ARM_CPU_TOPOLOGY
1337 Multi-core scheduler support improves the CPU scheduler's decision
1338 making when dealing with multi-core CPU chips at a cost of slightly
1339 increased overhead in some places. If unsure say N here.
1342 bool "SMT scheduler support"
1343 depends on ARM_CPU_TOPOLOGY
1345 Improves the CPU scheduler's decision making when dealing with
1346 MultiThreading at a cost of slightly increased overhead in some
1347 places. If unsure say N here.
1352 This option enables support for the ARM system coherency unit
1354 config HAVE_ARM_ARCH_TIMER
1355 bool "Architected timer support"
1357 select ARM_ARCH_TIMER
1358 select GENERIC_CLOCKEVENTS
1360 This option enables support for the ARM architected timer
1364 select TIMER_OF if OF
1366 This options enables support for the ARM timer and watchdog unit
1369 bool "Multi-Cluster Power Management"
1370 depends on CPU_V7 && SMP
1372 This option provides the common power management infrastructure
1373 for (multi-)cluster based systems, such as big.LITTLE based
1376 config MCPM_QUAD_CLUSTER
1380 To avoid wasting resources unnecessarily, MCPM only supports up
1381 to 2 clusters by default.
1382 Platforms with 3 or 4 clusters that use MCPM must select this
1383 option to allow the additional clusters to be managed.
1386 bool "big.LITTLE support (Experimental)"
1387 depends on CPU_V7 && SMP
1390 This option enables support selections for the big.LITTLE
1391 system architecture.
1394 bool "big.LITTLE switcher support"
1395 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1398 The big.LITTLE "switcher" provides the core functionality to
1399 transparently handle transition between a cluster of A15's
1400 and a cluster of A7's in a big.LITTLE system.
1402 config BL_SWITCHER_DUMMY_IF
1403 tristate "Simple big.LITTLE switcher user interface"
1404 depends on BL_SWITCHER && DEBUG_KERNEL
1406 This is a simple and dummy char dev interface to control
1407 the big.LITTLE switcher core code. It is meant for
1408 debugging purposes only.
1411 prompt "Memory split"
1415 Select the desired split between kernel and user memory.
1417 If you are not absolutely sure what you are doing, leave this
1421 bool "3G/1G user/kernel split"
1422 config VMSPLIT_3G_OPT
1423 depends on !ARM_LPAE
1424 bool "3G/1G user/kernel split (for full 1G low memory)"
1426 bool "2G/2G user/kernel split"
1428 bool "1G/3G user/kernel split"
1433 default PHYS_OFFSET if !MMU
1434 default 0x40000000 if VMSPLIT_1G
1435 default 0x80000000 if VMSPLIT_2G
1436 default 0xB0000000 if VMSPLIT_3G_OPT
1440 int "Maximum number of CPUs (2-32)"
1446 bool "Support for hot-pluggable CPUs"
1449 Say Y here to experiment with turning CPUs off and on. CPUs
1450 can be controlled through /sys/devices/system/cpu.
1453 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1454 depends on HAVE_ARM_SMCCC
1457 Say Y here if you want Linux to communicate with system firmware
1458 implementing the PSCI specification for CPU-centric power
1459 management operations described in ARM document number ARM DEN
1460 0022A ("Power State Coordination Interface System Software on
1463 # The GPIO number here must be sorted by descending number. In case of
1464 # a multiplatform kernel, we just want the highest value required by the
1465 # selected platforms.
1468 default 2048 if ARCH_SOCFPGA
1469 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1471 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1472 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1473 default 416 if ARCH_SUNXI
1474 default 392 if ARCH_U8500
1475 default 352 if ARCH_VT8500
1476 default 288 if ARCH_ROCKCHIP
1477 default 264 if MACH_H4700
1480 Maximum number of GPIOs in the system.
1482 If unsure, leave the default value.
1486 default 200 if ARCH_EBSA110
1487 default 128 if SOC_AT91RM9200
1491 depends on HZ_FIXED = 0
1492 prompt "Timer frequency"
1516 default HZ_FIXED if HZ_FIXED != 0
1517 default 100 if HZ_100
1518 default 200 if HZ_200
1519 default 250 if HZ_250
1520 default 300 if HZ_300
1521 default 500 if HZ_500
1525 def_bool HIGH_RES_TIMERS
1527 config THUMB2_KERNEL
1528 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1529 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1530 default y if CPU_THUMBONLY
1533 By enabling this option, the kernel will be compiled in
1538 config THUMB2_AVOID_R_ARM_THM_JUMP11
1539 bool "Work around buggy Thumb-2 short branch relocations in gas"
1540 depends on THUMB2_KERNEL && MODULES
1543 Various binutils versions can resolve Thumb-2 branches to
1544 locally-defined, preemptible global symbols as short-range "b.n"
1545 branch instructions.
1547 This is a problem, because there's no guarantee the final
1548 destination of the symbol, or any candidate locations for a
1549 trampoline, are within range of the branch. For this reason, the
1550 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1551 relocation in modules at all, and it makes little sense to add
1554 The symptom is that the kernel fails with an "unsupported
1555 relocation" error when loading some modules.
1557 Until fixed tools are available, passing
1558 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1559 code which hits this problem, at the cost of a bit of extra runtime
1560 stack usage in some cases.
1562 The problem is described in more detail at:
1563 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1565 Only Thumb-2 kernels are affected.
1567 Unless you are sure your tools don't have this problem, say Y.
1569 config ARM_PATCH_IDIV
1570 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1571 depends on CPU_32v7 && !XIP_KERNEL
1574 The ARM compiler inserts calls to __aeabi_idiv() and
1575 __aeabi_uidiv() when it needs to perform division on signed
1576 and unsigned integers. Some v7 CPUs have support for the sdiv
1577 and udiv instructions that can be used to implement those
1580 Enabling this option allows the kernel to modify itself to
1581 replace the first two instructions of these library functions
1582 with the sdiv or udiv plus "bx lr" instructions when the CPU
1583 it is running on supports them. Typically this will be faster
1584 and less power intensive than running the original library
1585 code to do integer division.
1588 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1589 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1591 This option allows for the kernel to be compiled using the latest
1592 ARM ABI (aka EABI). This is only useful if you are using a user
1593 space environment that is also compiled with EABI.
1595 Since there are major incompatibilities between the legacy ABI and
1596 EABI, especially with regard to structure member alignment, this
1597 option also changes the kernel syscall calling convention to
1598 disambiguate both ABIs and allow for backward compatibility support
1599 (selected with CONFIG_OABI_COMPAT).
1601 To use this you need GCC version 4.0.0 or later.
1604 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1605 depends on AEABI && !THUMB2_KERNEL
1607 This option preserves the old syscall interface along with the
1608 new (ARM EABI) one. It also provides a compatibility layer to
1609 intercept syscalls that have structure arguments which layout
1610 in memory differs between the legacy ABI and the new ARM EABI
1611 (only for non "thumb" binaries). This option adds a tiny
1612 overhead to all syscalls and produces a slightly larger kernel.
1614 The seccomp filter system will not be available when this is
1615 selected, since there is no way yet to sensibly distinguish
1616 between calling conventions during filtering.
1618 If you know you'll be using only pure EABI user space then you
1619 can say N here. If this option is not selected and you attempt
1620 to execute a legacy ABI binary then the result will be
1621 UNPREDICTABLE (in fact it can be predicted that it won't work
1622 at all). If in doubt say N.
1624 config ARCH_HAS_HOLES_MEMORYMODEL
1627 config ARCH_SPARSEMEM_ENABLE
1630 config ARCH_SPARSEMEM_DEFAULT
1631 def_bool ARCH_SPARSEMEM_ENABLE
1633 config ARCH_SELECT_MEMORY_MODEL
1634 def_bool ARCH_SPARSEMEM_ENABLE
1636 config HAVE_ARCH_PFN_VALID
1637 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1639 config HAVE_GENERIC_GUP
1644 bool "High Memory Support"
1647 The address space of ARM processors is only 4 Gigabytes large
1648 and it has to accommodate user address space, kernel address
1649 space as well as some memory mapped IO. That means that, if you
1650 have a large amount of physical memory and/or IO, not all of the
1651 memory can be "permanently mapped" by the kernel. The physical
1652 memory that is not permanently mapped is called "high memory".
1654 Depending on the selected kernel/user memory split, minimum
1655 vmalloc space and actual amount of RAM, you may not need this
1656 option which should result in a slightly faster kernel.
1661 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1665 The VM uses one page of physical memory for each page table.
1666 For systems with a lot of processes, this can use a lot of
1667 precious low memory, eventually leading to low memory being
1668 consumed by page tables. Setting this option will allow
1669 user-space 2nd level page tables to reside in high memory.
1671 config CPU_SW_DOMAIN_PAN
1672 bool "Enable use of CPU domains to implement privileged no-access"
1673 depends on MMU && !ARM_LPAE
1676 Increase kernel security by ensuring that normal kernel accesses
1677 are unable to access userspace addresses. This can help prevent
1678 use-after-free bugs becoming an exploitable privilege escalation
1679 by ensuring that magic values (such as LIST_POISON) will always
1680 fault when dereferenced.
1682 CPUs with low-vector mappings use a best-efforts implementation.
1683 Their lower 1MB needs to remain accessible for the vectors, but
1684 the remainder of userspace will become appropriately inaccessible.
1686 config HW_PERF_EVENTS
1690 config SYS_SUPPORTS_HUGETLBFS
1694 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1698 config ARCH_WANT_GENERAL_HUGETLB
1701 config ARM_MODULE_PLTS
1702 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706 Allocate PLTs when loading modules so that jumps and calls whose
1707 targets are too far away for their relative offsets to be encoded
1708 in the instructions themselves can be bounced via veneers in the
1709 module's PLT. This allows modules to be allocated in the generic
1710 vmalloc area after the dedicated module memory area has been
1711 exhausted. The modules will use slightly more memory, but after
1712 rounding up to page size, the actual memory footprint is usually
1715 Disabling this is usually safe for small single-platform
1716 configurations. If unsure, say y.
1718 config FORCE_MAX_ZONEORDER
1719 int "Maximum zone order"
1720 default "12" if SOC_AM33XX
1721 default "9" if SA1111 || ARCH_EFM32
1724 The kernel memory allocator divides physically contiguous memory
1725 blocks into "zones", where each zone is a power of two number of
1726 pages. This option selects the largest power of two that the kernel
1727 keeps in the memory allocator. If you need to allocate very large
1728 blocks of physically contiguous memory, then you may need to
1729 increase this value.
1731 This config option is actually maximum order plus one. For example,
1732 a value of 11 means that the largest free memory block is 2^10 pages.
1734 config ALIGNMENT_TRAP
1736 depends on CPU_CP15_MMU
1737 default y if !ARCH_EBSA110
1738 select HAVE_PROC_CPU if PROC_FS
1740 ARM processors cannot fetch/store information which is not
1741 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1742 address divisible by 4. On 32-bit ARM processors, these non-aligned
1743 fetch/store instructions will be emulated in software if you say
1744 here, which has a severe performance impact. This is necessary for
1745 correct operation of some network protocols. With an IP-only
1746 configuration it is safe to say N, otherwise say Y.
1748 config UACCESS_WITH_MEMCPY
1749 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1751 default y if CPU_FEROCEON
1753 Implement faster copy_to_user and clear_user methods for CPU
1754 cores where a 8-word STM instruction give significantly higher
1755 memory write throughput than a sequence of individual 32bit stores.
1757 A possible side effect is a slight increase in scheduling latency
1758 between threads sharing the same address space if they invoke
1759 such copy operations with large buffers.
1761 However, if the CPU data cache is using a write-allocate mode,
1762 this option is unlikely to provide any performance gain.
1766 prompt "Enable seccomp to safely compute untrusted bytecode"
1768 This kernel feature is useful for number crunching applications
1769 that may need to compute untrusted bytecode during their
1770 execution. By using pipes or other transports made available to
1771 the process as file descriptors supporting the read/write
1772 syscalls, it's possible to isolate those applications in
1773 their own address space using seccomp. Once seccomp is
1774 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1775 and the task is only allowed to execute a few safe syscalls
1776 defined by each seccomp mode.
1779 bool "Enable paravirtualization code"
1781 This changes the kernel so it can modify itself when it is run
1782 under a hypervisor, potentially improving performance significantly
1783 over full virtualization.
1785 config PARAVIRT_TIME_ACCOUNTING
1786 bool "Paravirtual steal time accounting"
1790 Select this option to enable fine granularity task steal time
1791 accounting. Time spent executing other tasks in parallel with
1792 the current vCPU is discounted from the vCPU power. To account for
1793 that, there can be a small performance impact.
1795 If in doubt, say N here.
1802 bool "Xen guest support on ARM"
1803 depends on ARM && AEABI && OF
1804 depends on CPU_V7 && !CPU_V6
1805 depends on !GENERIC_ATOMIC64
1807 select ARCH_DMA_ADDR_T_64BIT
1813 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1820 bool "Flattened Device Tree support"
1824 Include support for flattened device tree machine descriptions.
1827 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1830 This is the traditional way of passing data to the kernel at boot
1831 time. If you are solely relying on the flattened device tree (or
1832 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1833 to remove ATAGS support from your kernel binary. If unsure,
1836 config DEPRECATED_PARAM_STRUCT
1837 bool "Provide old way to pass kernel parameters"
1840 This was deprecated in 2001 and announced to live on for 5 years.
1841 Some old boot loaders still use this way.
1843 # Compressed boot loader in ROM. Yes, we really want to ask about
1844 # TEXT and BSS so we preserve their values in the config files.
1845 config ZBOOT_ROM_TEXT
1846 hex "Compressed ROM boot loader base address"
1849 The physical address at which the ROM-able zImage is to be
1850 placed in the target. Platforms which normally make use of
1851 ROM-able zImage formats normally set this to a suitable
1852 value in their defconfig file.
1854 If ZBOOT_ROM is not enabled, this has no effect.
1856 config ZBOOT_ROM_BSS
1857 hex "Compressed ROM boot loader BSS address"
1860 The base address of an area of read/write memory in the target
1861 for the ROM-able zImage which must be available while the
1862 decompressor is running. It must be large enough to hold the
1863 entire decompressed kernel plus an additional 128 KiB.
1864 Platforms which normally make use of ROM-able zImage formats
1865 normally set this to a suitable value in their defconfig file.
1867 If ZBOOT_ROM is not enabled, this has no effect.
1870 bool "Compressed boot loader in ROM/flash"
1871 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1872 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1874 Say Y here if you intend to execute your compressed kernel image
1875 (zImage) directly from ROM or flash. If unsure, say N.
1877 config ARM_APPENDED_DTB
1878 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1881 With this option, the boot code will look for a device tree binary
1882 (DTB) appended to zImage
1883 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1885 This is meant as a backward compatibility convenience for those
1886 systems with a bootloader that can't be upgraded to accommodate
1887 the documented boot protocol using a device tree.
1889 Beware that there is very little in terms of protection against
1890 this option being confused by leftover garbage in memory that might
1891 look like a DTB header after a reboot if no actual DTB is appended
1892 to zImage. Do not leave this option active in a production kernel
1893 if you don't intend to always append a DTB. Proper passing of the
1894 location into r2 of a bootloader provided DTB is always preferable
1897 config ARM_ATAG_DTB_COMPAT
1898 bool "Supplement the appended DTB with traditional ATAG information"
1899 depends on ARM_APPENDED_DTB
1901 Some old bootloaders can't be updated to a DTB capable one, yet
1902 they provide ATAGs with memory configuration, the ramdisk address,
1903 the kernel cmdline string, etc. Such information is dynamically
1904 provided by the bootloader and can't always be stored in a static
1905 DTB. To allow a device tree enabled kernel to be used with such
1906 bootloaders, this option allows zImage to extract the information
1907 from the ATAG list and store it at run time into the appended DTB.
1910 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1911 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1914 bool "Use bootloader kernel arguments if available"
1916 Uses the command-line options passed by the boot loader instead of
1917 the device tree bootargs property. If the boot loader doesn't provide
1918 any, the device tree bootargs property will be used.
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1921 bool "Extend with bootloader kernel arguments"
1923 The command-line arguments provided by the boot loader will be
1924 appended to the the device tree bootargs property.
1929 string "Default kernel command string"
1932 On some architectures (EBSA110 and CATS), there is currently no way
1933 for the boot loader to pass arguments to the kernel. For these
1934 architectures, you should supply some command-line options at build
1935 time by entering them here. As a minimum, you should specify the
1936 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1939 prompt "Kernel command line type" if CMDLINE != ""
1940 default CMDLINE_FROM_BOOTLOADER
1943 config CMDLINE_FROM_BOOTLOADER
1944 bool "Use bootloader kernel arguments if available"
1946 Uses the command-line options passed by the boot loader. If
1947 the boot loader doesn't provide any, the default kernel command
1948 string provided in CMDLINE will be used.
1950 config CMDLINE_EXTEND
1951 bool "Extend bootloader kernel arguments"
1953 The command-line arguments provided by the boot loader will be
1954 appended to the default kernel command string.
1956 config CMDLINE_FORCE
1957 bool "Always use the default kernel command string"
1959 Always use the default kernel command string, even if the boot
1960 loader passes other arguments to the kernel.
1961 This is useful if you cannot or don't want to change the
1962 command-line options your boot loader passes to the kernel.
1966 bool "Kernel Execute-In-Place from ROM"
1967 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1969 Execute-In-Place allows the kernel to run from non-volatile storage
1970 directly addressable by the CPU, such as NOR flash. This saves RAM
1971 space since the text section of the kernel is not loaded from flash
1972 to RAM. Read-write sections, such as the data section and stack,
1973 are still copied to RAM. The XIP kernel is not compressed since
1974 it has to run directly from flash, so it will take more space to
1975 store it. The flash address used to link the kernel object files,
1976 and for storing it, is configuration dependent. Therefore, if you
1977 say Y here, you must know the proper physical address where to
1978 store the kernel image depending on your own flash memory usage.
1980 Also note that the make target becomes "make xipImage" rather than
1981 "make zImage" or "make Image". The final kernel binary to put in
1982 ROM memory will be arch/arm/boot/xipImage.
1986 config XIP_PHYS_ADDR
1987 hex "XIP Kernel Physical Location"
1988 depends on XIP_KERNEL
1989 default "0x00080000"
1991 This is the physical address in your flash memory the kernel will
1992 be linked for and stored to. This address is dependent on your
1995 config XIP_DEFLATED_DATA
1996 bool "Store kernel .data section compressed in ROM"
1997 depends on XIP_KERNEL
2000 Before the kernel is actually executed, its .data section has to be
2001 copied to RAM from ROM. This option allows for storing that data
2002 in compressed form and decompressed to RAM rather than merely being
2003 copied, saving some precious ROM space. A possible drawback is a
2004 slightly longer boot delay.
2007 bool "Kexec system call (EXPERIMENTAL)"
2008 depends on (!SMP || PM_SLEEP_SMP)
2012 kexec is a system call that implements the ability to shutdown your
2013 current kernel, and to start another kernel. It is like a reboot
2014 but it is independent of the system firmware. And like a reboot
2015 you can start any kernel with it, not just Linux.
2017 It is an ongoing process to be certain the hardware in a machine
2018 is properly shutdown, so do not be surprised if this code does not
2019 initially work for you.
2022 bool "Export atags in procfs"
2023 depends on ATAGS && KEXEC
2026 Should the atags used to boot the kernel be exported in an "atags"
2027 file in procfs. Useful with kexec.
2030 bool "Build kdump crash kernel (EXPERIMENTAL)"
2032 Generate crash dump after being started by kexec. This should
2033 be normally only set in special crash dump kernels which are
2034 loaded in the main kernel with kexec-tools into a specially
2035 reserved region and then later executed after a crash by
2036 kdump/kexec. The crash dump kernel must be compiled to a
2037 memory address not used by the main kernel
2039 For more details see Documentation/kdump/kdump.txt
2041 config AUTO_ZRELADDR
2042 bool "Auto calculation of the decompressed kernel image address"
2044 ZRELADDR is the physical address where the decompressed kernel
2045 image will be placed. If AUTO_ZRELADDR is selected, the address
2046 will be determined at run-time by masking the current IP with
2047 0xf8000000. This assumes the zImage being placed in the first 128MB
2048 from start of memory.
2054 bool "UEFI runtime support"
2055 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2057 select EFI_PARAMS_FROM_FDT
2060 select EFI_RUNTIME_WRAPPERS
2062 This option provides support for runtime services provided
2063 by UEFI firmware (such as non-volatile variables, realtime
2064 clock, and platform reset). A UEFI stub is also provided to
2065 allow the kernel to be booted as an EFI application. This
2066 is only useful for kernels that may run on systems that have
2070 bool "Enable support for SMBIOS (DMI) tables"
2074 This enables SMBIOS/DMI feature for systems.
2076 This option is only useful on systems that have UEFI firmware.
2077 However, even with this option, the resultant kernel should
2078 continue to boot on existing non-UEFI platforms.
2080 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2081 i.e., the the practice of identifying the platform via DMI to
2082 decide whether certain workarounds for buggy hardware and/or
2083 firmware need to be enabled. This would require the DMI subsystem
2084 to be enabled much earlier than we do on ARM, which is non-trivial.
2088 menu "CPU Power Management"
2090 source "drivers/cpufreq/Kconfig"
2092 source "drivers/cpuidle/Kconfig"
2096 menu "Floating point emulation"
2098 comment "At least one emulation must be selected"
2101 bool "NWFPE math emulation"
2102 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2104 Say Y to include the NWFPE floating point emulator in the kernel.
2105 This is necessary to run most binaries. Linux does not currently
2106 support floating point hardware so you need to say Y here even if
2107 your machine has an FPA or floating point co-processor podule.
2109 You may say N here if you are going to load the Acorn FPEmulator
2110 early in the bootup.
2113 bool "Support extended precision"
2114 depends on FPE_NWFPE
2116 Say Y to include 80-bit support in the kernel floating-point
2117 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2118 Note that gcc does not generate 80-bit operations by default,
2119 so in most cases this option only enlarges the size of the
2120 floating point emulator without any good reason.
2122 You almost surely want to say N here.
2125 bool "FastFPE math emulation (EXPERIMENTAL)"
2126 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2128 Say Y here to include the FAST floating point emulator in the kernel.
2129 This is an experimental much faster emulator which now also has full
2130 precision for the mantissa. It does not support any exceptions.
2131 It is very simple, and approximately 3-6 times faster than NWFPE.
2133 It should be sufficient for most programs. It may be not suitable
2134 for scientific calculations, but you have to check this for yourself.
2135 If you do not feel you need a faster FP emulation you should better
2139 bool "VFP-format floating point maths"
2140 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2142 Say Y to include VFP support code in the kernel. This is needed
2143 if your hardware includes a VFP unit.
2145 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2146 release notes and additional status information.
2148 Say N if your target does not have VFP hardware.
2156 bool "Advanced SIMD (NEON) Extension support"
2157 depends on VFPv3 && CPU_V7
2159 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2162 config KERNEL_MODE_NEON
2163 bool "Support for NEON in kernel mode"
2164 depends on NEON && AEABI
2166 Say Y to include support for NEON in kernel mode.
2170 menu "Power management options"
2172 source "kernel/power/Kconfig"
2174 config ARCH_SUSPEND_POSSIBLE
2175 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2176 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2179 config ARM_CPU_SUSPEND
2180 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2181 depends on ARCH_SUSPEND_POSSIBLE
2183 config ARCH_HIBERNATION_POSSIBLE
2186 default y if ARCH_SUSPEND_POSSIBLE
2190 source "drivers/firmware/Kconfig"
2193 source "arch/arm/crypto/Kconfig"
2196 source "arch/arm/kvm/Kconfig"