1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_USE_BUILTIN_BSWAP
35 select ARCH_USE_CMPXCHG_LOCKREF
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
39 select BUILDTIME_TABLE_SORT if MMU
40 select CLONE_BACKWARDS
41 select CPU_PM if SUSPEND || CPU_IDLE
42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
43 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_CPU_AUTOPROBE
53 select GENERIC_EARLY_IOREMAP
54 select GENERIC_IDLE_POLL_SETUP
55 select GENERIC_IRQ_PROBE
56 select GENERIC_IRQ_SHOW
57 select GENERIC_IRQ_SHOW_LEVEL
58 select GENERIC_PCI_IOMAP
59 select GENERIC_SCHED_CLOCK
60 select GENERIC_SMP_IDLE_THREAD
61 select GENERIC_STRNCPY_FROM_USER
62 select GENERIC_STRNLEN_USER
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_MMAP_RND_BITS if MMU
70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
72 select HAVE_ARCH_TRACEHOOK
73 select HAVE_ARM_SMCCC if CPU_V7
74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
75 select HAVE_CONTEXT_TRACKING
76 select HAVE_C_RECORDMCOUNT
77 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
78 select HAVE_DMA_CONTIGUOUS if MMU
79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
82 select HAVE_EXIT_THREAD
83 select HAVE_FAST_GUP if ARM_LPAE
84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
87 select HAVE_GCC_PLUGINS
88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
89 select HAVE_IDE if PCI || ISA || PCMCIA
90 select HAVE_IRQ_TIME_ACCOUNTING
91 select HAVE_KERNEL_GZIP
92 select HAVE_KERNEL_LZ4
93 select HAVE_KERNEL_LZMA
94 select HAVE_KERNEL_LZO
96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
97 select HAVE_KRETPROBES if HAVE_KPROBES
98 select HAVE_MOD_ARCH_SPECIFIC
100 select HAVE_OPROFILE if HAVE_PERF_EVENTS
101 select HAVE_OPTPROBES if !THUMB2_KERNEL
102 select HAVE_PERF_EVENTS
103 select HAVE_PERF_REGS
104 select HAVE_PERF_USER_STACK_DUMP
105 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
106 select HAVE_REGS_AND_STACK_ACCESS_API
108 select HAVE_STACKPROTECTOR
109 select HAVE_SYSCALL_TRACEPOINTS
111 select HAVE_VIRT_CPU_ACCOUNTING_GEN
112 select IRQ_FORCED_THREADING
113 select MODULES_USE_ELF_REL
114 select NEED_DMA_MAP_STATE
115 select OF_EARLY_FLATTREE if OF
117 select OLD_SIGSUSPEND3
118 select PCI_SYSCALL if PCI
119 select PERF_USE_VMALLOC
121 select SYS_SUPPORTS_APM_EMULATION
122 # Above selects are sorted alphabetically; please add new ones
123 # according to that. Thanks.
125 The ARM series is a line of low-power-consumption RISC chip designs
126 licensed by ARM Ltd and targeted at embedded applications and
127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
128 manufactured, but legacy ARM-based PC hardware remains popular in
129 Europe. There is an ARM Linux project with a web page at
130 <http://www.arm.linux.org.uk/>.
132 config ARM_HAS_SG_CHAIN
135 config ARM_DMA_USE_IOMMU
137 select ARM_HAS_SG_CHAIN
138 select NEED_SG_DMA_LENGTH
142 config ARM_DMA_IOMMU_ALIGNMENT
143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
147 DMA mapping framework by default aligns all buffers to the smallest
148 PAGE_SIZE order which is greater than or equal to the requested buffer
149 size. This works well for buffers up to a few hundreds kilobytes, but
150 for larger buffers it just a waste of address space. Drivers which has
151 relatively small addressing window (like 64Mib) might run out of
152 virtual space with just a few allocations.
154 With this parameter you can specify the maximum PAGE_SIZE order for
155 DMA IOMMU buffers. Larger buffers will be aligned only to this
156 specified order. The order is expressed as a power of two multiplied
161 config SYS_SUPPORTS_APM_EMULATION
166 select GENERIC_ALLOCATOR
177 config STACKTRACE_SUPPORT
181 config LOCKDEP_SUPPORT
185 config TRACE_IRQFLAGS_SUPPORT
189 config ARCH_HAS_ILOG2_U32
192 config ARCH_HAS_ILOG2_U64
195 config ARCH_HAS_BANDGAP
198 config FIX_EARLYCON_MEM
201 config GENERIC_HWEIGHT
205 config GENERIC_CALIBRATE_DELAY
209 config ARCH_MAY_HAVE_PC_FDC
215 config ARCH_SUPPORTS_UPROBES
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
221 config GENERIC_ISA_DMA
227 config NEED_RET_TO_USER
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
238 Patch phys-to-virt and virt-to-phys translation functions at
239 boot and module load time according to the position of the
240 kernel in system memory.
242 This can only be used with non-XIP MMU kernels where the base
243 of physical memory is at a 16MB boundary.
245 Only disable this option if you know that you do not require
246 this feature (eg, building a kernel for a single machine) and
247 you need to shrink the kernel to the minimal size.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT
266 default DRAM_BASE if !MMU
267 default 0x00000000 if ARCH_EBSA110 || \
271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
272 default 0x20000000 if ARCH_S5PV210
273 default 0xc0000000 if ARCH_SA1100
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 config PGTABLE_LEVELS
284 default 3 if ARM_LPAE
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
296 config ARCH_MMAP_RND_BITS_MIN
299 config ARCH_MMAP_RND_BITS_MAX
300 default 14 if PAGE_OFFSET=0x40000000
301 default 15 if PAGE_OFFSET=0x80000000
305 # The "ARM system type" choice list is ordered alphabetically by option
306 # text. Please add new entries in the option alphabetic order.
309 prompt "ARM system type"
310 default ARM_SINGLE_ARMV7M if !MMU
311 default ARCH_MULTIPLATFORM if MMU
313 config ARCH_MULTIPLATFORM
314 bool "Allow multiple platforms to be selected"
316 select ARCH_FLATMEM_ENABLE
317 select ARCH_SPARSEMEM_ENABLE
318 select ARCH_SELECT_MEMORY_MODEL
319 select ARM_HAS_SG_CHAIN
320 select ARM_PATCH_PHYS_VIRT
324 select GENERIC_CLOCKEVENTS
325 select GENERIC_IRQ_MULTI_HANDLER
327 select PCI_DOMAINS_GENERIC if PCI
331 config ARM_SINGLE_ARMV7M
332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
339 select GENERIC_CLOCKEVENTS
346 select ARCH_USES_GETTIMEOFFSET
349 select NEED_MACH_IO_H
350 select NEED_MACH_MEMORY_H
353 This is an evaluation board for the StrongARM processor available
354 from Digital. It has limited hardware on-board, including an
355 Ethernet interface, two PCMCIA sockets, two serial ports and a
360 select ARCH_SPARSEMEM_ENABLE
362 imply ARM_PATCH_PHYS_VIRT
368 select GENERIC_CLOCKEVENTS
370 select HAVE_LEGACY_CLK
372 This enables support for the Cirrus EP93xx series of CPUs.
374 config ARCH_FOOTBRIDGE
378 select GENERIC_CLOCKEVENTS
380 select NEED_MACH_IO_H if !MMU
381 select NEED_MACH_MEMORY_H
383 Support for systems based on the DC21285 companion chip
384 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
392 select NEED_RET_TO_USER
396 Support for Intel's 80219 and IOP32X (XScale) family of
402 select ARCH_HAS_DMA_SET_COHERENT_MASK
403 select ARCH_SUPPORTS_BIG_ENDIAN
405 select DMABOUNCE if PCI
406 select GENERIC_CLOCKEVENTS
407 select GENERIC_IRQ_MULTI_HANDLER
413 select NEED_MACH_IO_H
414 select USB_EHCI_BIG_ENDIAN_DESC
415 select USB_EHCI_BIG_ENDIAN_MMIO
417 Support for Intel's IXP4XX (XScale) family of processors.
422 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_MULTI_HANDLER
429 select PLAT_ORION_LEGACY
431 select PM_GENERIC_DOMAINS if PM
433 Support for the Marvell Dove SoC 88AP510
436 bool "PXA2xx/PXA3xx-based"
439 select ARM_CPU_SUSPEND if PM
445 select CPU_XSCALE if !CPU_XSC3
446 select GENERIC_CLOCKEVENTS
447 select GENERIC_IRQ_MULTI_HANDLER
455 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
461 select ARCH_MAY_HAVE_PC_FDC
462 select ARCH_SPARSEMEM_ENABLE
463 select ARM_HAS_SG_CHAIN
467 select HAVE_PATA_PLATFORM
469 select NEED_MACH_IO_H
470 select NEED_MACH_MEMORY_H
473 On the Acorn Risc-PC, Linux can support the internal IDE disk and
474 CD-ROM interface, serial and parallel port, and the floppy drive.
479 select ARCH_SPARSEMEM_ENABLE
482 select TIMER_OF if OF
486 select GENERIC_CLOCKEVENTS
487 select GENERIC_IRQ_MULTI_HANDLER
492 select NEED_MACH_MEMORY_H
495 Support for StrongARM 11x0 based boards.
498 bool "Samsung S3C24XX SoCs"
500 select CLKSRC_SAMSUNG_PWM
501 select GENERIC_CLOCKEVENTS
504 select GENERIC_IRQ_MULTI_HANDLER
505 select HAVE_S3C2410_I2C if I2C
506 select HAVE_S3C2410_WATCHDOG if WATCHDOG
507 select HAVE_S3C_RTC if RTC_CLASS
508 select NEED_MACH_IO_H
512 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
513 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
514 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
515 Samsung SMDK2410 development board (and derivatives).
520 select ARCH_HAS_HOLES_MEMORYMODEL
524 select GENERIC_CLOCKEVENTS
525 select GENERIC_IRQ_CHIP
526 select GENERIC_IRQ_MULTI_HANDLER
529 select HAVE_LEGACY_CLK
531 select NEED_MACH_IO_H if PCCARD
532 select NEED_MACH_MEMORY_H
535 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
539 menu "Multiple platform selection"
540 depends on ARCH_MULTIPLATFORM
542 comment "CPU Core family selection"
545 bool "ARMv4 based platforms (FA526)"
546 depends on !ARCH_MULTI_V6_V7
547 select ARCH_MULTI_V4_V5
550 config ARCH_MULTI_V4T
551 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
552 depends on !ARCH_MULTI_V6_V7
553 select ARCH_MULTI_V4_V5
554 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
555 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
556 CPU_ARM925T || CPU_ARM940T)
559 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
560 depends on !ARCH_MULTI_V6_V7
561 select ARCH_MULTI_V4_V5
562 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
563 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
564 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
566 config ARCH_MULTI_V4_V5
570 bool "ARMv6 based platforms (ARM11)"
571 select ARCH_MULTI_V6_V7
575 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
577 select ARCH_MULTI_V6_V7
581 config ARCH_MULTI_V6_V7
583 select MIGHT_HAVE_CACHE_L2X0
585 config ARCH_MULTI_CPU_AUTO
586 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
592 bool "Dummy Virtual Machine"
593 depends on ARCH_MULTI_V7
596 select ARM_GIC_V2M if PCI
598 select ARM_GIC_V3_ITS if PCI
600 select HAVE_ARM_ARCH_TIMER
601 select ARCH_SUPPORTS_BIG_ENDIAN
604 # This is sorted alphabetically by mach-* pathname. However, plat-*
605 # Kconfigs may be included either alphabetically (according to the
606 # plat- suffix) or along side the corresponding mach-* source.
608 source "arch/arm/mach-actions/Kconfig"
610 source "arch/arm/mach-alpine/Kconfig"
612 source "arch/arm/mach-artpec/Kconfig"
614 source "arch/arm/mach-asm9260/Kconfig"
616 source "arch/arm/mach-aspeed/Kconfig"
618 source "arch/arm/mach-at91/Kconfig"
620 source "arch/arm/mach-axxia/Kconfig"
622 source "arch/arm/mach-bcm/Kconfig"
624 source "arch/arm/mach-berlin/Kconfig"
626 source "arch/arm/mach-clps711x/Kconfig"
628 source "arch/arm/mach-cns3xxx/Kconfig"
630 source "arch/arm/mach-davinci/Kconfig"
632 source "arch/arm/mach-digicolor/Kconfig"
634 source "arch/arm/mach-dove/Kconfig"
636 source "arch/arm/mach-ep93xx/Kconfig"
638 source "arch/arm/mach-exynos/Kconfig"
639 source "arch/arm/plat-samsung/Kconfig"
641 source "arch/arm/mach-footbridge/Kconfig"
643 source "arch/arm/mach-gemini/Kconfig"
645 source "arch/arm/mach-highbank/Kconfig"
647 source "arch/arm/mach-hisi/Kconfig"
649 source "arch/arm/mach-imx/Kconfig"
651 source "arch/arm/mach-integrator/Kconfig"
653 source "arch/arm/mach-iop32x/Kconfig"
655 source "arch/arm/mach-ixp4xx/Kconfig"
657 source "arch/arm/mach-keystone/Kconfig"
659 source "arch/arm/mach-lpc32xx/Kconfig"
661 source "arch/arm/mach-mediatek/Kconfig"
663 source "arch/arm/mach-meson/Kconfig"
665 source "arch/arm/mach-milbeaut/Kconfig"
667 source "arch/arm/mach-mmp/Kconfig"
669 source "arch/arm/mach-moxart/Kconfig"
671 source "arch/arm/mach-mstar/Kconfig"
673 source "arch/arm/mach-mv78xx0/Kconfig"
675 source "arch/arm/mach-mvebu/Kconfig"
677 source "arch/arm/mach-mxs/Kconfig"
679 source "arch/arm/mach-nomadik/Kconfig"
681 source "arch/arm/mach-npcm/Kconfig"
683 source "arch/arm/mach-nspire/Kconfig"
685 source "arch/arm/plat-omap/Kconfig"
687 source "arch/arm/mach-omap1/Kconfig"
689 source "arch/arm/mach-omap2/Kconfig"
691 source "arch/arm/mach-orion5x/Kconfig"
693 source "arch/arm/mach-oxnas/Kconfig"
695 source "arch/arm/mach-picoxcell/Kconfig"
697 source "arch/arm/mach-prima2/Kconfig"
699 source "arch/arm/mach-pxa/Kconfig"
700 source "arch/arm/plat-pxa/Kconfig"
702 source "arch/arm/mach-qcom/Kconfig"
704 source "arch/arm/mach-rda/Kconfig"
706 source "arch/arm/mach-realtek/Kconfig"
708 source "arch/arm/mach-realview/Kconfig"
710 source "arch/arm/mach-rockchip/Kconfig"
712 source "arch/arm/mach-s3c24xx/Kconfig"
714 source "arch/arm/mach-s3c64xx/Kconfig"
716 source "arch/arm/mach-s5pv210/Kconfig"
718 source "arch/arm/mach-sa1100/Kconfig"
720 source "arch/arm/mach-shmobile/Kconfig"
722 source "arch/arm/mach-socfpga/Kconfig"
724 source "arch/arm/mach-spear/Kconfig"
726 source "arch/arm/mach-sti/Kconfig"
728 source "arch/arm/mach-stm32/Kconfig"
730 source "arch/arm/mach-sunxi/Kconfig"
732 source "arch/arm/mach-tango/Kconfig"
734 source "arch/arm/mach-tegra/Kconfig"
736 source "arch/arm/mach-u300/Kconfig"
738 source "arch/arm/mach-uniphier/Kconfig"
740 source "arch/arm/mach-ux500/Kconfig"
742 source "arch/arm/mach-versatile/Kconfig"
744 source "arch/arm/mach-vexpress/Kconfig"
746 source "arch/arm/mach-vt8500/Kconfig"
748 source "arch/arm/mach-zx/Kconfig"
750 source "arch/arm/mach-zynq/Kconfig"
752 # ARMv7-M architecture
754 bool "Energy Micro efm32"
755 depends on ARM_SINGLE_ARMV7M
758 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
762 bool "NXP LPC18xx/LPC43xx"
763 depends on ARM_SINGLE_ARMV7M
764 select ARCH_HAS_RESET_CONTROLLER
766 select CLKSRC_LPC32XX
769 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
770 high performance microcontrollers.
773 bool "ARM MPS2 platform"
774 depends on ARM_SINGLE_ARMV7M
778 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
779 with a range of available cores like Cortex-M3/M4/M7.
781 Please, note that depends which Application Note is used memory map
782 for the platform may vary, so adjustment of RAM base might be needed.
784 # Definitions to make life easier
790 select GENERIC_CLOCKEVENTS
796 select GENERIC_IRQ_CHIP
799 config PLAT_ORION_LEGACY
806 config PLAT_VERSATILE
809 source "arch/arm/mm/Kconfig"
812 bool "Enable iWMMXt support"
813 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
814 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
816 Enable support for iWMMXt context switching at run time if
817 running on a CPU that supports it.
820 source "arch/arm/Kconfig-nommu"
823 config PJ4B_ERRATA_4742
824 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
825 depends on CPU_PJ4B && MACH_ARMADA_370
828 When coming out of either a Wait for Interrupt (WFI) or a Wait for
829 Event (WFE) IDLE states, a specific timing sensitivity exists between
830 the retiring WFI/WFE instructions and the newly issued subsequent
831 instructions. This sensitivity can result in a CPU hang scenario.
833 The software must insert either a Data Synchronization Barrier (DSB)
834 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
837 config ARM_ERRATA_326103
838 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
841 Executing a SWP instruction to read-only memory does not set bit 11
842 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
843 treat the access as a read, preventing a COW from occurring and
844 causing the faulting task to livelock.
846 config ARM_ERRATA_411920
847 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
848 depends on CPU_V6 || CPU_V6K
850 Invalidation of the Instruction Cache operation can
851 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
852 It does not affect the MPCore. This option enables the ARM Ltd.
853 recommended workaround.
855 config ARM_ERRATA_430973
856 bool "ARM errata: Stale prediction on replaced interworking branch"
859 This option enables the workaround for the 430973 Cortex-A8
860 r1p* erratum. If a code sequence containing an ARM/Thumb
861 interworking branch is replaced with another code sequence at the
862 same virtual address, whether due to self-modifying code or virtual
863 to physical address re-mapping, Cortex-A8 does not recover from the
864 stale interworking branch prediction. This results in Cortex-A8
865 executing the new code sequence in the incorrect ARM or Thumb state.
866 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
867 and also flushes the branch target cache at every context switch.
868 Note that setting specific bits in the ACTLR register may not be
869 available in non-secure mode.
871 config ARM_ERRATA_458693
872 bool "ARM errata: Processor deadlock when a false hazard is created"
874 depends on !ARCH_MULTIPLATFORM
876 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
877 erratum. For very specific sequences of memory operations, it is
878 possible for a hazard condition intended for a cache line to instead
879 be incorrectly associated with a different cache line. This false
880 hazard might then cause a processor deadlock. The workaround enables
881 the L1 caching of the NEON accesses and disables the PLD instruction
882 in the ACTLR register. Note that setting specific bits in the ACTLR
883 register may not be available in non-secure mode.
885 config ARM_ERRATA_460075
886 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
888 depends on !ARCH_MULTIPLATFORM
890 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
891 erratum. Any asynchronous access to the L2 cache may encounter a
892 situation in which recent store transactions to the L2 cache are lost
893 and overwritten with stale memory contents from external memory. The
894 workaround disables the write-allocate mode for the L2 cache via the
895 ACTLR register. Note that setting specific bits in the ACTLR register
896 may not be available in non-secure mode.
898 config ARM_ERRATA_742230
899 bool "ARM errata: DMB operation may be faulty"
900 depends on CPU_V7 && SMP
901 depends on !ARCH_MULTIPLATFORM
903 This option enables the workaround for the 742230 Cortex-A9
904 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
905 between two write operations may not ensure the correct visibility
906 ordering of the two writes. This workaround sets a specific bit in
907 the diagnostic register of the Cortex-A9 which causes the DMB
908 instruction to behave as a DSB, ensuring the correct behaviour of
911 config ARM_ERRATA_742231
912 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
913 depends on CPU_V7 && SMP
914 depends on !ARCH_MULTIPLATFORM
916 This option enables the workaround for the 742231 Cortex-A9
917 (r2p0..r2p2) erratum. Under certain conditions, specific to the
918 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
919 accessing some data located in the same cache line, may get corrupted
920 data due to bad handling of the address hazard when the line gets
921 replaced from one of the CPUs at the same time as another CPU is
922 accessing it. This workaround sets specific bits in the diagnostic
923 register of the Cortex-A9 which reduces the linefill issuing
924 capabilities of the processor.
926 config ARM_ERRATA_643719
927 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
928 depends on CPU_V7 && SMP
931 This option enables the workaround for the 643719 Cortex-A9 (prior to
932 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
933 register returns zero when it should return one. The workaround
934 corrects this value, ensuring cache maintenance operations which use
935 it behave as intended and avoiding data corruption.
937 config ARM_ERRATA_720789
938 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
941 This option enables the workaround for the 720789 Cortex-A9 (prior to
942 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
943 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
944 As a consequence of this erratum, some TLB entries which should be
945 invalidated are not, resulting in an incoherency in the system page
946 tables. The workaround changes the TLB flushing routines to invalidate
947 entries regardless of the ASID.
949 config ARM_ERRATA_743622
950 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
952 depends on !ARCH_MULTIPLATFORM
954 This option enables the workaround for the 743622 Cortex-A9
955 (r2p*) erratum. Under very rare conditions, a faulty
956 optimisation in the Cortex-A9 Store Buffer may lead to data
957 corruption. This workaround sets a specific bit in the diagnostic
958 register of the Cortex-A9 which disables the Store Buffer
959 optimisation, preventing the defect from occurring. This has no
960 visible impact on the overall performance or power consumption of the
963 config ARM_ERRATA_751472
964 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
966 depends on !ARCH_MULTIPLATFORM
968 This option enables the workaround for the 751472 Cortex-A9 (prior
969 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
970 completion of a following broadcasted operation if the second
971 operation is received by a CPU before the ICIALLUIS has completed,
972 potentially leading to corrupted entries in the cache or TLB.
974 config ARM_ERRATA_754322
975 bool "ARM errata: possible faulty MMU translations following an ASID switch"
978 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
979 r3p*) erratum. A speculative memory access may cause a page table walk
980 which starts prior to an ASID switch but completes afterwards. This
981 can populate the micro-TLB with a stale entry which may be hit with
982 the new ASID. This workaround places two dsb instructions in the mm
983 switching code so that no page table walks can cross the ASID switch.
985 config ARM_ERRATA_754327
986 bool "ARM errata: no automatic Store Buffer drain"
987 depends on CPU_V7 && SMP
989 This option enables the workaround for the 754327 Cortex-A9 (prior to
990 r2p0) erratum. The Store Buffer does not have any automatic draining
991 mechanism and therefore a livelock may occur if an external agent
992 continuously polls a memory location waiting to observe an update.
993 This workaround defines cpu_relax() as smp_mb(), preventing correctly
994 written polling loops from denying visibility of updates to memory.
996 config ARM_ERRATA_364296
997 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1000 This options enables the workaround for the 364296 ARM1136
1001 r0p2 erratum (possible cache data corruption with
1002 hit-under-miss enabled). It sets the undocumented bit 31 in
1003 the auxiliary control register and the FI bit in the control
1004 register, thus disabling hit-under-miss without putting the
1005 processor into full low interrupt latency mode. ARM11MPCore
1008 config ARM_ERRATA_764369
1009 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1010 depends on CPU_V7 && SMP
1012 This option enables the workaround for erratum 764369
1013 affecting Cortex-A9 MPCore with two or more processors (all
1014 current revisions). Under certain timing circumstances, a data
1015 cache line maintenance operation by MVA targeting an Inner
1016 Shareable memory region may fail to proceed up to either the
1017 Point of Coherency or to the Point of Unification of the
1018 system. This workaround adds a DSB instruction before the
1019 relevant cache maintenance functions and sets a specific bit
1020 in the diagnostic control register of the SCU.
1022 config ARM_ERRATA_775420
1023 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1026 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1027 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1028 operation aborts with MMU exception, it might cause the processor
1029 to deadlock. This workaround puts DSB before executing ISB if
1030 an abort may occur on cache maintenance.
1032 config ARM_ERRATA_798181
1033 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1034 depends on CPU_V7 && SMP
1036 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1037 adequately shooting down all use of the old entries. This
1038 option enables the Linux kernel workaround for this erratum
1039 which sends an IPI to the CPUs that are running the same ASID
1040 as the one being invalidated.
1042 config ARM_ERRATA_773022
1043 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1046 This option enables the workaround for the 773022 Cortex-A15
1047 (up to r0p4) erratum. In certain rare sequences of code, the
1048 loop buffer may deliver incorrect instructions. This
1049 workaround disables the loop buffer to avoid the erratum.
1051 config ARM_ERRATA_818325_852422
1052 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1055 This option enables the workaround for:
1056 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1057 instruction might deadlock. Fixed in r0p1.
1058 - Cortex-A12 852422: Execution of a sequence of instructions might
1059 lead to either a data corruption or a CPU deadlock. Not fixed in
1060 any Cortex-A12 cores yet.
1061 This workaround for all both errata involves setting bit[12] of the
1062 Feature Register. This bit disables an optimisation applied to a
1063 sequence of 2 instructions that use opposing condition codes.
1065 config ARM_ERRATA_821420
1066 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1069 This option enables the workaround for the 821420 Cortex-A12
1070 (all revs) erratum. In very rare timing conditions, a sequence
1071 of VMOV to Core registers instructions, for which the second
1072 one is in the shadow of a branch or abort, can lead to a
1073 deadlock when the VMOV instructions are issued out-of-order.
1075 config ARM_ERRATA_825619
1076 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1079 This option enables the workaround for the 825619 Cortex-A12
1080 (all revs) erratum. Within rare timing constraints, executing a
1081 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1082 and Device/Strongly-Ordered loads and stores might cause deadlock
1084 config ARM_ERRATA_857271
1085 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1088 This option enables the workaround for the 857271 Cortex-A12
1089 (all revs) erratum. Under very rare timing conditions, the CPU might
1090 hang. The workaround is expected to have a < 1% performance impact.
1092 config ARM_ERRATA_852421
1093 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1096 This option enables the workaround for the 852421 Cortex-A17
1097 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1098 execution of a DMB ST instruction might fail to properly order
1099 stores from GroupA and stores from GroupB.
1101 config ARM_ERRATA_852423
1102 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1105 This option enables the workaround for:
1106 - Cortex-A17 852423: Execution of a sequence of instructions might
1107 lead to either a data corruption or a CPU deadlock. Not fixed in
1108 any Cortex-A17 cores yet.
1109 This is identical to Cortex-A12 erratum 852422. It is a separate
1110 config option from the A12 erratum due to the way errata are checked
1113 config ARM_ERRATA_857272
1114 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1117 This option enables the workaround for the 857272 Cortex-A17 erratum.
1118 This erratum is not known to be fixed in any A17 revision.
1119 This is identical to Cortex-A12 erratum 857271. It is a separate
1120 config option from the A12 erratum due to the way errata are checked
1125 source "arch/arm/common/Kconfig"
1132 Find out whether you have ISA slots on your motherboard. ISA is the
1133 name of a bus system, i.e. the way the CPU talks to the other stuff
1134 inside your box. Other bus systems are PCI, EISA, MicroChannel
1135 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1136 newer boards don't support it. If you have ISA, say Y, otherwise N.
1138 # Select ISA DMA controller support
1143 # Select ISA DMA interface
1147 config PCI_NANOENGINE
1148 bool "BSE nanoEngine PCI support"
1149 depends on SA1100_NANOENGINE
1151 Enable PCI on the BSE nanoEngine board.
1153 config ARM_ERRATA_814220
1154 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1157 The v7 ARM states that all cache and branch predictor maintenance
1158 operations that do not specify an address execute, relative to
1159 each other, in program order.
1160 However, because of this erratum, an L2 set/way cache maintenance
1161 operation can overtake an L1 set/way cache maintenance operation.
1162 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1167 menu "Kernel Features"
1172 This option should be selected by machines which have an SMP-
1175 The only effect of this option is to make the SMP-related
1176 options available to the user for configuration.
1179 bool "Symmetric Multi-Processing"
1180 depends on CPU_V6K || CPU_V7
1181 depends on GENERIC_CLOCKEVENTS
1183 depends on MMU || ARM_MPU
1186 This enables support for systems with more than one CPU. If you have
1187 a system with only one CPU, say N. If you have a system with more
1188 than one CPU, say Y.
1190 If you say N here, the kernel will run on uni- and multiprocessor
1191 machines, but will use only one CPU of a multiprocessor machine. If
1192 you say Y here, the kernel will run on many, but not all,
1193 uniprocessor machines. On a uniprocessor machine, the kernel
1194 will run faster if you say N here.
1196 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1197 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1198 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1200 If you don't know what to do here, say N.
1203 bool "Allow booting SMP kernel on uniprocessor systems"
1204 depends on SMP && !XIP_KERNEL && MMU
1207 SMP kernels contain instructions which fail on non-SMP processors.
1208 Enabling this option allows the kernel to modify itself to make
1209 these instructions safe. Disabling it allows about 1K of space
1212 If you don't know what to do here, say Y.
1214 config ARM_CPU_TOPOLOGY
1215 bool "Support cpu topology definition"
1216 depends on SMP && CPU_V7
1219 Support ARM cpu topology definition. The MPIDR register defines
1220 affinity between processors which is then used to describe the cpu
1221 topology of an ARM System.
1224 bool "Multi-core scheduler support"
1225 depends on ARM_CPU_TOPOLOGY
1227 Multi-core scheduler support improves the CPU scheduler's decision
1228 making when dealing with multi-core CPU chips at a cost of slightly
1229 increased overhead in some places. If unsure say N here.
1232 bool "SMT scheduler support"
1233 depends on ARM_CPU_TOPOLOGY
1235 Improves the CPU scheduler's decision making when dealing with
1236 MultiThreading at a cost of slightly increased overhead in some
1237 places. If unsure say N here.
1242 This option enables support for the ARM snoop control unit
1244 config HAVE_ARM_ARCH_TIMER
1245 bool "Architected timer support"
1247 select ARM_ARCH_TIMER
1249 This option enables support for the ARM architected timer
1254 This options enables support for the ARM timer and watchdog unit
1257 bool "Multi-Cluster Power Management"
1258 depends on CPU_V7 && SMP
1260 This option provides the common power management infrastructure
1261 for (multi-)cluster based systems, such as big.LITTLE based
1264 config MCPM_QUAD_CLUSTER
1268 To avoid wasting resources unnecessarily, MCPM only supports up
1269 to 2 clusters by default.
1270 Platforms with 3 or 4 clusters that use MCPM must select this
1271 option to allow the additional clusters to be managed.
1274 bool "big.LITTLE support (Experimental)"
1275 depends on CPU_V7 && SMP
1278 This option enables support selections for the big.LITTLE
1279 system architecture.
1282 bool "big.LITTLE switcher support"
1283 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1286 The big.LITTLE "switcher" provides the core functionality to
1287 transparently handle transition between a cluster of A15's
1288 and a cluster of A7's in a big.LITTLE system.
1290 config BL_SWITCHER_DUMMY_IF
1291 tristate "Simple big.LITTLE switcher user interface"
1292 depends on BL_SWITCHER && DEBUG_KERNEL
1294 This is a simple and dummy char dev interface to control
1295 the big.LITTLE switcher core code. It is meant for
1296 debugging purposes only.
1299 prompt "Memory split"
1303 Select the desired split between kernel and user memory.
1305 If you are not absolutely sure what you are doing, leave this
1309 bool "3G/1G user/kernel split"
1310 config VMSPLIT_3G_OPT
1311 depends on !ARM_LPAE
1312 bool "3G/1G user/kernel split (for full 1G low memory)"
1314 bool "2G/2G user/kernel split"
1316 bool "1G/3G user/kernel split"
1321 default PHYS_OFFSET if !MMU
1322 default 0x40000000 if VMSPLIT_1G
1323 default 0x80000000 if VMSPLIT_2G
1324 default 0xB0000000 if VMSPLIT_3G_OPT
1328 int "Maximum number of CPUs (2-32)"
1334 bool "Support for hot-pluggable CPUs"
1336 select GENERIC_IRQ_MIGRATION
1338 Say Y here to experiment with turning CPUs off and on. CPUs
1339 can be controlled through /sys/devices/system/cpu.
1342 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1343 depends on HAVE_ARM_SMCCC
1346 Say Y here if you want Linux to communicate with system firmware
1347 implementing the PSCI specification for CPU-centric power
1348 management operations described in ARM document number ARM DEN
1349 0022A ("Power State Coordination Interface System Software on
1352 # The GPIO number here must be sorted by descending number. In case of
1353 # a multiplatform kernel, we just want the highest value required by the
1354 # selected platforms.
1357 default 2048 if ARCH_SOCFPGA
1358 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1359 ARCH_ZYNQ || ARCH_ASPEED
1360 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1361 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1362 default 416 if ARCH_SUNXI
1363 default 392 if ARCH_U8500
1364 default 352 if ARCH_VT8500
1365 default 288 if ARCH_ROCKCHIP
1366 default 264 if MACH_H4700
1369 Maximum number of GPIOs in the system.
1371 If unsure, leave the default value.
1375 default 200 if ARCH_EBSA110
1376 default 128 if SOC_AT91RM9200
1380 depends on HZ_FIXED = 0
1381 prompt "Timer frequency"
1405 default HZ_FIXED if HZ_FIXED != 0
1406 default 100 if HZ_100
1407 default 200 if HZ_200
1408 default 250 if HZ_250
1409 default 300 if HZ_300
1410 default 500 if HZ_500
1414 def_bool HIGH_RES_TIMERS
1416 config THUMB2_KERNEL
1417 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1418 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1419 default y if CPU_THUMBONLY
1422 By enabling this option, the kernel will be compiled in
1427 config ARM_PATCH_IDIV
1428 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1429 depends on CPU_32v7 && !XIP_KERNEL
1432 The ARM compiler inserts calls to __aeabi_idiv() and
1433 __aeabi_uidiv() when it needs to perform division on signed
1434 and unsigned integers. Some v7 CPUs have support for the sdiv
1435 and udiv instructions that can be used to implement those
1438 Enabling this option allows the kernel to modify itself to
1439 replace the first two instructions of these library functions
1440 with the sdiv or udiv plus "bx lr" instructions when the CPU
1441 it is running on supports them. Typically this will be faster
1442 and less power intensive than running the original library
1443 code to do integer division.
1446 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1447 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1448 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1450 This option allows for the kernel to be compiled using the latest
1451 ARM ABI (aka EABI). This is only useful if you are using a user
1452 space environment that is also compiled with EABI.
1454 Since there are major incompatibilities between the legacy ABI and
1455 EABI, especially with regard to structure member alignment, this
1456 option also changes the kernel syscall calling convention to
1457 disambiguate both ABIs and allow for backward compatibility support
1458 (selected with CONFIG_OABI_COMPAT).
1460 To use this you need GCC version 4.0.0 or later.
1463 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1464 depends on AEABI && !THUMB2_KERNEL
1466 This option preserves the old syscall interface along with the
1467 new (ARM EABI) one. It also provides a compatibility layer to
1468 intercept syscalls that have structure arguments which layout
1469 in memory differs between the legacy ABI and the new ARM EABI
1470 (only for non "thumb" binaries). This option adds a tiny
1471 overhead to all syscalls and produces a slightly larger kernel.
1473 The seccomp filter system will not be available when this is
1474 selected, since there is no way yet to sensibly distinguish
1475 between calling conventions during filtering.
1477 If you know you'll be using only pure EABI user space then you
1478 can say N here. If this option is not selected and you attempt
1479 to execute a legacy ABI binary then the result will be
1480 UNPREDICTABLE (in fact it can be predicted that it won't work
1481 at all). If in doubt say N.
1483 config ARCH_HAS_HOLES_MEMORYMODEL
1486 config ARCH_SELECT_MEMORY_MODEL
1489 config ARCH_FLATMEM_ENABLE
1492 config ARCH_SPARSEMEM_ENABLE
1494 select SPARSEMEM_STATIC if SPARSEMEM
1496 config HAVE_ARCH_PFN_VALID
1497 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1500 bool "High Memory Support"
1503 The address space of ARM processors is only 4 Gigabytes large
1504 and it has to accommodate user address space, kernel address
1505 space as well as some memory mapped IO. That means that, if you
1506 have a large amount of physical memory and/or IO, not all of the
1507 memory can be "permanently mapped" by the kernel. The physical
1508 memory that is not permanently mapped is called "high memory".
1510 Depending on the selected kernel/user memory split, minimum
1511 vmalloc space and actual amount of RAM, you may not need this
1512 option which should result in a slightly faster kernel.
1517 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1521 The VM uses one page of physical memory for each page table.
1522 For systems with a lot of processes, this can use a lot of
1523 precious low memory, eventually leading to low memory being
1524 consumed by page tables. Setting this option will allow
1525 user-space 2nd level page tables to reside in high memory.
1527 config CPU_SW_DOMAIN_PAN
1528 bool "Enable use of CPU domains to implement privileged no-access"
1529 depends on MMU && !ARM_LPAE
1532 Increase kernel security by ensuring that normal kernel accesses
1533 are unable to access userspace addresses. This can help prevent
1534 use-after-free bugs becoming an exploitable privilege escalation
1535 by ensuring that magic values (such as LIST_POISON) will always
1536 fault when dereferenced.
1538 CPUs with low-vector mappings use a best-efforts implementation.
1539 Their lower 1MB needs to remain accessible for the vectors, but
1540 the remainder of userspace will become appropriately inaccessible.
1542 config HW_PERF_EVENTS
1546 config SYS_SUPPORTS_HUGETLBFS
1550 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1554 config ARCH_WANT_GENERAL_HUGETLB
1557 config ARM_MODULE_PLTS
1558 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1562 Allocate PLTs when loading modules so that jumps and calls whose
1563 targets are too far away for their relative offsets to be encoded
1564 in the instructions themselves can be bounced via veneers in the
1565 module's PLT. This allows modules to be allocated in the generic
1566 vmalloc area after the dedicated module memory area has been
1567 exhausted. The modules will use slightly more memory, but after
1568 rounding up to page size, the actual memory footprint is usually
1571 Disabling this is usually safe for small single-platform
1572 configurations. If unsure, say y.
1574 config FORCE_MAX_ZONEORDER
1575 int "Maximum zone order"
1576 default "12" if SOC_AM33XX
1577 default "9" if SA1111 || ARCH_EFM32
1580 The kernel memory allocator divides physically contiguous memory
1581 blocks into "zones", where each zone is a power of two number of
1582 pages. This option selects the largest power of two that the kernel
1583 keeps in the memory allocator. If you need to allocate very large
1584 blocks of physically contiguous memory, then you may need to
1585 increase this value.
1587 This config option is actually maximum order plus one. For example,
1588 a value of 11 means that the largest free memory block is 2^10 pages.
1590 config ALIGNMENT_TRAP
1592 depends on CPU_CP15_MMU
1593 default y if !ARCH_EBSA110
1594 select HAVE_PROC_CPU if PROC_FS
1596 ARM processors cannot fetch/store information which is not
1597 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1598 address divisible by 4. On 32-bit ARM processors, these non-aligned
1599 fetch/store instructions will be emulated in software if you say
1600 here, which has a severe performance impact. This is necessary for
1601 correct operation of some network protocols. With an IP-only
1602 configuration it is safe to say N, otherwise say Y.
1604 config UACCESS_WITH_MEMCPY
1605 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1607 default y if CPU_FEROCEON
1609 Implement faster copy_to_user and clear_user methods for CPU
1610 cores where a 8-word STM instruction give significantly higher
1611 memory write throughput than a sequence of individual 32bit stores.
1613 A possible side effect is a slight increase in scheduling latency
1614 between threads sharing the same address space if they invoke
1615 such copy operations with large buffers.
1617 However, if the CPU data cache is using a write-allocate mode,
1618 this option is unlikely to provide any performance gain.
1622 prompt "Enable seccomp to safely compute untrusted bytecode"
1624 This kernel feature is useful for number crunching applications
1625 that may need to compute untrusted bytecode during their
1626 execution. By using pipes or other transports made available to
1627 the process as file descriptors supporting the read/write
1628 syscalls, it's possible to isolate those applications in
1629 their own address space using seccomp. Once seccomp is
1630 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1631 and the task is only allowed to execute a few safe syscalls
1632 defined by each seccomp mode.
1635 bool "Enable paravirtualization code"
1637 This changes the kernel so it can modify itself when it is run
1638 under a hypervisor, potentially improving performance significantly
1639 over full virtualization.
1641 config PARAVIRT_TIME_ACCOUNTING
1642 bool "Paravirtual steal time accounting"
1645 Select this option to enable fine granularity task steal time
1646 accounting. Time spent executing other tasks in parallel with
1647 the current vCPU is discounted from the vCPU power. To account for
1648 that, there can be a small performance impact.
1650 If in doubt, say N here.
1657 bool "Xen guest support on ARM"
1658 depends on ARM && AEABI && OF
1659 depends on CPU_V7 && !CPU_V6
1660 depends on !GENERIC_ATOMIC64
1662 select ARCH_DMA_ADDR_T_64BIT
1668 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1670 config STACKPROTECTOR_PER_TASK
1671 bool "Use a unique stack canary value for each task"
1672 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1673 select GCC_PLUGIN_ARM_SSP_PER_TASK
1676 Due to the fact that GCC uses an ordinary symbol reference from
1677 which to load the value of the stack canary, this value can only
1678 change at reboot time on SMP systems, and all tasks running in the
1679 kernel's address space are forced to use the same canary value for
1680 the entire duration that the system is up.
1682 Enable this option to switch to a different method that uses a
1683 different canary value for each task.
1690 bool "Flattened Device Tree support"
1694 Include support for flattened device tree machine descriptions.
1697 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1700 This is the traditional way of passing data to the kernel at boot
1701 time. If you are solely relying on the flattened device tree (or
1702 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1703 to remove ATAGS support from your kernel binary. If unsure,
1706 config DEPRECATED_PARAM_STRUCT
1707 bool "Provide old way to pass kernel parameters"
1710 This was deprecated in 2001 and announced to live on for 5 years.
1711 Some old boot loaders still use this way.
1713 # Compressed boot loader in ROM. Yes, we really want to ask about
1714 # TEXT and BSS so we preserve their values in the config files.
1715 config ZBOOT_ROM_TEXT
1716 hex "Compressed ROM boot loader base address"
1719 The physical address at which the ROM-able zImage is to be
1720 placed in the target. Platforms which normally make use of
1721 ROM-able zImage formats normally set this to a suitable
1722 value in their defconfig file.
1724 If ZBOOT_ROM is not enabled, this has no effect.
1726 config ZBOOT_ROM_BSS
1727 hex "Compressed ROM boot loader BSS address"
1730 The base address of an area of read/write memory in the target
1731 for the ROM-able zImage which must be available while the
1732 decompressor is running. It must be large enough to hold the
1733 entire decompressed kernel plus an additional 128 KiB.
1734 Platforms which normally make use of ROM-able zImage formats
1735 normally set this to a suitable value in their defconfig file.
1737 If ZBOOT_ROM is not enabled, this has no effect.
1740 bool "Compressed boot loader in ROM/flash"
1741 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1742 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1744 Say Y here if you intend to execute your compressed kernel image
1745 (zImage) directly from ROM or flash. If unsure, say N.
1747 config ARM_APPENDED_DTB
1748 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1751 With this option, the boot code will look for a device tree binary
1752 (DTB) appended to zImage
1753 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1755 This is meant as a backward compatibility convenience for those
1756 systems with a bootloader that can't be upgraded to accommodate
1757 the documented boot protocol using a device tree.
1759 Beware that there is very little in terms of protection against
1760 this option being confused by leftover garbage in memory that might
1761 look like a DTB header after a reboot if no actual DTB is appended
1762 to zImage. Do not leave this option active in a production kernel
1763 if you don't intend to always append a DTB. Proper passing of the
1764 location into r2 of a bootloader provided DTB is always preferable
1767 config ARM_ATAG_DTB_COMPAT
1768 bool "Supplement the appended DTB with traditional ATAG information"
1769 depends on ARM_APPENDED_DTB
1771 Some old bootloaders can't be updated to a DTB capable one, yet
1772 they provide ATAGs with memory configuration, the ramdisk address,
1773 the kernel cmdline string, etc. Such information is dynamically
1774 provided by the bootloader and can't always be stored in a static
1775 DTB. To allow a device tree enabled kernel to be used with such
1776 bootloaders, this option allows zImage to extract the information
1777 from the ATAG list and store it at run time into the appended DTB.
1780 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1781 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1783 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1784 bool "Use bootloader kernel arguments if available"
1786 Uses the command-line options passed by the boot loader instead of
1787 the device tree bootargs property. If the boot loader doesn't provide
1788 any, the device tree bootargs property will be used.
1790 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1791 bool "Extend with bootloader kernel arguments"
1793 The command-line arguments provided by the boot loader will be
1794 appended to the the device tree bootargs property.
1799 string "Default kernel command string"
1802 On some architectures (EBSA110 and CATS), there is currently no way
1803 for the boot loader to pass arguments to the kernel. For these
1804 architectures, you should supply some command-line options at build
1805 time by entering them here. As a minimum, you should specify the
1806 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1809 prompt "Kernel command line type" if CMDLINE != ""
1810 default CMDLINE_FROM_BOOTLOADER
1813 config CMDLINE_FROM_BOOTLOADER
1814 bool "Use bootloader kernel arguments if available"
1816 Uses the command-line options passed by the boot loader. If
1817 the boot loader doesn't provide any, the default kernel command
1818 string provided in CMDLINE will be used.
1820 config CMDLINE_EXTEND
1821 bool "Extend bootloader kernel arguments"
1823 The command-line arguments provided by the boot loader will be
1824 appended to the default kernel command string.
1826 config CMDLINE_FORCE
1827 bool "Always use the default kernel command string"
1829 Always use the default kernel command string, even if the boot
1830 loader passes other arguments to the kernel.
1831 This is useful if you cannot or don't want to change the
1832 command-line options your boot loader passes to the kernel.
1836 bool "Kernel Execute-In-Place from ROM"
1837 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1839 Execute-In-Place allows the kernel to run from non-volatile storage
1840 directly addressable by the CPU, such as NOR flash. This saves RAM
1841 space since the text section of the kernel is not loaded from flash
1842 to RAM. Read-write sections, such as the data section and stack,
1843 are still copied to RAM. The XIP kernel is not compressed since
1844 it has to run directly from flash, so it will take more space to
1845 store it. The flash address used to link the kernel object files,
1846 and for storing it, is configuration dependent. Therefore, if you
1847 say Y here, you must know the proper physical address where to
1848 store the kernel image depending on your own flash memory usage.
1850 Also note that the make target becomes "make xipImage" rather than
1851 "make zImage" or "make Image". The final kernel binary to put in
1852 ROM memory will be arch/arm/boot/xipImage.
1856 config XIP_PHYS_ADDR
1857 hex "XIP Kernel Physical Location"
1858 depends on XIP_KERNEL
1859 default "0x00080000"
1861 This is the physical address in your flash memory the kernel will
1862 be linked for and stored to. This address is dependent on your
1865 config XIP_DEFLATED_DATA
1866 bool "Store kernel .data section compressed in ROM"
1867 depends on XIP_KERNEL
1870 Before the kernel is actually executed, its .data section has to be
1871 copied to RAM from ROM. This option allows for storing that data
1872 in compressed form and decompressed to RAM rather than merely being
1873 copied, saving some precious ROM space. A possible drawback is a
1874 slightly longer boot delay.
1877 bool "Kexec system call (EXPERIMENTAL)"
1878 depends on (!SMP || PM_SLEEP_SMP)
1882 kexec is a system call that implements the ability to shutdown your
1883 current kernel, and to start another kernel. It is like a reboot
1884 but it is independent of the system firmware. And like a reboot
1885 you can start any kernel with it, not just Linux.
1887 It is an ongoing process to be certain the hardware in a machine
1888 is properly shutdown, so do not be surprised if this code does not
1889 initially work for you.
1892 bool "Export atags in procfs"
1893 depends on ATAGS && KEXEC
1896 Should the atags used to boot the kernel be exported in an "atags"
1897 file in procfs. Useful with kexec.
1900 bool "Build kdump crash kernel (EXPERIMENTAL)"
1902 Generate crash dump after being started by kexec. This should
1903 be normally only set in special crash dump kernels which are
1904 loaded in the main kernel with kexec-tools into a specially
1905 reserved region and then later executed after a crash by
1906 kdump/kexec. The crash dump kernel must be compiled to a
1907 memory address not used by the main kernel
1909 For more details see Documentation/admin-guide/kdump/kdump.rst
1911 config AUTO_ZRELADDR
1912 bool "Auto calculation of the decompressed kernel image address"
1914 ZRELADDR is the physical address where the decompressed kernel
1915 image will be placed. If AUTO_ZRELADDR is selected, the address
1916 will be determined at run-time by masking the current IP with
1917 0xf8000000. This assumes the zImage being placed in the first 128MB
1918 from start of memory.
1924 bool "UEFI runtime support"
1925 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1927 select EFI_PARAMS_FROM_FDT
1929 select EFI_GENERIC_STUB
1930 select EFI_RUNTIME_WRAPPERS
1932 This option provides support for runtime services provided
1933 by UEFI firmware (such as non-volatile variables, realtime
1934 clock, and platform reset). A UEFI stub is also provided to
1935 allow the kernel to be booted as an EFI application. This
1936 is only useful for kernels that may run on systems that have
1940 bool "Enable support for SMBIOS (DMI) tables"
1944 This enables SMBIOS/DMI feature for systems.
1946 This option is only useful on systems that have UEFI firmware.
1947 However, even with this option, the resultant kernel should
1948 continue to boot on existing non-UEFI platforms.
1950 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1951 i.e., the the practice of identifying the platform via DMI to
1952 decide whether certain workarounds for buggy hardware and/or
1953 firmware need to be enabled. This would require the DMI subsystem
1954 to be enabled much earlier than we do on ARM, which is non-trivial.
1958 menu "CPU Power Management"
1960 source "drivers/cpufreq/Kconfig"
1962 source "drivers/cpuidle/Kconfig"
1966 menu "Floating point emulation"
1968 comment "At least one emulation must be selected"
1971 bool "NWFPE math emulation"
1972 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1974 Say Y to include the NWFPE floating point emulator in the kernel.
1975 This is necessary to run most binaries. Linux does not currently
1976 support floating point hardware so you need to say Y here even if
1977 your machine has an FPA or floating point co-processor podule.
1979 You may say N here if you are going to load the Acorn FPEmulator
1980 early in the bootup.
1983 bool "Support extended precision"
1984 depends on FPE_NWFPE
1986 Say Y to include 80-bit support in the kernel floating-point
1987 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1988 Note that gcc does not generate 80-bit operations by default,
1989 so in most cases this option only enlarges the size of the
1990 floating point emulator without any good reason.
1992 You almost surely want to say N here.
1995 bool "FastFPE math emulation (EXPERIMENTAL)"
1996 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1998 Say Y here to include the FAST floating point emulator in the kernel.
1999 This is an experimental much faster emulator which now also has full
2000 precision for the mantissa. It does not support any exceptions.
2001 It is very simple, and approximately 3-6 times faster than NWFPE.
2003 It should be sufficient for most programs. It may be not suitable
2004 for scientific calculations, but you have to check this for yourself.
2005 If you do not feel you need a faster FP emulation you should better
2009 bool "VFP-format floating point maths"
2010 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2012 Say Y to include VFP support code in the kernel. This is needed
2013 if your hardware includes a VFP unit.
2015 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2016 release notes and additional status information.
2018 Say N if your target does not have VFP hardware.
2026 bool "Advanced SIMD (NEON) Extension support"
2027 depends on VFPv3 && CPU_V7
2029 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2032 config KERNEL_MODE_NEON
2033 bool "Support for NEON in kernel mode"
2034 depends on NEON && AEABI
2036 Say Y to include support for NEON in kernel mode.
2040 menu "Power management options"
2042 source "kernel/power/Kconfig"
2044 config ARCH_SUSPEND_POSSIBLE
2045 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2046 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2049 config ARM_CPU_SUSPEND
2050 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2051 depends on ARCH_SUSPEND_POSSIBLE
2053 config ARCH_HIBERNATION_POSSIBLE
2056 default y if ARCH_SUSPEND_POSSIBLE
2060 source "drivers/firmware/Kconfig"
2063 source "arch/arm/crypto/Kconfig"
2066 source "arch/arm/Kconfig.assembler"