1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_USE_BUILTIN_BSWAP
35 select ARCH_USE_CMPXCHG_LOCKREF
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
39 select BUILDTIME_TABLE_SORT if MMU
40 select CLONE_BACKWARDS
41 select CPU_PM if SUSPEND || CPU_IDLE
42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
43 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_IRQ_IPI if SMP
53 select GENERIC_CPU_AUTOPROBE
54 select GENERIC_EARLY_IOREMAP
55 select GENERIC_IDLE_POLL_SETUP
56 select GENERIC_IRQ_PROBE
57 select GENERIC_IRQ_SHOW
58 select GENERIC_IRQ_SHOW_LEVEL
59 select GENERIC_PCI_IOMAP
60 select GENERIC_SCHED_CLOCK
61 select GENERIC_SMP_IDLE_THREAD
62 select GENERIC_STRNCPY_FROM_USER
63 select GENERIC_STRNLEN_USER
64 select HANDLE_DOMAIN_IRQ
65 select HARDIRQS_SW_RESEND
66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
70 select HAVE_ARCH_MMAP_RND_BITS if MMU
71 select HAVE_ARCH_SECCOMP
72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
74 select HAVE_ARCH_TRACEHOOK
75 select HAVE_ARM_SMCCC if CPU_V7
76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
77 select HAVE_CONTEXT_TRACKING
78 select HAVE_C_RECORDMCOUNT
79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
80 select HAVE_DMA_CONTIGUOUS if MMU
81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
84 select HAVE_EXIT_THREAD
85 select HAVE_FAST_GUP if ARM_LPAE
86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
89 select HAVE_GCC_PLUGINS
90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
91 select HAVE_IDE if PCI || ISA || PCMCIA
92 select HAVE_IRQ_TIME_ACCOUNTING
93 select HAVE_KERNEL_GZIP
94 select HAVE_KERNEL_LZ4
95 select HAVE_KERNEL_LZMA
96 select HAVE_KERNEL_LZO
98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
99 select HAVE_KRETPROBES if HAVE_KPROBES
100 select HAVE_MOD_ARCH_SPECIFIC
102 select HAVE_OPROFILE if HAVE_PERF_EVENTS
103 select HAVE_OPTPROBES if !THUMB2_KERNEL
104 select HAVE_PERF_EVENTS
105 select HAVE_PERF_REGS
106 select HAVE_PERF_USER_STACK_DUMP
107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
108 select HAVE_REGS_AND_STACK_ACCESS_API
110 select HAVE_STACKPROTECTOR
111 select HAVE_SYSCALL_TRACEPOINTS
113 select HAVE_VIRT_CPU_ACCOUNTING_GEN
114 select IRQ_FORCED_THREADING
115 select MODULES_USE_ELF_REL
116 select NEED_DMA_MAP_STATE
117 select OF_EARLY_FLATTREE if OF
119 select OLD_SIGSUSPEND3
120 select PCI_SYSCALL if PCI
121 select PERF_USE_VMALLOC
124 select SYS_SUPPORTS_APM_EMULATION
125 # Above selects are sorted alphabetically; please add new ones
126 # according to that. Thanks.
128 The ARM series is a line of low-power-consumption RISC chip designs
129 licensed by ARM Ltd and targeted at embedded applications and
130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
131 manufactured, but legacy ARM-based PC hardware remains popular in
132 Europe. There is an ARM Linux project with a web page at
133 <http://www.arm.linux.org.uk/>.
135 config ARM_HAS_SG_CHAIN
138 config ARM_DMA_USE_IOMMU
140 select ARM_HAS_SG_CHAIN
141 select NEED_SG_DMA_LENGTH
145 config ARM_DMA_IOMMU_ALIGNMENT
146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
150 DMA mapping framework by default aligns all buffers to the smallest
151 PAGE_SIZE order which is greater than or equal to the requested buffer
152 size. This works well for buffers up to a few hundreds kilobytes, but
153 for larger buffers it just a waste of address space. Drivers which has
154 relatively small addressing window (like 64Mib) might run out of
155 virtual space with just a few allocations.
157 With this parameter you can specify the maximum PAGE_SIZE order for
158 DMA IOMMU buffers. Larger buffers will be aligned only to this
159 specified order. The order is expressed as a power of two multiplied
164 config SYS_SUPPORTS_APM_EMULATION
169 select GENERIC_ALLOCATOR
180 config STACKTRACE_SUPPORT
184 config LOCKDEP_SUPPORT
188 config TRACE_IRQFLAGS_SUPPORT
192 config ARCH_HAS_ILOG2_U32
195 config ARCH_HAS_ILOG2_U64
198 config ARCH_HAS_BANDGAP
201 config FIX_EARLYCON_MEM
204 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
212 config ARCH_MAY_HAVE_PC_FDC
218 config ARCH_SUPPORTS_UPROBES
221 config ARCH_HAS_DMA_SET_COHERENT_MASK
224 config GENERIC_ISA_DMA
230 config NEED_RET_TO_USER
236 config ARM_PATCH_PHYS_VIRT
237 bool "Patch physical to virtual translations at runtime" if EMBEDDED
239 depends on !XIP_KERNEL && MMU
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT
269 default DRAM_BASE if !MMU
270 default 0x00000000 if ARCH_EBSA110 || \
274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
275 default 0x20000000 if ARCH_S5PV210
276 default 0xc0000000 if ARCH_SA1100
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 config PGTABLE_LEVELS
287 default 3 if ARM_LPAE
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
299 config ARCH_MMAP_RND_BITS_MIN
302 config ARCH_MMAP_RND_BITS_MAX
303 default 14 if PAGE_OFFSET=0x40000000
304 default 15 if PAGE_OFFSET=0x80000000
308 # The "ARM system type" choice list is ordered alphabetically by option
309 # text. Please add new entries in the option alphabetic order.
312 prompt "ARM system type"
313 default ARM_SINGLE_ARMV7M if !MMU
314 default ARCH_MULTIPLATFORM if MMU
316 config ARCH_MULTIPLATFORM
317 bool "Allow multiple platforms to be selected"
319 select ARCH_FLATMEM_ENABLE
320 select ARCH_SPARSEMEM_ENABLE
321 select ARCH_SELECT_MEMORY_MODEL
322 select ARM_HAS_SG_CHAIN
323 select ARM_PATCH_PHYS_VIRT
327 select GENERIC_CLOCKEVENTS
328 select GENERIC_IRQ_MULTI_HANDLER
330 select PCI_DOMAINS_GENERIC if PCI
334 config ARM_SINGLE_ARMV7M
335 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
342 select GENERIC_CLOCKEVENTS
349 select ARCH_USES_GETTIMEOFFSET
352 select NEED_MACH_IO_H
353 select NEED_MACH_MEMORY_H
356 This is an evaluation board for the StrongARM processor available
357 from Digital. It has limited hardware on-board, including an
358 Ethernet interface, two PCMCIA sockets, two serial ports and a
363 select ARCH_SPARSEMEM_ENABLE
365 imply ARM_PATCH_PHYS_VIRT
371 select GENERIC_CLOCKEVENTS
373 select HAVE_LEGACY_CLK
375 This enables support for the Cirrus EP93xx series of CPUs.
377 config ARCH_FOOTBRIDGE
381 select GENERIC_CLOCKEVENTS
383 select NEED_MACH_IO_H if !MMU
384 select NEED_MACH_MEMORY_H
386 Support for systems based on the DC21285 companion chip
387 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
395 select NEED_RET_TO_USER
399 Support for Intel's 80219 and IOP32X (XScale) family of
405 select ARCH_HAS_DMA_SET_COHERENT_MASK
406 select ARCH_SUPPORTS_BIG_ENDIAN
408 select DMABOUNCE if PCI
409 select GENERIC_CLOCKEVENTS
410 select GENERIC_IRQ_MULTI_HANDLER
416 select NEED_MACH_IO_H
417 select USB_EHCI_BIG_ENDIAN_DESC
418 select USB_EHCI_BIG_ENDIAN_MMIO
420 Support for Intel's IXP4XX (XScale) family of processors.
425 select GENERIC_CLOCKEVENTS
426 select GENERIC_IRQ_MULTI_HANDLER
432 select PLAT_ORION_LEGACY
434 select PM_GENERIC_DOMAINS if PM
436 Support for the Marvell Dove SoC 88AP510
439 bool "PXA2xx/PXA3xx-based"
442 select ARM_CPU_SUSPEND if PM
448 select CPU_XSCALE if !CPU_XSC3
449 select GENERIC_CLOCKEVENTS
450 select GENERIC_IRQ_MULTI_HANDLER
458 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
464 select ARCH_MAY_HAVE_PC_FDC
465 select ARCH_SPARSEMEM_ENABLE
466 select ARM_HAS_SG_CHAIN
470 select HAVE_PATA_PLATFORM
472 select NEED_MACH_IO_H
473 select NEED_MACH_MEMORY_H
476 On the Acorn Risc-PC, Linux can support the internal IDE disk and
477 CD-ROM interface, serial and parallel port, and the floppy drive.
482 select ARCH_SPARSEMEM_ENABLE
485 select TIMER_OF if OF
489 select GENERIC_CLOCKEVENTS
490 select GENERIC_IRQ_MULTI_HANDLER
495 select NEED_MACH_MEMORY_H
498 Support for StrongARM 11x0 based boards.
501 bool "Samsung S3C24XX SoCs"
503 select CLKSRC_SAMSUNG_PWM
504 select GENERIC_CLOCKEVENTS
507 select GENERIC_IRQ_MULTI_HANDLER
508 select HAVE_S3C2410_I2C if I2C
509 select HAVE_S3C2410_WATCHDOG if WATCHDOG
510 select HAVE_S3C_RTC if RTC_CLASS
511 select NEED_MACH_IO_H
515 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
516 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
517 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
518 Samsung SMDK2410 development board (and derivatives).
523 select ARCH_HAS_HOLES_MEMORYMODEL
527 select GENERIC_CLOCKEVENTS
528 select GENERIC_IRQ_CHIP
529 select GENERIC_IRQ_MULTI_HANDLER
532 select HAVE_LEGACY_CLK
534 select NEED_MACH_IO_H if PCCARD
535 select NEED_MACH_MEMORY_H
538 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
542 menu "Multiple platform selection"
543 depends on ARCH_MULTIPLATFORM
545 comment "CPU Core family selection"
548 bool "ARMv4 based platforms (FA526)"
549 depends on !ARCH_MULTI_V6_V7
550 select ARCH_MULTI_V4_V5
553 config ARCH_MULTI_V4T
554 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
555 depends on !ARCH_MULTI_V6_V7
556 select ARCH_MULTI_V4_V5
557 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
558 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
559 CPU_ARM925T || CPU_ARM940T)
562 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
563 depends on !ARCH_MULTI_V6_V7
564 select ARCH_MULTI_V4_V5
565 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
566 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
567 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
569 config ARCH_MULTI_V4_V5
573 bool "ARMv6 based platforms (ARM11)"
574 select ARCH_MULTI_V6_V7
578 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
580 select ARCH_MULTI_V6_V7
584 config ARCH_MULTI_V6_V7
586 select MIGHT_HAVE_CACHE_L2X0
588 config ARCH_MULTI_CPU_AUTO
589 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
595 bool "Dummy Virtual Machine"
596 depends on ARCH_MULTI_V7
599 select ARM_GIC_V2M if PCI
601 select ARM_GIC_V3_ITS if PCI
603 select HAVE_ARM_ARCH_TIMER
604 select ARCH_SUPPORTS_BIG_ENDIAN
607 # This is sorted alphabetically by mach-* pathname. However, plat-*
608 # Kconfigs may be included either alphabetically (according to the
609 # plat- suffix) or along side the corresponding mach-* source.
611 source "arch/arm/mach-actions/Kconfig"
613 source "arch/arm/mach-alpine/Kconfig"
615 source "arch/arm/mach-artpec/Kconfig"
617 source "arch/arm/mach-asm9260/Kconfig"
619 source "arch/arm/mach-aspeed/Kconfig"
621 source "arch/arm/mach-at91/Kconfig"
623 source "arch/arm/mach-axxia/Kconfig"
625 source "arch/arm/mach-bcm/Kconfig"
627 source "arch/arm/mach-berlin/Kconfig"
629 source "arch/arm/mach-clps711x/Kconfig"
631 source "arch/arm/mach-cns3xxx/Kconfig"
633 source "arch/arm/mach-davinci/Kconfig"
635 source "arch/arm/mach-digicolor/Kconfig"
637 source "arch/arm/mach-dove/Kconfig"
639 source "arch/arm/mach-ep93xx/Kconfig"
641 source "arch/arm/mach-exynos/Kconfig"
642 source "arch/arm/plat-samsung/Kconfig"
644 source "arch/arm/mach-footbridge/Kconfig"
646 source "arch/arm/mach-gemini/Kconfig"
648 source "arch/arm/mach-highbank/Kconfig"
650 source "arch/arm/mach-hisi/Kconfig"
652 source "arch/arm/mach-imx/Kconfig"
654 source "arch/arm/mach-integrator/Kconfig"
656 source "arch/arm/mach-iop32x/Kconfig"
658 source "arch/arm/mach-ixp4xx/Kconfig"
660 source "arch/arm/mach-keystone/Kconfig"
662 source "arch/arm/mach-lpc32xx/Kconfig"
664 source "arch/arm/mach-mediatek/Kconfig"
666 source "arch/arm/mach-meson/Kconfig"
668 source "arch/arm/mach-milbeaut/Kconfig"
670 source "arch/arm/mach-mmp/Kconfig"
672 source "arch/arm/mach-moxart/Kconfig"
674 source "arch/arm/mach-mstar/Kconfig"
676 source "arch/arm/mach-mv78xx0/Kconfig"
678 source "arch/arm/mach-mvebu/Kconfig"
680 source "arch/arm/mach-mxs/Kconfig"
682 source "arch/arm/mach-nomadik/Kconfig"
684 source "arch/arm/mach-npcm/Kconfig"
686 source "arch/arm/mach-nspire/Kconfig"
688 source "arch/arm/plat-omap/Kconfig"
690 source "arch/arm/mach-omap1/Kconfig"
692 source "arch/arm/mach-omap2/Kconfig"
694 source "arch/arm/mach-orion5x/Kconfig"
696 source "arch/arm/mach-oxnas/Kconfig"
698 source "arch/arm/mach-picoxcell/Kconfig"
700 source "arch/arm/mach-prima2/Kconfig"
702 source "arch/arm/mach-pxa/Kconfig"
703 source "arch/arm/plat-pxa/Kconfig"
705 source "arch/arm/mach-qcom/Kconfig"
707 source "arch/arm/mach-rda/Kconfig"
709 source "arch/arm/mach-realtek/Kconfig"
711 source "arch/arm/mach-realview/Kconfig"
713 source "arch/arm/mach-rockchip/Kconfig"
715 source "arch/arm/mach-s3c24xx/Kconfig"
717 source "arch/arm/mach-s3c64xx/Kconfig"
719 source "arch/arm/mach-s5pv210/Kconfig"
721 source "arch/arm/mach-sa1100/Kconfig"
723 source "arch/arm/mach-shmobile/Kconfig"
725 source "arch/arm/mach-socfpga/Kconfig"
727 source "arch/arm/mach-spear/Kconfig"
729 source "arch/arm/mach-sti/Kconfig"
731 source "arch/arm/mach-stm32/Kconfig"
733 source "arch/arm/mach-sunxi/Kconfig"
735 source "arch/arm/mach-tango/Kconfig"
737 source "arch/arm/mach-tegra/Kconfig"
739 source "arch/arm/mach-u300/Kconfig"
741 source "arch/arm/mach-uniphier/Kconfig"
743 source "arch/arm/mach-ux500/Kconfig"
745 source "arch/arm/mach-versatile/Kconfig"
747 source "arch/arm/mach-vexpress/Kconfig"
749 source "arch/arm/mach-vt8500/Kconfig"
751 source "arch/arm/mach-zx/Kconfig"
753 source "arch/arm/mach-zynq/Kconfig"
755 # ARMv7-M architecture
757 bool "Energy Micro efm32"
758 depends on ARM_SINGLE_ARMV7M
761 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
765 bool "NXP LPC18xx/LPC43xx"
766 depends on ARM_SINGLE_ARMV7M
767 select ARCH_HAS_RESET_CONTROLLER
769 select CLKSRC_LPC32XX
772 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
773 high performance microcontrollers.
776 bool "ARM MPS2 platform"
777 depends on ARM_SINGLE_ARMV7M
781 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
782 with a range of available cores like Cortex-M3/M4/M7.
784 Please, note that depends which Application Note is used memory map
785 for the platform may vary, so adjustment of RAM base might be needed.
787 # Definitions to make life easier
793 select GENERIC_CLOCKEVENTS
799 select GENERIC_IRQ_CHIP
802 config PLAT_ORION_LEGACY
809 config PLAT_VERSATILE
812 source "arch/arm/mm/Kconfig"
815 bool "Enable iWMMXt support"
816 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
817 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
819 Enable support for iWMMXt context switching at run time if
820 running on a CPU that supports it.
823 source "arch/arm/Kconfig-nommu"
826 config PJ4B_ERRATA_4742
827 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
828 depends on CPU_PJ4B && MACH_ARMADA_370
831 When coming out of either a Wait for Interrupt (WFI) or a Wait for
832 Event (WFE) IDLE states, a specific timing sensitivity exists between
833 the retiring WFI/WFE instructions and the newly issued subsequent
834 instructions. This sensitivity can result in a CPU hang scenario.
836 The software must insert either a Data Synchronization Barrier (DSB)
837 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
840 config ARM_ERRATA_326103
841 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
844 Executing a SWP instruction to read-only memory does not set bit 11
845 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
846 treat the access as a read, preventing a COW from occurring and
847 causing the faulting task to livelock.
849 config ARM_ERRATA_411920
850 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
851 depends on CPU_V6 || CPU_V6K
853 Invalidation of the Instruction Cache operation can
854 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
855 It does not affect the MPCore. This option enables the ARM Ltd.
856 recommended workaround.
858 config ARM_ERRATA_430973
859 bool "ARM errata: Stale prediction on replaced interworking branch"
862 This option enables the workaround for the 430973 Cortex-A8
863 r1p* erratum. If a code sequence containing an ARM/Thumb
864 interworking branch is replaced with another code sequence at the
865 same virtual address, whether due to self-modifying code or virtual
866 to physical address re-mapping, Cortex-A8 does not recover from the
867 stale interworking branch prediction. This results in Cortex-A8
868 executing the new code sequence in the incorrect ARM or Thumb state.
869 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
870 and also flushes the branch target cache at every context switch.
871 Note that setting specific bits in the ACTLR register may not be
872 available in non-secure mode.
874 config ARM_ERRATA_458693
875 bool "ARM errata: Processor deadlock when a false hazard is created"
877 depends on !ARCH_MULTIPLATFORM
879 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
880 erratum. For very specific sequences of memory operations, it is
881 possible for a hazard condition intended for a cache line to instead
882 be incorrectly associated with a different cache line. This false
883 hazard might then cause a processor deadlock. The workaround enables
884 the L1 caching of the NEON accesses and disables the PLD instruction
885 in the ACTLR register. Note that setting specific bits in the ACTLR
886 register may not be available in non-secure mode.
888 config ARM_ERRATA_460075
889 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
891 depends on !ARCH_MULTIPLATFORM
893 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
894 erratum. Any asynchronous access to the L2 cache may encounter a
895 situation in which recent store transactions to the L2 cache are lost
896 and overwritten with stale memory contents from external memory. The
897 workaround disables the write-allocate mode for the L2 cache via the
898 ACTLR register. Note that setting specific bits in the ACTLR register
899 may not be available in non-secure mode.
901 config ARM_ERRATA_742230
902 bool "ARM errata: DMB operation may be faulty"
903 depends on CPU_V7 && SMP
904 depends on !ARCH_MULTIPLATFORM
906 This option enables the workaround for the 742230 Cortex-A9
907 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
908 between two write operations may not ensure the correct visibility
909 ordering of the two writes. This workaround sets a specific bit in
910 the diagnostic register of the Cortex-A9 which causes the DMB
911 instruction to behave as a DSB, ensuring the correct behaviour of
914 config ARM_ERRATA_742231
915 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
916 depends on CPU_V7 && SMP
917 depends on !ARCH_MULTIPLATFORM
919 This option enables the workaround for the 742231 Cortex-A9
920 (r2p0..r2p2) erratum. Under certain conditions, specific to the
921 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
922 accessing some data located in the same cache line, may get corrupted
923 data due to bad handling of the address hazard when the line gets
924 replaced from one of the CPUs at the same time as another CPU is
925 accessing it. This workaround sets specific bits in the diagnostic
926 register of the Cortex-A9 which reduces the linefill issuing
927 capabilities of the processor.
929 config ARM_ERRATA_643719
930 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
931 depends on CPU_V7 && SMP
934 This option enables the workaround for the 643719 Cortex-A9 (prior to
935 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
936 register returns zero when it should return one. The workaround
937 corrects this value, ensuring cache maintenance operations which use
938 it behave as intended and avoiding data corruption.
940 config ARM_ERRATA_720789
941 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
944 This option enables the workaround for the 720789 Cortex-A9 (prior to
945 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
946 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
947 As a consequence of this erratum, some TLB entries which should be
948 invalidated are not, resulting in an incoherency in the system page
949 tables. The workaround changes the TLB flushing routines to invalidate
950 entries regardless of the ASID.
952 config ARM_ERRATA_743622
953 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
955 depends on !ARCH_MULTIPLATFORM
957 This option enables the workaround for the 743622 Cortex-A9
958 (r2p*) erratum. Under very rare conditions, a faulty
959 optimisation in the Cortex-A9 Store Buffer may lead to data
960 corruption. This workaround sets a specific bit in the diagnostic
961 register of the Cortex-A9 which disables the Store Buffer
962 optimisation, preventing the defect from occurring. This has no
963 visible impact on the overall performance or power consumption of the
966 config ARM_ERRATA_751472
967 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
969 depends on !ARCH_MULTIPLATFORM
971 This option enables the workaround for the 751472 Cortex-A9 (prior
972 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
973 completion of a following broadcasted operation if the second
974 operation is received by a CPU before the ICIALLUIS has completed,
975 potentially leading to corrupted entries in the cache or TLB.
977 config ARM_ERRATA_754322
978 bool "ARM errata: possible faulty MMU translations following an ASID switch"
981 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
982 r3p*) erratum. A speculative memory access may cause a page table walk
983 which starts prior to an ASID switch but completes afterwards. This
984 can populate the micro-TLB with a stale entry which may be hit with
985 the new ASID. This workaround places two dsb instructions in the mm
986 switching code so that no page table walks can cross the ASID switch.
988 config ARM_ERRATA_754327
989 bool "ARM errata: no automatic Store Buffer drain"
990 depends on CPU_V7 && SMP
992 This option enables the workaround for the 754327 Cortex-A9 (prior to
993 r2p0) erratum. The Store Buffer does not have any automatic draining
994 mechanism and therefore a livelock may occur if an external agent
995 continuously polls a memory location waiting to observe an update.
996 This workaround defines cpu_relax() as smp_mb(), preventing correctly
997 written polling loops from denying visibility of updates to memory.
999 config ARM_ERRATA_364296
1000 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1003 This options enables the workaround for the 364296 ARM1136
1004 r0p2 erratum (possible cache data corruption with
1005 hit-under-miss enabled). It sets the undocumented bit 31 in
1006 the auxiliary control register and the FI bit in the control
1007 register, thus disabling hit-under-miss without putting the
1008 processor into full low interrupt latency mode. ARM11MPCore
1011 config ARM_ERRATA_764369
1012 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1013 depends on CPU_V7 && SMP
1015 This option enables the workaround for erratum 764369
1016 affecting Cortex-A9 MPCore with two or more processors (all
1017 current revisions). Under certain timing circumstances, a data
1018 cache line maintenance operation by MVA targeting an Inner
1019 Shareable memory region may fail to proceed up to either the
1020 Point of Coherency or to the Point of Unification of the
1021 system. This workaround adds a DSB instruction before the
1022 relevant cache maintenance functions and sets a specific bit
1023 in the diagnostic control register of the SCU.
1025 config ARM_ERRATA_775420
1026 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1029 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1030 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1031 operation aborts with MMU exception, it might cause the processor
1032 to deadlock. This workaround puts DSB before executing ISB if
1033 an abort may occur on cache maintenance.
1035 config ARM_ERRATA_798181
1036 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1037 depends on CPU_V7 && SMP
1039 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1040 adequately shooting down all use of the old entries. This
1041 option enables the Linux kernel workaround for this erratum
1042 which sends an IPI to the CPUs that are running the same ASID
1043 as the one being invalidated.
1045 config ARM_ERRATA_773022
1046 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1049 This option enables the workaround for the 773022 Cortex-A15
1050 (up to r0p4) erratum. In certain rare sequences of code, the
1051 loop buffer may deliver incorrect instructions. This
1052 workaround disables the loop buffer to avoid the erratum.
1054 config ARM_ERRATA_818325_852422
1055 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1058 This option enables the workaround for:
1059 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1060 instruction might deadlock. Fixed in r0p1.
1061 - Cortex-A12 852422: Execution of a sequence of instructions might
1062 lead to either a data corruption or a CPU deadlock. Not fixed in
1063 any Cortex-A12 cores yet.
1064 This workaround for all both errata involves setting bit[12] of the
1065 Feature Register. This bit disables an optimisation applied to a
1066 sequence of 2 instructions that use opposing condition codes.
1068 config ARM_ERRATA_821420
1069 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1072 This option enables the workaround for the 821420 Cortex-A12
1073 (all revs) erratum. In very rare timing conditions, a sequence
1074 of VMOV to Core registers instructions, for which the second
1075 one is in the shadow of a branch or abort, can lead to a
1076 deadlock when the VMOV instructions are issued out-of-order.
1078 config ARM_ERRATA_825619
1079 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1082 This option enables the workaround for the 825619 Cortex-A12
1083 (all revs) erratum. Within rare timing constraints, executing a
1084 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1085 and Device/Strongly-Ordered loads and stores might cause deadlock
1087 config ARM_ERRATA_857271
1088 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1091 This option enables the workaround for the 857271 Cortex-A12
1092 (all revs) erratum. Under very rare timing conditions, the CPU might
1093 hang. The workaround is expected to have a < 1% performance impact.
1095 config ARM_ERRATA_852421
1096 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1099 This option enables the workaround for the 852421 Cortex-A17
1100 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1101 execution of a DMB ST instruction might fail to properly order
1102 stores from GroupA and stores from GroupB.
1104 config ARM_ERRATA_852423
1105 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1108 This option enables the workaround for:
1109 - Cortex-A17 852423: Execution of a sequence of instructions might
1110 lead to either a data corruption or a CPU deadlock. Not fixed in
1111 any Cortex-A17 cores yet.
1112 This is identical to Cortex-A12 erratum 852422. It is a separate
1113 config option from the A12 erratum due to the way errata are checked
1116 config ARM_ERRATA_857272
1117 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1120 This option enables the workaround for the 857272 Cortex-A17 erratum.
1121 This erratum is not known to be fixed in any A17 revision.
1122 This is identical to Cortex-A12 erratum 857271. It is a separate
1123 config option from the A12 erratum due to the way errata are checked
1128 source "arch/arm/common/Kconfig"
1135 Find out whether you have ISA slots on your motherboard. ISA is the
1136 name of a bus system, i.e. the way the CPU talks to the other stuff
1137 inside your box. Other bus systems are PCI, EISA, MicroChannel
1138 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1139 newer boards don't support it. If you have ISA, say Y, otherwise N.
1141 # Select ISA DMA controller support
1146 # Select ISA DMA interface
1150 config PCI_NANOENGINE
1151 bool "BSE nanoEngine PCI support"
1152 depends on SA1100_NANOENGINE
1154 Enable PCI on the BSE nanoEngine board.
1156 config ARM_ERRATA_814220
1157 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1160 The v7 ARM states that all cache and branch predictor maintenance
1161 operations that do not specify an address execute, relative to
1162 each other, in program order.
1163 However, because of this erratum, an L2 set/way cache maintenance
1164 operation can overtake an L1 set/way cache maintenance operation.
1165 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1170 menu "Kernel Features"
1175 This option should be selected by machines which have an SMP-
1178 The only effect of this option is to make the SMP-related
1179 options available to the user for configuration.
1182 bool "Symmetric Multi-Processing"
1183 depends on CPU_V6K || CPU_V7
1184 depends on GENERIC_CLOCKEVENTS
1186 depends on MMU || ARM_MPU
1189 This enables support for systems with more than one CPU. If you have
1190 a system with only one CPU, say N. If you have a system with more
1191 than one CPU, say Y.
1193 If you say N here, the kernel will run on uni- and multiprocessor
1194 machines, but will use only one CPU of a multiprocessor machine. If
1195 you say Y here, the kernel will run on many, but not all,
1196 uniprocessor machines. On a uniprocessor machine, the kernel
1197 will run faster if you say N here.
1199 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1200 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1201 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1203 If you don't know what to do here, say N.
1206 bool "Allow booting SMP kernel on uniprocessor systems"
1207 depends on SMP && !XIP_KERNEL && MMU
1210 SMP kernels contain instructions which fail on non-SMP processors.
1211 Enabling this option allows the kernel to modify itself to make
1212 these instructions safe. Disabling it allows about 1K of space
1215 If you don't know what to do here, say Y.
1217 config ARM_CPU_TOPOLOGY
1218 bool "Support cpu topology definition"
1219 depends on SMP && CPU_V7
1222 Support ARM cpu topology definition. The MPIDR register defines
1223 affinity between processors which is then used to describe the cpu
1224 topology of an ARM System.
1227 bool "Multi-core scheduler support"
1228 depends on ARM_CPU_TOPOLOGY
1230 Multi-core scheduler support improves the CPU scheduler's decision
1231 making when dealing with multi-core CPU chips at a cost of slightly
1232 increased overhead in some places. If unsure say N here.
1235 bool "SMT scheduler support"
1236 depends on ARM_CPU_TOPOLOGY
1238 Improves the CPU scheduler's decision making when dealing with
1239 MultiThreading at a cost of slightly increased overhead in some
1240 places. If unsure say N here.
1245 This option enables support for the ARM snoop control unit
1247 config HAVE_ARM_ARCH_TIMER
1248 bool "Architected timer support"
1250 select ARM_ARCH_TIMER
1252 This option enables support for the ARM architected timer
1257 This options enables support for the ARM timer and watchdog unit
1260 bool "Multi-Cluster Power Management"
1261 depends on CPU_V7 && SMP
1263 This option provides the common power management infrastructure
1264 for (multi-)cluster based systems, such as big.LITTLE based
1267 config MCPM_QUAD_CLUSTER
1271 To avoid wasting resources unnecessarily, MCPM only supports up
1272 to 2 clusters by default.
1273 Platforms with 3 or 4 clusters that use MCPM must select this
1274 option to allow the additional clusters to be managed.
1277 bool "big.LITTLE support (Experimental)"
1278 depends on CPU_V7 && SMP
1281 This option enables support selections for the big.LITTLE
1282 system architecture.
1285 bool "big.LITTLE switcher support"
1286 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1289 The big.LITTLE "switcher" provides the core functionality to
1290 transparently handle transition between a cluster of A15's
1291 and a cluster of A7's in a big.LITTLE system.
1293 config BL_SWITCHER_DUMMY_IF
1294 tristate "Simple big.LITTLE switcher user interface"
1295 depends on BL_SWITCHER && DEBUG_KERNEL
1297 This is a simple and dummy char dev interface to control
1298 the big.LITTLE switcher core code. It is meant for
1299 debugging purposes only.
1302 prompt "Memory split"
1306 Select the desired split between kernel and user memory.
1308 If you are not absolutely sure what you are doing, leave this
1312 bool "3G/1G user/kernel split"
1313 config VMSPLIT_3G_OPT
1314 depends on !ARM_LPAE
1315 bool "3G/1G user/kernel split (for full 1G low memory)"
1317 bool "2G/2G user/kernel split"
1319 bool "1G/3G user/kernel split"
1324 default PHYS_OFFSET if !MMU
1325 default 0x40000000 if VMSPLIT_1G
1326 default 0x80000000 if VMSPLIT_2G
1327 default 0xB0000000 if VMSPLIT_3G_OPT
1331 int "Maximum number of CPUs (2-32)"
1337 bool "Support for hot-pluggable CPUs"
1339 select GENERIC_IRQ_MIGRATION
1341 Say Y here to experiment with turning CPUs off and on. CPUs
1342 can be controlled through /sys/devices/system/cpu.
1345 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1346 depends on HAVE_ARM_SMCCC
1349 Say Y here if you want Linux to communicate with system firmware
1350 implementing the PSCI specification for CPU-centric power
1351 management operations described in ARM document number ARM DEN
1352 0022A ("Power State Coordination Interface System Software on
1355 # The GPIO number here must be sorted by descending number. In case of
1356 # a multiplatform kernel, we just want the highest value required by the
1357 # selected platforms.
1360 default 2048 if ARCH_SOCFPGA
1361 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1362 ARCH_ZYNQ || ARCH_ASPEED
1363 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1364 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1365 default 416 if ARCH_SUNXI
1366 default 392 if ARCH_U8500
1367 default 352 if ARCH_VT8500
1368 default 288 if ARCH_ROCKCHIP
1369 default 264 if MACH_H4700
1372 Maximum number of GPIOs in the system.
1374 If unsure, leave the default value.
1378 default 200 if ARCH_EBSA110
1379 default 128 if SOC_AT91RM9200
1383 depends on HZ_FIXED = 0
1384 prompt "Timer frequency"
1408 default HZ_FIXED if HZ_FIXED != 0
1409 default 100 if HZ_100
1410 default 200 if HZ_200
1411 default 250 if HZ_250
1412 default 300 if HZ_300
1413 default 500 if HZ_500
1417 def_bool HIGH_RES_TIMERS
1419 config THUMB2_KERNEL
1420 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1421 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1422 default y if CPU_THUMBONLY
1425 By enabling this option, the kernel will be compiled in
1430 config ARM_PATCH_IDIV
1431 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1432 depends on CPU_32v7 && !XIP_KERNEL
1435 The ARM compiler inserts calls to __aeabi_idiv() and
1436 __aeabi_uidiv() when it needs to perform division on signed
1437 and unsigned integers. Some v7 CPUs have support for the sdiv
1438 and udiv instructions that can be used to implement those
1441 Enabling this option allows the kernel to modify itself to
1442 replace the first two instructions of these library functions
1443 with the sdiv or udiv plus "bx lr" instructions when the CPU
1444 it is running on supports them. Typically this will be faster
1445 and less power intensive than running the original library
1446 code to do integer division.
1449 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1450 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1451 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1453 This option allows for the kernel to be compiled using the latest
1454 ARM ABI (aka EABI). This is only useful if you are using a user
1455 space environment that is also compiled with EABI.
1457 Since there are major incompatibilities between the legacy ABI and
1458 EABI, especially with regard to structure member alignment, this
1459 option also changes the kernel syscall calling convention to
1460 disambiguate both ABIs and allow for backward compatibility support
1461 (selected with CONFIG_OABI_COMPAT).
1463 To use this you need GCC version 4.0.0 or later.
1466 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1467 depends on AEABI && !THUMB2_KERNEL
1469 This option preserves the old syscall interface along with the
1470 new (ARM EABI) one. It also provides a compatibility layer to
1471 intercept syscalls that have structure arguments which layout
1472 in memory differs between the legacy ABI and the new ARM EABI
1473 (only for non "thumb" binaries). This option adds a tiny
1474 overhead to all syscalls and produces a slightly larger kernel.
1476 The seccomp filter system will not be available when this is
1477 selected, since there is no way yet to sensibly distinguish
1478 between calling conventions during filtering.
1480 If you know you'll be using only pure EABI user space then you
1481 can say N here. If this option is not selected and you attempt
1482 to execute a legacy ABI binary then the result will be
1483 UNPREDICTABLE (in fact it can be predicted that it won't work
1484 at all). If in doubt say N.
1486 config ARCH_HAS_HOLES_MEMORYMODEL
1489 config ARCH_SELECT_MEMORY_MODEL
1492 config ARCH_FLATMEM_ENABLE
1495 config ARCH_SPARSEMEM_ENABLE
1497 select SPARSEMEM_STATIC if SPARSEMEM
1499 config HAVE_ARCH_PFN_VALID
1500 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1503 bool "High Memory Support"
1506 The address space of ARM processors is only 4 Gigabytes large
1507 and it has to accommodate user address space, kernel address
1508 space as well as some memory mapped IO. That means that, if you
1509 have a large amount of physical memory and/or IO, not all of the
1510 memory can be "permanently mapped" by the kernel. The physical
1511 memory that is not permanently mapped is called "high memory".
1513 Depending on the selected kernel/user memory split, minimum
1514 vmalloc space and actual amount of RAM, you may not need this
1515 option which should result in a slightly faster kernel.
1520 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1524 The VM uses one page of physical memory for each page table.
1525 For systems with a lot of processes, this can use a lot of
1526 precious low memory, eventually leading to low memory being
1527 consumed by page tables. Setting this option will allow
1528 user-space 2nd level page tables to reside in high memory.
1530 config CPU_SW_DOMAIN_PAN
1531 bool "Enable use of CPU domains to implement privileged no-access"
1532 depends on MMU && !ARM_LPAE
1535 Increase kernel security by ensuring that normal kernel accesses
1536 are unable to access userspace addresses. This can help prevent
1537 use-after-free bugs becoming an exploitable privilege escalation
1538 by ensuring that magic values (such as LIST_POISON) will always
1539 fault when dereferenced.
1541 CPUs with low-vector mappings use a best-efforts implementation.
1542 Their lower 1MB needs to remain accessible for the vectors, but
1543 the remainder of userspace will become appropriately inaccessible.
1545 config HW_PERF_EVENTS
1549 config SYS_SUPPORTS_HUGETLBFS
1553 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1557 config ARCH_WANT_GENERAL_HUGETLB
1560 config ARM_MODULE_PLTS
1561 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1565 Allocate PLTs when loading modules so that jumps and calls whose
1566 targets are too far away for their relative offsets to be encoded
1567 in the instructions themselves can be bounced via veneers in the
1568 module's PLT. This allows modules to be allocated in the generic
1569 vmalloc area after the dedicated module memory area has been
1570 exhausted. The modules will use slightly more memory, but after
1571 rounding up to page size, the actual memory footprint is usually
1574 Disabling this is usually safe for small single-platform
1575 configurations. If unsure, say y.
1577 config FORCE_MAX_ZONEORDER
1578 int "Maximum zone order"
1579 default "12" if SOC_AM33XX
1580 default "9" if SA1111 || ARCH_EFM32
1583 The kernel memory allocator divides physically contiguous memory
1584 blocks into "zones", where each zone is a power of two number of
1585 pages. This option selects the largest power of two that the kernel
1586 keeps in the memory allocator. If you need to allocate very large
1587 blocks of physically contiguous memory, then you may need to
1588 increase this value.
1590 This config option is actually maximum order plus one. For example,
1591 a value of 11 means that the largest free memory block is 2^10 pages.
1593 config ALIGNMENT_TRAP
1595 depends on CPU_CP15_MMU
1596 default y if !ARCH_EBSA110
1597 select HAVE_PROC_CPU if PROC_FS
1599 ARM processors cannot fetch/store information which is not
1600 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1601 address divisible by 4. On 32-bit ARM processors, these non-aligned
1602 fetch/store instructions will be emulated in software if you say
1603 here, which has a severe performance impact. This is necessary for
1604 correct operation of some network protocols. With an IP-only
1605 configuration it is safe to say N, otherwise say Y.
1607 config UACCESS_WITH_MEMCPY
1608 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1610 default y if CPU_FEROCEON
1612 Implement faster copy_to_user and clear_user methods for CPU
1613 cores where a 8-word STM instruction give significantly higher
1614 memory write throughput than a sequence of individual 32bit stores.
1616 A possible side effect is a slight increase in scheduling latency
1617 between threads sharing the same address space if they invoke
1618 such copy operations with large buffers.
1620 However, if the CPU data cache is using a write-allocate mode,
1621 this option is unlikely to provide any performance gain.
1624 bool "Enable paravirtualization code"
1626 This changes the kernel so it can modify itself when it is run
1627 under a hypervisor, potentially improving performance significantly
1628 over full virtualization.
1630 config PARAVIRT_TIME_ACCOUNTING
1631 bool "Paravirtual steal time accounting"
1634 Select this option to enable fine granularity task steal time
1635 accounting. Time spent executing other tasks in parallel with
1636 the current vCPU is discounted from the vCPU power. To account for
1637 that, there can be a small performance impact.
1639 If in doubt, say N here.
1646 bool "Xen guest support on ARM"
1647 depends on ARM && AEABI && OF
1648 depends on CPU_V7 && !CPU_V6
1649 depends on !GENERIC_ATOMIC64
1651 select ARCH_DMA_ADDR_T_64BIT
1657 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1659 config STACKPROTECTOR_PER_TASK
1660 bool "Use a unique stack canary value for each task"
1661 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1662 select GCC_PLUGIN_ARM_SSP_PER_TASK
1665 Due to the fact that GCC uses an ordinary symbol reference from
1666 which to load the value of the stack canary, this value can only
1667 change at reboot time on SMP systems, and all tasks running in the
1668 kernel's address space are forced to use the same canary value for
1669 the entire duration that the system is up.
1671 Enable this option to switch to a different method that uses a
1672 different canary value for each task.
1679 bool "Flattened Device Tree support"
1683 Include support for flattened device tree machine descriptions.
1686 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1689 This is the traditional way of passing data to the kernel at boot
1690 time. If you are solely relying on the flattened device tree (or
1691 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1692 to remove ATAGS support from your kernel binary. If unsure,
1695 config DEPRECATED_PARAM_STRUCT
1696 bool "Provide old way to pass kernel parameters"
1699 This was deprecated in 2001 and announced to live on for 5 years.
1700 Some old boot loaders still use this way.
1702 # Compressed boot loader in ROM. Yes, we really want to ask about
1703 # TEXT and BSS so we preserve their values in the config files.
1704 config ZBOOT_ROM_TEXT
1705 hex "Compressed ROM boot loader base address"
1708 The physical address at which the ROM-able zImage is to be
1709 placed in the target. Platforms which normally make use of
1710 ROM-able zImage formats normally set this to a suitable
1711 value in their defconfig file.
1713 If ZBOOT_ROM is not enabled, this has no effect.
1715 config ZBOOT_ROM_BSS
1716 hex "Compressed ROM boot loader BSS address"
1719 The base address of an area of read/write memory in the target
1720 for the ROM-able zImage which must be available while the
1721 decompressor is running. It must be large enough to hold the
1722 entire decompressed kernel plus an additional 128 KiB.
1723 Platforms which normally make use of ROM-able zImage formats
1724 normally set this to a suitable value in their defconfig file.
1726 If ZBOOT_ROM is not enabled, this has no effect.
1729 bool "Compressed boot loader in ROM/flash"
1730 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1731 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1733 Say Y here if you intend to execute your compressed kernel image
1734 (zImage) directly from ROM or flash. If unsure, say N.
1736 config ARM_APPENDED_DTB
1737 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1740 With this option, the boot code will look for a device tree binary
1741 (DTB) appended to zImage
1742 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1744 This is meant as a backward compatibility convenience for those
1745 systems with a bootloader that can't be upgraded to accommodate
1746 the documented boot protocol using a device tree.
1748 Beware that there is very little in terms of protection against
1749 this option being confused by leftover garbage in memory that might
1750 look like a DTB header after a reboot if no actual DTB is appended
1751 to zImage. Do not leave this option active in a production kernel
1752 if you don't intend to always append a DTB. Proper passing of the
1753 location into r2 of a bootloader provided DTB is always preferable
1756 config ARM_ATAG_DTB_COMPAT
1757 bool "Supplement the appended DTB with traditional ATAG information"
1758 depends on ARM_APPENDED_DTB
1760 Some old bootloaders can't be updated to a DTB capable one, yet
1761 they provide ATAGs with memory configuration, the ramdisk address,
1762 the kernel cmdline string, etc. Such information is dynamically
1763 provided by the bootloader and can't always be stored in a static
1764 DTB. To allow a device tree enabled kernel to be used with such
1765 bootloaders, this option allows zImage to extract the information
1766 from the ATAG list and store it at run time into the appended DTB.
1769 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1770 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1772 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1773 bool "Use bootloader kernel arguments if available"
1775 Uses the command-line options passed by the boot loader instead of
1776 the device tree bootargs property. If the boot loader doesn't provide
1777 any, the device tree bootargs property will be used.
1779 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1780 bool "Extend with bootloader kernel arguments"
1782 The command-line arguments provided by the boot loader will be
1783 appended to the the device tree bootargs property.
1788 string "Default kernel command string"
1791 On some architectures (EBSA110 and CATS), there is currently no way
1792 for the boot loader to pass arguments to the kernel. For these
1793 architectures, you should supply some command-line options at build
1794 time by entering them here. As a minimum, you should specify the
1795 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1798 prompt "Kernel command line type" if CMDLINE != ""
1799 default CMDLINE_FROM_BOOTLOADER
1802 config CMDLINE_FROM_BOOTLOADER
1803 bool "Use bootloader kernel arguments if available"
1805 Uses the command-line options passed by the boot loader. If
1806 the boot loader doesn't provide any, the default kernel command
1807 string provided in CMDLINE will be used.
1809 config CMDLINE_EXTEND
1810 bool "Extend bootloader kernel arguments"
1812 The command-line arguments provided by the boot loader will be
1813 appended to the default kernel command string.
1815 config CMDLINE_FORCE
1816 bool "Always use the default kernel command string"
1818 Always use the default kernel command string, even if the boot
1819 loader passes other arguments to the kernel.
1820 This is useful if you cannot or don't want to change the
1821 command-line options your boot loader passes to the kernel.
1825 bool "Kernel Execute-In-Place from ROM"
1826 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1828 Execute-In-Place allows the kernel to run from non-volatile storage
1829 directly addressable by the CPU, such as NOR flash. This saves RAM
1830 space since the text section of the kernel is not loaded from flash
1831 to RAM. Read-write sections, such as the data section and stack,
1832 are still copied to RAM. The XIP kernel is not compressed since
1833 it has to run directly from flash, so it will take more space to
1834 store it. The flash address used to link the kernel object files,
1835 and for storing it, is configuration dependent. Therefore, if you
1836 say Y here, you must know the proper physical address where to
1837 store the kernel image depending on your own flash memory usage.
1839 Also note that the make target becomes "make xipImage" rather than
1840 "make zImage" or "make Image". The final kernel binary to put in
1841 ROM memory will be arch/arm/boot/xipImage.
1845 config XIP_PHYS_ADDR
1846 hex "XIP Kernel Physical Location"
1847 depends on XIP_KERNEL
1848 default "0x00080000"
1850 This is the physical address in your flash memory the kernel will
1851 be linked for and stored to. This address is dependent on your
1854 config XIP_DEFLATED_DATA
1855 bool "Store kernel .data section compressed in ROM"
1856 depends on XIP_KERNEL
1859 Before the kernel is actually executed, its .data section has to be
1860 copied to RAM from ROM. This option allows for storing that data
1861 in compressed form and decompressed to RAM rather than merely being
1862 copied, saving some precious ROM space. A possible drawback is a
1863 slightly longer boot delay.
1866 bool "Kexec system call (EXPERIMENTAL)"
1867 depends on (!SMP || PM_SLEEP_SMP)
1871 kexec is a system call that implements the ability to shutdown your
1872 current kernel, and to start another kernel. It is like a reboot
1873 but it is independent of the system firmware. And like a reboot
1874 you can start any kernel with it, not just Linux.
1876 It is an ongoing process to be certain the hardware in a machine
1877 is properly shutdown, so do not be surprised if this code does not
1878 initially work for you.
1881 bool "Export atags in procfs"
1882 depends on ATAGS && KEXEC
1885 Should the atags used to boot the kernel be exported in an "atags"
1886 file in procfs. Useful with kexec.
1889 bool "Build kdump crash kernel (EXPERIMENTAL)"
1891 Generate crash dump after being started by kexec. This should
1892 be normally only set in special crash dump kernels which are
1893 loaded in the main kernel with kexec-tools into a specially
1894 reserved region and then later executed after a crash by
1895 kdump/kexec. The crash dump kernel must be compiled to a
1896 memory address not used by the main kernel
1898 For more details see Documentation/admin-guide/kdump/kdump.rst
1900 config AUTO_ZRELADDR
1901 bool "Auto calculation of the decompressed kernel image address"
1903 ZRELADDR is the physical address where the decompressed kernel
1904 image will be placed. If AUTO_ZRELADDR is selected, the address
1905 will be determined at run-time by masking the current IP with
1906 0xf8000000. This assumes the zImage being placed in the first 128MB
1907 from start of memory.
1913 bool "UEFI runtime support"
1914 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1916 select EFI_PARAMS_FROM_FDT
1918 select EFI_GENERIC_STUB
1919 select EFI_RUNTIME_WRAPPERS
1921 This option provides support for runtime services provided
1922 by UEFI firmware (such as non-volatile variables, realtime
1923 clock, and platform reset). A UEFI stub is also provided to
1924 allow the kernel to be booted as an EFI application. This
1925 is only useful for kernels that may run on systems that have
1929 bool "Enable support for SMBIOS (DMI) tables"
1933 This enables SMBIOS/DMI feature for systems.
1935 This option is only useful on systems that have UEFI firmware.
1936 However, even with this option, the resultant kernel should
1937 continue to boot on existing non-UEFI platforms.
1939 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1940 i.e., the the practice of identifying the platform via DMI to
1941 decide whether certain workarounds for buggy hardware and/or
1942 firmware need to be enabled. This would require the DMI subsystem
1943 to be enabled much earlier than we do on ARM, which is non-trivial.
1947 menu "CPU Power Management"
1949 source "drivers/cpufreq/Kconfig"
1951 source "drivers/cpuidle/Kconfig"
1955 menu "Floating point emulation"
1957 comment "At least one emulation must be selected"
1960 bool "NWFPE math emulation"
1961 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1963 Say Y to include the NWFPE floating point emulator in the kernel.
1964 This is necessary to run most binaries. Linux does not currently
1965 support floating point hardware so you need to say Y here even if
1966 your machine has an FPA or floating point co-processor podule.
1968 You may say N here if you are going to load the Acorn FPEmulator
1969 early in the bootup.
1972 bool "Support extended precision"
1973 depends on FPE_NWFPE
1975 Say Y to include 80-bit support in the kernel floating-point
1976 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1977 Note that gcc does not generate 80-bit operations by default,
1978 so in most cases this option only enlarges the size of the
1979 floating point emulator without any good reason.
1981 You almost surely want to say N here.
1984 bool "FastFPE math emulation (EXPERIMENTAL)"
1985 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1987 Say Y here to include the FAST floating point emulator in the kernel.
1988 This is an experimental much faster emulator which now also has full
1989 precision for the mantissa. It does not support any exceptions.
1990 It is very simple, and approximately 3-6 times faster than NWFPE.
1992 It should be sufficient for most programs. It may be not suitable
1993 for scientific calculations, but you have to check this for yourself.
1994 If you do not feel you need a faster FP emulation you should better
1998 bool "VFP-format floating point maths"
1999 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2001 Say Y to include VFP support code in the kernel. This is needed
2002 if your hardware includes a VFP unit.
2004 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2005 release notes and additional status information.
2007 Say N if your target does not have VFP hardware.
2015 bool "Advanced SIMD (NEON) Extension support"
2016 depends on VFPv3 && CPU_V7
2018 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2021 config KERNEL_MODE_NEON
2022 bool "Support for NEON in kernel mode"
2023 depends on NEON && AEABI
2025 Say Y to include support for NEON in kernel mode.
2029 menu "Power management options"
2031 source "kernel/power/Kconfig"
2033 config ARCH_SUSPEND_POSSIBLE
2034 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2035 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2038 config ARM_CPU_SUSPEND
2039 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2040 depends on ARCH_SUSPEND_POSSIBLE
2042 config ARCH_HIBERNATION_POSSIBLE
2045 default y if ARCH_SUSPEND_POSSIBLE
2049 source "drivers/firmware/Kconfig"
2052 source "arch/arm/crypto/Kconfig"
2055 source "arch/arm/Kconfig.assembler"