4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_KERNEL_GZIP
40 select HAVE_KERNEL_LZMA
41 select HAVE_KERNEL_LZO
43 select HAVE_KPROBES if !XIP_KERNEL
44 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
47 select HAVE_PERF_EVENTS
48 select HAVE_REGS_AND_STACK_ACCESS_API
49 select HAVE_SYSCALL_TRACEPOINTS
52 select PERF_USE_VMALLOC
54 select SYS_SUPPORTS_APM_EMULATION
55 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
56 select MODULES_USE_ELF_REL
57 select CLONE_BACKWARDS
59 The ARM series is a line of low-power-consumption RISC chip designs
60 licensed by ARM Ltd and targeted at embedded applications and
61 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
62 manufactured, but legacy ARM-based PC hardware remains popular in
63 Europe. There is an ARM Linux project with a web page at
64 <http://www.arm.linux.org.uk/>.
66 config ARM_HAS_SG_CHAIN
69 config NEED_SG_DMA_LENGTH
72 config ARM_DMA_USE_IOMMU
74 select ARM_HAS_SG_CHAIN
75 select NEED_SG_DMA_LENGTH
83 config SYS_SUPPORTS_APM_EMULATION
91 select GENERIC_ALLOCATOR
102 The Extended Industry Standard Architecture (EISA) bus was
103 developed as an open alternative to the IBM MicroChannel bus.
105 The EISA bus provided some of the features of the IBM MicroChannel
106 bus while maintaining backward compatibility with cards made for
107 the older ISA bus. The EISA bus saw limited use between 1988 and
108 1995 when it was made obsolete by the PCI bus.
110 Say Y here if you are building a kernel for an EISA-based machine.
117 config STACKTRACE_SUPPORT
121 config HAVE_LATENCYTOP_SUPPORT
126 config LOCKDEP_SUPPORT
130 config TRACE_IRQFLAGS_SUPPORT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_GPIO_H
214 Select this when mach/gpio.h is required to provide special
215 definitions for this platform. The need for mach/gpio.h should
216 be avoided when possible.
218 config NEED_MACH_IO_H
221 Select this when mach/io.h is required to provide special
222 definitions for this platform. The need for mach/io.h should
223 be avoided when possible.
225 config NEED_MACH_MEMORY_H
228 Select this when mach/memory.h is required to provide special
229 definitions for this platform. The need for mach/memory.h should
230 be avoided when possible.
233 hex "Physical address of main memory" if MMU
234 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
235 default DRAM_BASE if !MMU
237 Please provide the physical address corresponding to the
238 location of main memory in your system.
244 source "init/Kconfig"
246 source "kernel/Kconfig.freezer"
251 bool "MMU-based Paged Memory Management Support"
254 Select if you want MMU-based virtualised addressing space
255 support by paged memory management. If unsure, say 'Y'.
258 # The "ARM system type" choice list is ordered alphabetically by option
259 # text. Please add new entries in the option alphabetic order.
262 prompt "ARM system type"
263 default ARCH_MULTIPLATFORM
265 config ARCH_MULTIPLATFORM
266 bool "Allow multiple platforms to be selected"
268 select ARM_PATCH_PHYS_VIRT
271 select MULTI_IRQ_HANDLER
275 config ARCH_INTEGRATOR
276 bool "ARM Ltd. Integrator family"
277 select ARCH_HAS_CPUFREQ
280 select COMMON_CLK_VERSATILE
281 select GENERIC_CLOCKEVENTS
284 select MULTI_IRQ_HANDLER
285 select NEED_MACH_MEMORY_H
286 select PLAT_VERSATILE
288 select VERSATILE_FPGA_IRQ
290 Support for ARM's Integrator platform.
293 bool "ARM Ltd. RealView family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select COMMON_CLK_VERSATILE
299 select GENERIC_CLOCKEVENTS
300 select GPIO_PL061 if GPIOLIB
302 select NEED_MACH_MEMORY_H
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_TIMER_SP804
315 select GENERIC_CLOCKEVENTS
316 select HAVE_MACH_CLKDEV
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLCD
320 select PLAT_VERSATILE_CLOCK
321 select VERSATILE_FPGA_IRQ
323 This enables support for ARM Ltd Versatile board.
327 select ARCH_REQUIRE_GPIOLIB
331 select NEED_MACH_GPIO_H
332 select NEED_MACH_IO_H if PCCARD
334 select PINCTRL_AT91 if USE_OF
336 This enables support for systems based on Atmel
337 AT91RM9200 and AT91SAM9* processors.
340 bool "Broadcom BCM2835 family"
341 select ARCH_REQUIRE_GPIOLIB
343 select ARM_ERRATA_411920
344 select ARM_TIMER_SP804
348 select GENERIC_CLOCKEVENTS
350 select MULTI_IRQ_HANDLER
352 select PINCTRL_BCM2835
356 This enables support for the Broadcom BCM2835 SoC. This SoC is
357 use in the Raspberry Pi, and Roku 2 devices.
360 bool "Cavium Networks CNS3XXX family"
363 select GENERIC_CLOCKEVENTS
364 select MIGHT_HAVE_CACHE_L2X0
365 select MIGHT_HAVE_PCI
366 select PCI_DOMAINS if PCI
368 Support for Cavium Networks CNS3XXX platform.
371 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
372 select ARCH_REQUIRE_GPIOLIB
377 select GENERIC_CLOCKEVENTS
378 select MULTI_IRQ_HANDLER
379 select NEED_MACH_MEMORY_H
382 Support for Cirrus Logic 711x/721x/731x based boards.
385 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_USES_GETTIMEOFFSET
390 Support for the Cortina Systems Gemini family SoCs
394 select ARCH_REQUIRE_GPIOLIB
396 select GENERIC_CLOCKEVENTS
397 select GENERIC_IRQ_CHIP
398 select MIGHT_HAVE_CACHE_L2X0
404 Support for CSR SiRFprimaII/Marco/Polo platforms
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_REQUIRE_GPIOLIB
424 select ARCH_USES_GETTIMEOFFSET
429 select NEED_MACH_MEMORY_H
431 This enables support for the Cirrus EP93xx series of CPUs.
433 config ARCH_FOOTBRIDGE
437 select GENERIC_CLOCKEVENTS
439 select NEED_MACH_IO_H if !MMU
440 select NEED_MACH_MEMORY_H
442 Support for systems based on the DC21285 companion chip
443 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
446 bool "Freescale MXS-based"
447 select ARCH_REQUIRE_GPIOLIB
451 select GENERIC_CLOCKEVENTS
452 select HAVE_CLK_PREPARE
453 select MULTI_IRQ_HANDLER
458 Support for Freescale MXS-based family of processors
461 bool "Hilscher NetX based"
465 select GENERIC_CLOCKEVENTS
467 This enables support for systems based on the Hilscher NetX Soc
470 bool "Hynix HMS720x-based"
471 select ARCH_USES_GETTIMEOFFSET
475 This enables support for systems based on the Hynix HMS720x
480 select ARCH_SUPPORTS_MSI
482 select NEED_MACH_MEMORY_H
483 select NEED_RET_TO_USER
488 Support for Intel's IOP13XX (XScale) family of processors.
493 select ARCH_REQUIRE_GPIOLIB
495 select NEED_MACH_GPIO_H
496 select NEED_RET_TO_USER
500 Support for Intel's 80219 and IOP32X (XScale) family of
506 select ARCH_REQUIRE_GPIOLIB
508 select NEED_MACH_GPIO_H
509 select NEED_RET_TO_USER
513 Support for Intel's IOP33X (XScale) family of processors.
518 select ARCH_HAS_DMA_SET_COHERENT_MASK
519 select ARCH_REQUIRE_GPIOLIB
522 select DMABOUNCE if PCI
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
525 select NEED_MACH_IO_H
527 Support for Intel's IXP4XX (XScale) family of processors.
531 select ARCH_REQUIRE_GPIOLIB
532 select COMMON_CLK_DOVE
534 select GENERIC_CLOCKEVENTS
535 select MIGHT_HAVE_PCI
538 select PLAT_ORION_LEGACY
539 select USB_ARCH_HAS_EHCI
541 Support for the Marvell Dove SoC 88AP510
544 bool "Marvell Kirkwood"
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
551 select PINCTRL_KIRKWOOD
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell Kirkwood series SoCs:
555 88F6180, 88F6192 and 88F6281.
558 bool "Marvell MV78xx0"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
563 select PLAT_ORION_LEGACY
565 Support for the following Marvell MV78xx0 series SoCs:
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Orion 5x series SoCs:
578 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
579 Orion-2 (5281), Orion-1-90 (6183).
582 bool "Marvell PXA168/910/MMP2"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_ALLOCATOR
587 select GENERIC_CLOCKEVENTS
590 select NEED_MACH_GPIO_H
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
626 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
634 select USB_ARCH_HAS_OHCI
637 Support for the NXP LPC32XX family of processors
641 select ARCH_HAS_CPUFREQ
645 select GENERIC_CLOCKEVENTS
649 select MIGHT_HAVE_CACHE_L2X0
653 This enables support for NVIDIA Tegra based systems (Tegra APX,
654 Tegra 6xx and Tegra 2 series).
657 bool "PXA2xx/PXA3xx-based"
659 select ARCH_HAS_CPUFREQ
661 select ARCH_REQUIRE_GPIOLIB
662 select ARM_CPU_SUSPEND if PM
666 select GENERIC_CLOCKEVENTS
669 select MULTI_IRQ_HANDLER
670 select NEED_MACH_GPIO_H
674 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
678 select ARCH_REQUIRE_GPIOLIB
680 select GENERIC_CLOCKEVENTS
683 Support for Qualcomm MSM/QSD based systems. This runs on the
684 apps processor of the MSM/QSD and depends on a shared memory
685 interface to the modem processor which runs the baseband
686 stack and controls some vital subsystems
687 (clock and power control, etc).
690 bool "Renesas SH-Mobile / R-Mobile"
692 select GENERIC_CLOCKEVENTS
694 select HAVE_MACH_CLKDEV
696 select MIGHT_HAVE_CACHE_L2X0
697 select MULTI_IRQ_HANDLER
698 select NEED_MACH_MEMORY_H
700 select PM_GENERIC_DOMAINS if PM
703 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
708 select ARCH_MAY_HAVE_PC_FDC
709 select ARCH_SPARSEMEM_ENABLE
710 select ARCH_USES_GETTIMEOFFSET
713 select HAVE_PATA_PLATFORM
715 select NEED_MACH_IO_H
716 select NEED_MACH_MEMORY_H
719 On the Acorn Risc-PC, Linux can support the internal IDE disk and
720 CD-ROM interface, serial and parallel port, and the floppy drive.
724 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
727 select ARCH_SPARSEMEM_ENABLE
732 select GENERIC_CLOCKEVENTS
735 select NEED_MACH_GPIO_H
736 select NEED_MACH_MEMORY_H
739 Support for StrongARM 11x0 based boards.
742 bool "Samsung S3C24XX SoCs"
743 select ARCH_HAS_CPUFREQ
744 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 select HAVE_S3C_RTC if RTC_CLASS
751 select NEED_MACH_GPIO_H
752 select NEED_MACH_IO_H
754 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
755 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
756 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
757 Samsung SMDK2410 development board (and derivatives).
760 bool "Samsung S3C64XX"
761 select ARCH_HAS_CPUFREQ
762 select ARCH_REQUIRE_GPIOLIB
763 select ARCH_USES_GETTIMEOFFSET
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select NEED_MACH_GPIO_H
775 select S3C_GPIO_TRACK
776 select SAMSUNG_CLKSRC
777 select SAMSUNG_GPIOLIB_4BIT
778 select SAMSUNG_IRQ_VIC_TIMER
779 select USB_ARCH_HAS_OHCI
781 Samsung S3C64XX series based systems
784 bool "Samsung S5P6440 S5P6450"
788 select GENERIC_CLOCKEVENTS
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 select HAVE_S3C_RTC if RTC_CLASS
794 select NEED_MACH_GPIO_H
796 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
800 bool "Samsung S5PC100"
801 select ARCH_USES_GETTIMEOFFSET
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select HAVE_S3C_RTC if RTC_CLASS
809 select NEED_MACH_GPIO_H
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
821 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select HAVE_S3C_RTC if RTC_CLASS
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_SPARSEMEM_ENABLE
839 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_GPIO_H
846 select NEED_MACH_MEMORY_H
848 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
852 select ARCH_USES_GETTIMEOFFSET
856 select NEED_MACH_MEMORY_H
860 Support for the StrongARM based Digital DNARD machine, also known
861 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 bool "ST-Ericsson U300 Series"
866 select ARCH_REQUIRE_GPIOLIB
868 select ARM_PATCH_PHYS_VIRT
874 select GENERIC_CLOCKEVENTS
879 Support for ST-Ericsson U300 series mobile platforms.
882 bool "ST-Ericsson U8500 Series"
884 select ARCH_HAS_CPUFREQ
885 select ARCH_REQUIRE_GPIOLIB
889 select GENERIC_CLOCKEVENTS
891 select MIGHT_HAVE_CACHE_L2X0
894 Support for ST-Ericsson's Ux500 architecture
897 bool "STMicroelectronics Nomadik"
898 select ARCH_REQUIRE_GPIOLIB
903 select GENERIC_CLOCKEVENTS
904 select MIGHT_HAVE_CACHE_L2X0
906 select PINCTRL_STN8815
909 Support for the Nomadik platform by ST-Ericsson
913 select ARCH_HAS_CPUFREQ
914 select ARCH_REQUIRE_GPIOLIB
919 select GENERIC_CLOCKEVENTS
922 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
926 select ARCH_HAS_HOLES_MEMORYMODEL
927 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_ALLOCATOR
930 select GENERIC_CLOCKEVENTS
931 select GENERIC_IRQ_CHIP
933 select NEED_MACH_GPIO_H
937 Support for TI's DaVinci platform.
942 select ARCH_HAS_CPUFREQ
943 select ARCH_HAS_HOLES_MEMORYMODEL
944 select ARCH_REQUIRE_GPIOLIB
946 select GENERIC_CLOCKEVENTS
949 Support for TI's OMAP platform (OMAP1/2/3/4).
951 config ARCH_VT8500_SINGLE
952 bool "VIA/WonderMedia 85xx"
953 select ARCH_HAS_CPUFREQ
954 select ARCH_REQUIRE_GPIOLIB
958 select GENERIC_CLOCKEVENTS
961 select MULTI_IRQ_HANDLER
965 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
969 menu "Multiple platform selection"
970 depends on ARCH_MULTIPLATFORM
972 comment "CPU Core family selection"
975 bool "ARMv4 based platforms (FA526, StrongARM)"
976 depends on !ARCH_MULTI_V6_V7
977 select ARCH_MULTI_V4_V5
979 config ARCH_MULTI_V4T
980 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
981 depends on !ARCH_MULTI_V6_V7
982 select ARCH_MULTI_V4_V5
985 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
986 depends on !ARCH_MULTI_V6_V7
987 select ARCH_MULTI_V4_V5
989 config ARCH_MULTI_V4_V5
993 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
994 select ARCH_MULTI_V6_V7
998 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1000 select ARCH_MULTI_V6_V7
1001 select ARCH_VEXPRESS
1004 config ARCH_MULTI_V6_V7
1007 config ARCH_MULTI_CPU_AUTO
1008 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1009 select ARCH_MULTI_V5
1014 # This is sorted alphabetically by mach-* pathname. However, plat-*
1015 # Kconfigs may be included either alphabetically (according to the
1016 # plat- suffix) or along side the corresponding mach-* source.
1018 source "arch/arm/mach-mvebu/Kconfig"
1020 source "arch/arm/mach-at91/Kconfig"
1022 source "arch/arm/mach-bcm/Kconfig"
1024 source "arch/arm/mach-clps711x/Kconfig"
1026 source "arch/arm/mach-cns3xxx/Kconfig"
1028 source "arch/arm/mach-davinci/Kconfig"
1030 source "arch/arm/mach-dove/Kconfig"
1032 source "arch/arm/mach-ep93xx/Kconfig"
1034 source "arch/arm/mach-footbridge/Kconfig"
1036 source "arch/arm/mach-gemini/Kconfig"
1038 source "arch/arm/mach-h720x/Kconfig"
1040 source "arch/arm/mach-highbank/Kconfig"
1042 source "arch/arm/mach-integrator/Kconfig"
1044 source "arch/arm/mach-iop32x/Kconfig"
1046 source "arch/arm/mach-iop33x/Kconfig"
1048 source "arch/arm/mach-iop13xx/Kconfig"
1050 source "arch/arm/mach-ixp4xx/Kconfig"
1052 source "arch/arm/mach-kirkwood/Kconfig"
1054 source "arch/arm/mach-ks8695/Kconfig"
1056 source "arch/arm/mach-msm/Kconfig"
1058 source "arch/arm/mach-mv78xx0/Kconfig"
1060 source "arch/arm/mach-imx/Kconfig"
1062 source "arch/arm/mach-mxs/Kconfig"
1064 source "arch/arm/mach-netx/Kconfig"
1066 source "arch/arm/mach-nomadik/Kconfig"
1068 source "arch/arm/plat-omap/Kconfig"
1070 source "arch/arm/mach-omap1/Kconfig"
1072 source "arch/arm/mach-omap2/Kconfig"
1074 source "arch/arm/mach-orion5x/Kconfig"
1076 source "arch/arm/mach-picoxcell/Kconfig"
1078 source "arch/arm/mach-pxa/Kconfig"
1079 source "arch/arm/plat-pxa/Kconfig"
1081 source "arch/arm/mach-mmp/Kconfig"
1083 source "arch/arm/mach-realview/Kconfig"
1085 source "arch/arm/mach-sa1100/Kconfig"
1087 source "arch/arm/plat-samsung/Kconfig"
1088 source "arch/arm/plat-s3c24xx/Kconfig"
1090 source "arch/arm/mach-socfpga/Kconfig"
1092 source "arch/arm/plat-spear/Kconfig"
1094 source "arch/arm/mach-s3c24xx/Kconfig"
1096 source "arch/arm/mach-s3c2412/Kconfig"
1097 source "arch/arm/mach-s3c2440/Kconfig"
1101 source "arch/arm/mach-s3c64xx/Kconfig"
1104 source "arch/arm/mach-s5p64x0/Kconfig"
1106 source "arch/arm/mach-s5pc100/Kconfig"
1108 source "arch/arm/mach-s5pv210/Kconfig"
1110 source "arch/arm/mach-exynos/Kconfig"
1112 source "arch/arm/mach-shmobile/Kconfig"
1114 source "arch/arm/mach-sunxi/Kconfig"
1116 source "arch/arm/mach-prima2/Kconfig"
1118 source "arch/arm/mach-tegra/Kconfig"
1120 source "arch/arm/mach-u300/Kconfig"
1122 source "arch/arm/mach-ux500/Kconfig"
1124 source "arch/arm/mach-versatile/Kconfig"
1126 source "arch/arm/mach-vexpress/Kconfig"
1127 source "arch/arm/plat-versatile/Kconfig"
1129 source "arch/arm/mach-vt8500/Kconfig"
1131 source "arch/arm/mach-w90x900/Kconfig"
1133 source "arch/arm/mach-zynq/Kconfig"
1135 # Definitions to make life easier
1141 select GENERIC_CLOCKEVENTS
1147 select GENERIC_IRQ_CHIP
1150 config PLAT_ORION_LEGACY
1157 config PLAT_VERSATILE
1160 config ARM_TIMER_SP804
1163 select HAVE_SCHED_CLOCK
1165 source arch/arm/mm/Kconfig
1169 default 16 if ARCH_EP93XX
1173 bool "Enable iWMMXt support"
1174 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1175 default y if PXA27x || PXA3xx || ARCH_MMP
1177 Enable support for iWMMXt context switching at run time if
1178 running on a CPU that supports it.
1182 depends on CPU_XSCALE
1185 config MULTI_IRQ_HANDLER
1188 Allow each machine to specify it's own IRQ handler at run time.
1191 source "arch/arm/Kconfig-nommu"
1194 config ARM_ERRATA_326103
1195 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1198 Executing a SWP instruction to read-only memory does not set bit 11
1199 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1200 treat the access as a read, preventing a COW from occurring and
1201 causing the faulting task to livelock.
1203 config ARM_ERRATA_411920
1204 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1205 depends on CPU_V6 || CPU_V6K
1207 Invalidation of the Instruction Cache operation can
1208 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1209 It does not affect the MPCore. This option enables the ARM Ltd.
1210 recommended workaround.
1212 config ARM_ERRATA_430973
1213 bool "ARM errata: Stale prediction on replaced interworking branch"
1216 This option enables the workaround for the 430973 Cortex-A8
1217 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1218 interworking branch is replaced with another code sequence at the
1219 same virtual address, whether due to self-modifying code or virtual
1220 to physical address re-mapping, Cortex-A8 does not recover from the
1221 stale interworking branch prediction. This results in Cortex-A8
1222 executing the new code sequence in the incorrect ARM or Thumb state.
1223 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1224 and also flushes the branch target cache at every context switch.
1225 Note that setting specific bits in the ACTLR register may not be
1226 available in non-secure mode.
1228 config ARM_ERRATA_458693
1229 bool "ARM errata: Processor deadlock when a false hazard is created"
1231 depends on !ARCH_MULTIPLATFORM
1233 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1234 erratum. For very specific sequences of memory operations, it is
1235 possible for a hazard condition intended for a cache line to instead
1236 be incorrectly associated with a different cache line. This false
1237 hazard might then cause a processor deadlock. The workaround enables
1238 the L1 caching of the NEON accesses and disables the PLD instruction
1239 in the ACTLR register. Note that setting specific bits in the ACTLR
1240 register may not be available in non-secure mode.
1242 config ARM_ERRATA_460075
1243 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1248 erratum. Any asynchronous access to the L2 cache may encounter a
1249 situation in which recent store transactions to the L2 cache are lost
1250 and overwritten with stale memory contents from external memory. The
1251 workaround disables the write-allocate mode for the L2 cache via the
1252 ACTLR register. Note that setting specific bits in the ACTLR register
1253 may not be available in non-secure mode.
1255 config ARM_ERRATA_742230
1256 bool "ARM errata: DMB operation may be faulty"
1257 depends on CPU_V7 && SMP
1258 depends on !ARCH_MULTIPLATFORM
1260 This option enables the workaround for the 742230 Cortex-A9
1261 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1262 between two write operations may not ensure the correct visibility
1263 ordering of the two writes. This workaround sets a specific bit in
1264 the diagnostic register of the Cortex-A9 which causes the DMB
1265 instruction to behave as a DSB, ensuring the correct behaviour of
1268 config ARM_ERRATA_742231
1269 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1270 depends on CPU_V7 && SMP
1271 depends on !ARCH_MULTIPLATFORM
1273 This option enables the workaround for the 742231 Cortex-A9
1274 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1275 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1276 accessing some data located in the same cache line, may get corrupted
1277 data due to bad handling of the address hazard when the line gets
1278 replaced from one of the CPUs at the same time as another CPU is
1279 accessing it. This workaround sets specific bits in the diagnostic
1280 register of the Cortex-A9 which reduces the linefill issuing
1281 capabilities of the processor.
1283 config PL310_ERRATA_588369
1284 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1285 depends on CACHE_L2X0
1287 The PL310 L2 cache controller implements three types of Clean &
1288 Invalidate maintenance operations: by Physical Address
1289 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1290 They are architecturally defined to behave as the execution of a
1291 clean operation followed immediately by an invalidate operation,
1292 both performing to the same memory location. This functionality
1293 is not correctly implemented in PL310 as clean lines are not
1294 invalidated as a result of these operations.
1296 config ARM_ERRATA_720789
1297 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1300 This option enables the workaround for the 720789 Cortex-A9 (prior to
1301 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1302 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1303 As a consequence of this erratum, some TLB entries which should be
1304 invalidated are not, resulting in an incoherency in the system page
1305 tables. The workaround changes the TLB flushing routines to invalidate
1306 entries regardless of the ASID.
1308 config PL310_ERRATA_727915
1309 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1310 depends on CACHE_L2X0
1312 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1313 operation (offset 0x7FC). This operation runs in background so that
1314 PL310 can handle normal accesses while it is in progress. Under very
1315 rare circumstances, due to this erratum, write data can be lost when
1316 PL310 treats a cacheable write transaction during a Clean &
1317 Invalidate by Way operation.
1319 config ARM_ERRATA_743622
1320 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1322 depends on !ARCH_MULTIPLATFORM
1324 This option enables the workaround for the 743622 Cortex-A9
1325 (r2p*) erratum. Under very rare conditions, a faulty
1326 optimisation in the Cortex-A9 Store Buffer may lead to data
1327 corruption. This workaround sets a specific bit in the diagnostic
1328 register of the Cortex-A9 which disables the Store Buffer
1329 optimisation, preventing the defect from occurring. This has no
1330 visible impact on the overall performance or power consumption of the
1333 config ARM_ERRATA_751472
1334 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1336 depends on !ARCH_MULTIPLATFORM
1338 This option enables the workaround for the 751472 Cortex-A9 (prior
1339 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1340 completion of a following broadcasted operation if the second
1341 operation is received by a CPU before the ICIALLUIS has completed,
1342 potentially leading to corrupted entries in the cache or TLB.
1344 config PL310_ERRATA_753970
1345 bool "PL310 errata: cache sync operation may be faulty"
1346 depends on CACHE_PL310
1348 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1350 Under some condition the effect of cache sync operation on
1351 the store buffer still remains when the operation completes.
1352 This means that the store buffer is always asked to drain and
1353 this prevents it from merging any further writes. The workaround
1354 is to replace the normal offset of cache sync operation (0x730)
1355 by another offset targeting an unmapped PL310 register 0x740.
1356 This has the same effect as the cache sync operation: store buffer
1357 drain and waiting for all buffers empty.
1359 config ARM_ERRATA_754322
1360 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1363 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1364 r3p*) erratum. A speculative memory access may cause a page table walk
1365 which starts prior to an ASID switch but completes afterwards. This
1366 can populate the micro-TLB with a stale entry which may be hit with
1367 the new ASID. This workaround places two dsb instructions in the mm
1368 switching code so that no page table walks can cross the ASID switch.
1370 config ARM_ERRATA_754327
1371 bool "ARM errata: no automatic Store Buffer drain"
1372 depends on CPU_V7 && SMP
1374 This option enables the workaround for the 754327 Cortex-A9 (prior to
1375 r2p0) erratum. The Store Buffer does not have any automatic draining
1376 mechanism and therefore a livelock may occur if an external agent
1377 continuously polls a memory location waiting to observe an update.
1378 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1379 written polling loops from denying visibility of updates to memory.
1381 config ARM_ERRATA_364296
1382 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1383 depends on CPU_V6 && !SMP
1385 This options enables the workaround for the 364296 ARM1136
1386 r0p2 erratum (possible cache data corruption with
1387 hit-under-miss enabled). It sets the undocumented bit 31 in
1388 the auxiliary control register and the FI bit in the control
1389 register, thus disabling hit-under-miss without putting the
1390 processor into full low interrupt latency mode. ARM11MPCore
1393 config ARM_ERRATA_764369
1394 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1395 depends on CPU_V7 && SMP
1397 This option enables the workaround for erratum 764369
1398 affecting Cortex-A9 MPCore with two or more processors (all
1399 current revisions). Under certain timing circumstances, a data
1400 cache line maintenance operation by MVA targeting an Inner
1401 Shareable memory region may fail to proceed up to either the
1402 Point of Coherency or to the Point of Unification of the
1403 system. This workaround adds a DSB instruction before the
1404 relevant cache maintenance functions and sets a specific bit
1405 in the diagnostic control register of the SCU.
1407 config PL310_ERRATA_769419
1408 bool "PL310 errata: no automatic Store Buffer drain"
1409 depends on CACHE_L2X0
1411 On revisions of the PL310 prior to r3p2, the Store Buffer does
1412 not automatically drain. This can cause normal, non-cacheable
1413 writes to be retained when the memory system is idle, leading
1414 to suboptimal I/O performance for drivers using coherent DMA.
1415 This option adds a write barrier to the cpu_idle loop so that,
1416 on systems with an outer cache, the store buffer is drained
1419 config ARM_ERRATA_775420
1420 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1423 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1424 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1425 operation aborts with MMU exception, it might cause the processor
1426 to deadlock. This workaround puts DSB before executing ISB if
1427 an abort may occur on cache maintenance.
1431 source "arch/arm/common/Kconfig"
1441 Find out whether you have ISA slots on your motherboard. ISA is the
1442 name of a bus system, i.e. the way the CPU talks to the other stuff
1443 inside your box. Other bus systems are PCI, EISA, MicroChannel
1444 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1445 newer boards don't support it. If you have ISA, say Y, otherwise N.
1447 # Select ISA DMA controller support
1452 # Select ISA DMA interface
1457 bool "PCI support" if MIGHT_HAVE_PCI
1459 Find out whether you have a PCI motherboard. PCI is the name of a
1460 bus system, i.e. the way the CPU talks to the other stuff inside
1461 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1462 VESA. If you have PCI, say Y, otherwise N.
1468 config PCI_NANOENGINE
1469 bool "BSE nanoEngine PCI support"
1470 depends on SA1100_NANOENGINE
1472 Enable PCI on the BSE nanoEngine board.
1477 # Select the host bridge type
1478 config PCI_HOST_VIA82C505
1480 depends on PCI && ARCH_SHARK
1483 config PCI_HOST_ITE8152
1485 depends on PCI && MACH_ARMCORE
1489 source "drivers/pci/Kconfig"
1491 source "drivers/pcmcia/Kconfig"
1495 menu "Kernel Features"
1500 This option should be selected by machines which have an SMP-
1503 The only effect of this option is to make the SMP-related
1504 options available to the user for configuration.
1507 bool "Symmetric Multi-Processing"
1508 depends on CPU_V6K || CPU_V7
1509 depends on GENERIC_CLOCKEVENTS
1512 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1513 select USE_GENERIC_SMP_HELPERS
1515 This enables support for systems with more than one CPU. If you have
1516 a system with only one CPU, like most personal computers, say N. If
1517 you have a system with more than one CPU, say Y.
1519 If you say N here, the kernel will run on single and multiprocessor
1520 machines, but will use only one CPU of a multiprocessor machine. If
1521 you say Y here, the kernel will run on many, but not all, single
1522 processor machines. On a single processor machine, the kernel will
1523 run faster if you say N here.
1525 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1526 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1527 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1529 If you don't know what to do here, say N.
1532 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1533 depends on EXPERIMENTAL
1534 depends on SMP && !XIP_KERNEL
1537 SMP kernels contain instructions which fail on non-SMP processors.
1538 Enabling this option allows the kernel to modify itself to make
1539 these instructions safe. Disabling it allows about 1K of space
1542 If you don't know what to do here, say Y.
1544 config ARM_CPU_TOPOLOGY
1545 bool "Support cpu topology definition"
1546 depends on SMP && CPU_V7
1549 Support ARM cpu topology definition. The MPIDR register defines
1550 affinity between processors which is then used to describe the cpu
1551 topology of an ARM System.
1554 bool "Multi-core scheduler support"
1555 depends on ARM_CPU_TOPOLOGY
1557 Multi-core scheduler support improves the CPU scheduler's decision
1558 making when dealing with multi-core CPU chips at a cost of slightly
1559 increased overhead in some places. If unsure say N here.
1562 bool "SMT scheduler support"
1563 depends on ARM_CPU_TOPOLOGY
1565 Improves the CPU scheduler's decision making when dealing with
1566 MultiThreading at a cost of slightly increased overhead in some
1567 places. If unsure say N here.
1572 This option enables support for the ARM system coherency unit
1574 config ARM_ARCH_TIMER
1575 bool "Architected timer support"
1578 This option enables support for the ARM architected timer
1584 This options enables support for the ARM timer and watchdog unit
1587 prompt "Memory split"
1590 Select the desired split between kernel and user memory.
1592 If you are not absolutely sure what you are doing, leave this
1596 bool "3G/1G user/kernel split"
1598 bool "2G/2G user/kernel split"
1600 bool "1G/3G user/kernel split"
1605 default 0x40000000 if VMSPLIT_1G
1606 default 0x80000000 if VMSPLIT_2G
1610 int "Maximum number of CPUs (2-32)"
1616 bool "Support for hot-pluggable CPUs"
1617 depends on SMP && HOTPLUG
1619 Say Y here to experiment with turning CPUs off and on. CPUs
1620 can be controlled through /sys/devices/system/cpu.
1623 bool "Use local timer interrupts"
1626 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1628 Enable support for local timers on SMP platforms, rather then the
1629 legacy IPI broadcast method. Local timers allows the system
1630 accounting to be spread across the timer interval, preventing a
1631 "thundering herd" at every timer tick.
1635 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1636 default 355 if ARCH_U8500
1637 default 264 if MACH_H4700
1638 default 512 if SOC_OMAP5
1639 default 288 if ARCH_VT8500
1642 Maximum number of GPIOs in the system.
1644 If unsure, leave the default value.
1646 source kernel/Kconfig.preempt
1650 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1651 ARCH_S5PV210 || ARCH_EXYNOS4
1652 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1653 default AT91_TIMER_HZ if ARCH_AT91
1654 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1657 config THUMB2_KERNEL
1658 bool "Compile the kernel in Thumb-2 mode"
1659 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1661 select ARM_ASM_UNIFIED
1664 By enabling this option, the kernel will be compiled in
1665 Thumb-2 mode. A compiler/assembler that understand the unified
1666 ARM-Thumb syntax is needed.
1670 config THUMB2_AVOID_R_ARM_THM_JUMP11
1671 bool "Work around buggy Thumb-2 short branch relocations in gas"
1672 depends on THUMB2_KERNEL && MODULES
1675 Various binutils versions can resolve Thumb-2 branches to
1676 locally-defined, preemptible global symbols as short-range "b.n"
1677 branch instructions.
1679 This is a problem, because there's no guarantee the final
1680 destination of the symbol, or any candidate locations for a
1681 trampoline, are within range of the branch. For this reason, the
1682 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1683 relocation in modules at all, and it makes little sense to add
1686 The symptom is that the kernel fails with an "unsupported
1687 relocation" error when loading some modules.
1689 Until fixed tools are available, passing
1690 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1691 code which hits this problem, at the cost of a bit of extra runtime
1692 stack usage in some cases.
1694 The problem is described in more detail at:
1695 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1697 Only Thumb-2 kernels are affected.
1699 Unless you are sure your tools don't have this problem, say Y.
1701 config ARM_ASM_UNIFIED
1705 bool "Use the ARM EABI to compile the kernel"
1707 This option allows for the kernel to be compiled using the latest
1708 ARM ABI (aka EABI). This is only useful if you are using a user
1709 space environment that is also compiled with EABI.
1711 Since there are major incompatibilities between the legacy ABI and
1712 EABI, especially with regard to structure member alignment, this
1713 option also changes the kernel syscall calling convention to
1714 disambiguate both ABIs and allow for backward compatibility support
1715 (selected with CONFIG_OABI_COMPAT).
1717 To use this you need GCC version 4.0.0 or later.
1720 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1721 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1724 This option preserves the old syscall interface along with the
1725 new (ARM EABI) one. It also provides a compatibility layer to
1726 intercept syscalls that have structure arguments which layout
1727 in memory differs between the legacy ABI and the new ARM EABI
1728 (only for non "thumb" binaries). This option adds a tiny
1729 overhead to all syscalls and produces a slightly larger kernel.
1730 If you know you'll be using only pure EABI user space then you
1731 can say N here. If this option is not selected and you attempt
1732 to execute a legacy ABI binary then the result will be
1733 UNPREDICTABLE (in fact it can be predicted that it won't work
1734 at all). If in doubt say Y.
1736 config ARCH_HAS_HOLES_MEMORYMODEL
1739 config ARCH_SPARSEMEM_ENABLE
1742 config ARCH_SPARSEMEM_DEFAULT
1743 def_bool ARCH_SPARSEMEM_ENABLE
1745 config ARCH_SELECT_MEMORY_MODEL
1746 def_bool ARCH_SPARSEMEM_ENABLE
1748 config HAVE_ARCH_PFN_VALID
1749 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1752 bool "High Memory Support"
1755 The address space of ARM processors is only 4 Gigabytes large
1756 and it has to accommodate user address space, kernel address
1757 space as well as some memory mapped IO. That means that, if you
1758 have a large amount of physical memory and/or IO, not all of the
1759 memory can be "permanently mapped" by the kernel. The physical
1760 memory that is not permanently mapped is called "high memory".
1762 Depending on the selected kernel/user memory split, minimum
1763 vmalloc space and actual amount of RAM, you may not need this
1764 option which should result in a slightly faster kernel.
1769 bool "Allocate 2nd-level pagetables from highmem"
1772 config HW_PERF_EVENTS
1773 bool "Enable hardware performance counter support for perf events"
1774 depends on PERF_EVENTS
1777 Enable hardware performance counter support for perf events. If
1778 disabled, perf events will use software events only.
1782 config FORCE_MAX_ZONEORDER
1783 int "Maximum zone order" if ARCH_SHMOBILE
1784 range 11 64 if ARCH_SHMOBILE
1785 default "12" if SOC_AM33XX
1786 default "9" if SA1111
1789 The kernel memory allocator divides physically contiguous memory
1790 blocks into "zones", where each zone is a power of two number of
1791 pages. This option selects the largest power of two that the kernel
1792 keeps in the memory allocator. If you need to allocate very large
1793 blocks of physically contiguous memory, then you may need to
1794 increase this value.
1796 This config option is actually maximum order plus one. For example,
1797 a value of 11 means that the largest free memory block is 2^10 pages.
1799 config ALIGNMENT_TRAP
1801 depends on CPU_CP15_MMU
1802 default y if !ARCH_EBSA110
1803 select HAVE_PROC_CPU if PROC_FS
1805 ARM processors cannot fetch/store information which is not
1806 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1807 address divisible by 4. On 32-bit ARM processors, these non-aligned
1808 fetch/store instructions will be emulated in software if you say
1809 here, which has a severe performance impact. This is necessary for
1810 correct operation of some network protocols. With an IP-only
1811 configuration it is safe to say N, otherwise say Y.
1813 config UACCESS_WITH_MEMCPY
1814 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1816 default y if CPU_FEROCEON
1818 Implement faster copy_to_user and clear_user methods for CPU
1819 cores where a 8-word STM instruction give significantly higher
1820 memory write throughput than a sequence of individual 32bit stores.
1822 A possible side effect is a slight increase in scheduling latency
1823 between threads sharing the same address space if they invoke
1824 such copy operations with large buffers.
1826 However, if the CPU data cache is using a write-allocate mode,
1827 this option is unlikely to provide any performance gain.
1831 prompt "Enable seccomp to safely compute untrusted bytecode"
1833 This kernel feature is useful for number crunching applications
1834 that may need to compute untrusted bytecode during their
1835 execution. By using pipes or other transports made available to
1836 the process as file descriptors supporting the read/write
1837 syscalls, it's possible to isolate those applications in
1838 their own address space using seccomp. Once seccomp is
1839 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1840 and the task is only allowed to execute a few safe syscalls
1841 defined by each seccomp mode.
1843 config CC_STACKPROTECTOR
1844 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1845 depends on EXPERIMENTAL
1847 This option turns on the -fstack-protector GCC feature. This
1848 feature puts, at the beginning of functions, a canary value on
1849 the stack just before the return address, and validates
1850 the value just before actually returning. Stack based buffer
1851 overflows (that need to overwrite this return address) now also
1852 overwrite the canary, which gets detected and the attack is then
1853 neutralized via a kernel panic.
1854 This feature requires gcc version 4.2 or above.
1861 bool "Xen guest support on ARM (EXPERIMENTAL)"
1862 depends on EXPERIMENTAL && ARM && OF
1863 depends on CPU_V7 && !CPU_V6
1865 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1872 bool "Flattened Device Tree support"
1875 select OF_EARLY_FLATTREE
1877 Include support for flattened device tree machine descriptions.
1880 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1883 This is the traditional way of passing data to the kernel at boot
1884 time. If you are solely relying on the flattened device tree (or
1885 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1886 to remove ATAGS support from your kernel binary. If unsure,
1889 config DEPRECATED_PARAM_STRUCT
1890 bool "Provide old way to pass kernel parameters"
1893 This was deprecated in 2001 and announced to live on for 5 years.
1894 Some old boot loaders still use this way.
1896 # Compressed boot loader in ROM. Yes, we really want to ask about
1897 # TEXT and BSS so we preserve their values in the config files.
1898 config ZBOOT_ROM_TEXT
1899 hex "Compressed ROM boot loader base address"
1902 The physical address at which the ROM-able zImage is to be
1903 placed in the target. Platforms which normally make use of
1904 ROM-able zImage formats normally set this to a suitable
1905 value in their defconfig file.
1907 If ZBOOT_ROM is not enabled, this has no effect.
1909 config ZBOOT_ROM_BSS
1910 hex "Compressed ROM boot loader BSS address"
1913 The base address of an area of read/write memory in the target
1914 for the ROM-able zImage which must be available while the
1915 decompressor is running. It must be large enough to hold the
1916 entire decompressed kernel plus an additional 128 KiB.
1917 Platforms which normally make use of ROM-able zImage formats
1918 normally set this to a suitable value in their defconfig file.
1920 If ZBOOT_ROM is not enabled, this has no effect.
1923 bool "Compressed boot loader in ROM/flash"
1924 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1926 Say Y here if you intend to execute your compressed kernel image
1927 (zImage) directly from ROM or flash. If unsure, say N.
1930 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1931 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1932 default ZBOOT_ROM_NONE
1934 Include experimental SD/MMC loading code in the ROM-able zImage.
1935 With this enabled it is possible to write the ROM-able zImage
1936 kernel image to an MMC or SD card and boot the kernel straight
1937 from the reset vector. At reset the processor Mask ROM will load
1938 the first part of the ROM-able zImage which in turn loads the
1939 rest the kernel image to RAM.
1941 config ZBOOT_ROM_NONE
1942 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1944 Do not load image from SD or MMC
1946 config ZBOOT_ROM_MMCIF
1947 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1949 Load image from MMCIF hardware block.
1951 config ZBOOT_ROM_SH_MOBILE_SDHI
1952 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1954 Load image from SDHI hardware block
1958 config ARM_APPENDED_DTB
1959 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1960 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1962 With this option, the boot code will look for a device tree binary
1963 (DTB) appended to zImage
1964 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1966 This is meant as a backward compatibility convenience for those
1967 systems with a bootloader that can't be upgraded to accommodate
1968 the documented boot protocol using a device tree.
1970 Beware that there is very little in terms of protection against
1971 this option being confused by leftover garbage in memory that might
1972 look like a DTB header after a reboot if no actual DTB is appended
1973 to zImage. Do not leave this option active in a production kernel
1974 if you don't intend to always append a DTB. Proper passing of the
1975 location into r2 of a bootloader provided DTB is always preferable
1978 config ARM_ATAG_DTB_COMPAT
1979 bool "Supplement the appended DTB with traditional ATAG information"
1980 depends on ARM_APPENDED_DTB
1982 Some old bootloaders can't be updated to a DTB capable one, yet
1983 they provide ATAGs with memory configuration, the ramdisk address,
1984 the kernel cmdline string, etc. Such information is dynamically
1985 provided by the bootloader and can't always be stored in a static
1986 DTB. To allow a device tree enabled kernel to be used with such
1987 bootloaders, this option allows zImage to extract the information
1988 from the ATAG list and store it at run time into the appended DTB.
1991 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1992 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1994 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1995 bool "Use bootloader kernel arguments if available"
1997 Uses the command-line options passed by the boot loader instead of
1998 the device tree bootargs property. If the boot loader doesn't provide
1999 any, the device tree bootargs property will be used.
2001 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2002 bool "Extend with bootloader kernel arguments"
2004 The command-line arguments provided by the boot loader will be
2005 appended to the the device tree bootargs property.
2010 string "Default kernel command string"
2013 On some architectures (EBSA110 and CATS), there is currently no way
2014 for the boot loader to pass arguments to the kernel. For these
2015 architectures, you should supply some command-line options at build
2016 time by entering them here. As a minimum, you should specify the
2017 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2020 prompt "Kernel command line type" if CMDLINE != ""
2021 default CMDLINE_FROM_BOOTLOADER
2024 config CMDLINE_FROM_BOOTLOADER
2025 bool "Use bootloader kernel arguments if available"
2027 Uses the command-line options passed by the boot loader. If
2028 the boot loader doesn't provide any, the default kernel command
2029 string provided in CMDLINE will be used.
2031 config CMDLINE_EXTEND
2032 bool "Extend bootloader kernel arguments"
2034 The command-line arguments provided by the boot loader will be
2035 appended to the default kernel command string.
2037 config CMDLINE_FORCE
2038 bool "Always use the default kernel command string"
2040 Always use the default kernel command string, even if the boot
2041 loader passes other arguments to the kernel.
2042 This is useful if you cannot or don't want to change the
2043 command-line options your boot loader passes to the kernel.
2047 bool "Kernel Execute-In-Place from ROM"
2048 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2050 Execute-In-Place allows the kernel to run from non-volatile storage
2051 directly addressable by the CPU, such as NOR flash. This saves RAM
2052 space since the text section of the kernel is not loaded from flash
2053 to RAM. Read-write sections, such as the data section and stack,
2054 are still copied to RAM. The XIP kernel is not compressed since
2055 it has to run directly from flash, so it will take more space to
2056 store it. The flash address used to link the kernel object files,
2057 and for storing it, is configuration dependent. Therefore, if you
2058 say Y here, you must know the proper physical address where to
2059 store the kernel image depending on your own flash memory usage.
2061 Also note that the make target becomes "make xipImage" rather than
2062 "make zImage" or "make Image". The final kernel binary to put in
2063 ROM memory will be arch/arm/boot/xipImage.
2067 config XIP_PHYS_ADDR
2068 hex "XIP Kernel Physical Location"
2069 depends on XIP_KERNEL
2070 default "0x00080000"
2072 This is the physical address in your flash memory the kernel will
2073 be linked for and stored to. This address is dependent on your
2077 bool "Kexec system call (EXPERIMENTAL)"
2078 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2080 kexec is a system call that implements the ability to shutdown your
2081 current kernel, and to start another kernel. It is like a reboot
2082 but it is independent of the system firmware. And like a reboot
2083 you can start any kernel with it, not just Linux.
2085 It is an ongoing process to be certain the hardware in a machine
2086 is properly shutdown, so do not be surprised if this code does not
2087 initially work for you. It may help to enable device hotplugging
2091 bool "Export atags in procfs"
2092 depends on ATAGS && KEXEC
2095 Should the atags used to boot the kernel be exported in an "atags"
2096 file in procfs. Useful with kexec.
2099 bool "Build kdump crash kernel (EXPERIMENTAL)"
2100 depends on EXPERIMENTAL
2102 Generate crash dump after being started by kexec. This should
2103 be normally only set in special crash dump kernels which are
2104 loaded in the main kernel with kexec-tools into a specially
2105 reserved region and then later executed after a crash by
2106 kdump/kexec. The crash dump kernel must be compiled to a
2107 memory address not used by the main kernel
2109 For more details see Documentation/kdump/kdump.txt
2111 config AUTO_ZRELADDR
2112 bool "Auto calculation of the decompressed kernel image address"
2113 depends on !ZBOOT_ROM && !ARCH_U300
2115 ZRELADDR is the physical address where the decompressed kernel
2116 image will be placed. If AUTO_ZRELADDR is selected, the address
2117 will be determined at run-time by masking the current IP with
2118 0xf8000000. This assumes the zImage being placed in the first 128MB
2119 from start of memory.
2123 menu "CPU Power Management"
2127 source "drivers/cpufreq/Kconfig"
2130 tristate "CPUfreq driver for i.MX CPUs"
2131 depends on ARCH_MXC && CPU_FREQ
2132 select CPU_FREQ_TABLE
2134 This enables the CPUfreq driver for i.MX CPUs.
2136 config CPU_FREQ_SA1100
2139 config CPU_FREQ_SA1110
2142 config CPU_FREQ_INTEGRATOR
2143 tristate "CPUfreq driver for ARM Integrator CPUs"
2144 depends on ARCH_INTEGRATOR && CPU_FREQ
2147 This enables the CPUfreq driver for ARM Integrator CPUs.
2149 For details, take a look at <file:Documentation/cpu-freq>.
2155 depends on CPU_FREQ && ARCH_PXA && PXA25x
2157 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2158 select CPU_FREQ_TABLE
2163 Internal configuration node for common cpufreq on Samsung SoC
2165 config CPU_FREQ_S3C24XX
2166 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2167 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2170 This enables the CPUfreq driver for the Samsung S3C24XX family
2173 For details, take a look at <file:Documentation/cpu-freq>.
2177 config CPU_FREQ_S3C24XX_PLL
2178 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2179 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2181 Compile in support for changing the PLL frequency from the
2182 S3C24XX series CPUfreq driver. The PLL takes time to settle
2183 after a frequency change, so by default it is not enabled.
2185 This also means that the PLL tables for the selected CPU(s) will
2186 be built which may increase the size of the kernel image.
2188 config CPU_FREQ_S3C24XX_DEBUG
2189 bool "Debug CPUfreq Samsung driver core"
2190 depends on CPU_FREQ_S3C24XX
2192 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2194 config CPU_FREQ_S3C24XX_IODEBUG
2195 bool "Debug CPUfreq Samsung driver IO timing"
2196 depends on CPU_FREQ_S3C24XX
2198 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2200 config CPU_FREQ_S3C24XX_DEBUGFS
2201 bool "Export debugfs for CPUFreq"
2202 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2204 Export status information via debugfs.
2208 source "drivers/cpuidle/Kconfig"
2212 menu "Floating point emulation"
2214 comment "At least one emulation must be selected"
2217 bool "NWFPE math emulation"
2218 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2220 Say Y to include the NWFPE floating point emulator in the kernel.
2221 This is necessary to run most binaries. Linux does not currently
2222 support floating point hardware so you need to say Y here even if
2223 your machine has an FPA or floating point co-processor podule.
2225 You may say N here if you are going to load the Acorn FPEmulator
2226 early in the bootup.
2229 bool "Support extended precision"
2230 depends on FPE_NWFPE
2232 Say Y to include 80-bit support in the kernel floating-point
2233 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2234 Note that gcc does not generate 80-bit operations by default,
2235 so in most cases this option only enlarges the size of the
2236 floating point emulator without any good reason.
2238 You almost surely want to say N here.
2241 bool "FastFPE math emulation (EXPERIMENTAL)"
2242 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2244 Say Y here to include the FAST floating point emulator in the kernel.
2245 This is an experimental much faster emulator which now also has full
2246 precision for the mantissa. It does not support any exceptions.
2247 It is very simple, and approximately 3-6 times faster than NWFPE.
2249 It should be sufficient for most programs. It may be not suitable
2250 for scientific calculations, but you have to check this for yourself.
2251 If you do not feel you need a faster FP emulation you should better
2255 bool "VFP-format floating point maths"
2256 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2258 Say Y to include VFP support code in the kernel. This is needed
2259 if your hardware includes a VFP unit.
2261 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2262 release notes and additional status information.
2264 Say N if your target does not have VFP hardware.
2272 bool "Advanced SIMD (NEON) Extension support"
2273 depends on VFPv3 && CPU_V7
2275 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2280 menu "Userspace binary formats"
2282 source "fs/Kconfig.binfmt"
2285 tristate "RISC OS personality"
2288 Say Y here to include the kernel code necessary if you want to run
2289 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2290 experimental; if this sounds frightening, say N and sleep in peace.
2291 You can also say M here to compile this support as a module (which
2292 will be called arthur).
2296 menu "Power management options"
2298 source "kernel/power/Kconfig"
2300 config ARCH_SUSPEND_POSSIBLE
2301 depends on !ARCH_S5PC100
2302 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2303 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2306 config ARM_CPU_SUSPEND
2311 source "net/Kconfig"
2313 source "drivers/Kconfig"
2317 source "arch/arm/Kconfig.debug"
2319 source "security/Kconfig"
2321 source "crypto/Kconfig"
2323 source "lib/Kconfig"