4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 select ARCH_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT
260 default DRAM_BASE if !MMU
261 default 0x00000000 if ARCH_EBSA110 || \
262 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
267 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210
270 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
271 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
272 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
273 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
274 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 source "init/Kconfig"
285 source "kernel/Kconfig.freezer"
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text. Please add new entries in the option alphabetic order.
301 prompt "ARM system type"
302 default ARCH_VERSATILE if !MMU
303 default ARCH_MULTIPLATFORM if MMU
305 config ARCH_MULTIPLATFORM
306 bool "Allow multiple platforms to be selected"
308 select ARCH_WANT_OPTIONAL_GPIOLIB
309 select ARM_HAS_SG_CHAIN
310 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MIGHT_HAVE_PCI
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
323 select ARM_PATCH_PHYS_VIRT if MMU
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select PLAT_VERSATILE
334 select VERSATILE_FPGA_IRQ
336 Support for ARM's Integrator platform.
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
351 This enables support for ARM Ltd RealView boards.
353 config ARCH_VERSATILE
354 bool "ARM Ltd. Versatile family"
355 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_TIMER_SP804
360 select GENERIC_CLOCKEVENTS
361 select HAVE_MACH_CLKDEV
363 select PLAT_VERSATILE
364 select PLAT_VERSATILE_CLOCK
365 select VERSATILE_FPGA_IRQ
367 This enables support for ARM Ltd Versatile board.
371 select ARCH_REQUIRE_GPIOLIB
374 select NEED_MACH_IO_H if PCCARD
376 select PINCTRL_AT91 if USE_OF
378 This enables support for systems based on Atmel
379 AT91RM9200 and AT91SAM9* processors.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cortina Systems Gemini"
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
400 Support for the Cortina Systems Gemini family SoCs
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 bool "Energy Micro efm32"
419 select ARCH_REQUIRE_GPIOLIB
425 select GENERIC_CLOCKEVENTS
431 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_REQUIRE_GPIOLIB
438 select ARCH_USES_GETTIMEOFFSET
444 This enables support for the Cirrus EP93xx series of CPUs.
446 config ARCH_FOOTBRIDGE
450 select GENERIC_CLOCKEVENTS
452 select NEED_MACH_IO_H if !MMU
453 select NEED_MACH_MEMORY_H
455 Support for systems based on the DC21285 companion chip
456 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
459 bool "Hilscher NetX based"
463 select GENERIC_CLOCKEVENTS
465 This enables support for systems based on the Hilscher NetX Soc
471 select NEED_MACH_MEMORY_H
472 select NEED_RET_TO_USER
478 Support for Intel's IOP13XX (XScale) family of processors.
483 select ARCH_REQUIRE_GPIOLIB
486 select NEED_RET_TO_USER
490 Support for Intel's 80219 and IOP32X (XScale) family of
496 select ARCH_REQUIRE_GPIOLIB
499 select NEED_RET_TO_USER
503 Support for Intel's IOP33X (XScale) family of processors.
508 select ARCH_HAS_DMA_SET_COHERENT_MASK
509 select ARCH_REQUIRE_GPIOLIB
510 select ARCH_SUPPORTS_BIG_ENDIAN
513 select DMABOUNCE if PCI
514 select GENERIC_CLOCKEVENTS
515 select MIGHT_HAVE_PCI
516 select NEED_MACH_IO_H
517 select USB_EHCI_BIG_ENDIAN_DESC
518 select USB_EHCI_BIG_ENDIAN_MMIO
520 Support for Intel's IXP4XX (XScale) family of processors.
524 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
531 select PLAT_ORION_LEGACY
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell MV78xx0"
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
542 select PLAT_ORION_LEGACY
544 Support for the following Marvell MV78xx0 series SoCs:
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Orion 5x series SoCs:
558 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
559 Orion-2 (5281), Orion-1-90 (6183).
562 bool "Marvell PXA168/910/MMP2"
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_ALLOCATOR
567 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
575 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
578 bool "Micrel/Kendin KS8695"
579 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_MEMORY_H
585 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586 System-on-Chip devices.
589 bool "Nuvoton W90X900 CPU"
590 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
596 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
597 At present, the w90x900 has been renamed nuc900, regarding
598 the ARM series product line, you can login the following
599 link address to know more.
601 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
602 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
606 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_CLOCKEVENTS
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
627 select GENERIC_CLOCKEVENTS
630 select MULTI_IRQ_HANDLER
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
637 bool "Qualcomm MSM (non-multiplatform)"
638 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
648 config ARCH_SHMOBILE_LEGACY
649 bool "Renesas ARM SoCs (non-multiplatform)"
651 select ARM_PATCH_PHYS_VIRT if MMU
654 select GENERIC_CLOCKEVENTS
655 select HAVE_ARM_SCU if SMP
656 select HAVE_ARM_TWD if SMP
657 select HAVE_MACH_CLKDEV
659 select MIGHT_HAVE_CACHE_L2X0
660 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
666 Support for Renesas ARM SoC platforms using a non-multiplatform
667 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
673 select ARCH_MAY_HAVE_PC_FDC
674 select ARCH_SPARSEMEM_ENABLE
675 select ARCH_USES_GETTIMEOFFSET
679 select HAVE_PATA_PLATFORM
681 select NEED_MACH_IO_H
682 select NEED_MACH_MEMORY_H
686 On the Acorn Risc-PC, Linux can support the internal IDE disk and
687 CD-ROM interface, serial and parallel port, and the floppy drive.
692 select ARCH_REQUIRE_GPIOLIB
693 select ARCH_SPARSEMEM_ENABLE
698 select GENERIC_CLOCKEVENTS
701 select NEED_MACH_MEMORY_H
704 Support for StrongARM 11x0 based boards.
707 bool "Samsung S3C24XX SoCs"
708 select ARCH_REQUIRE_GPIOLIB
711 select CLKSRC_SAMSUNG_PWM
712 select GENERIC_CLOCKEVENTS
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
716 select HAVE_S3C_RTC if RTC_CLASS
717 select MULTI_IRQ_HANDLER
718 select NEED_MACH_IO_H
721 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
722 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
723 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
724 Samsung SMDK2410 development board (and derivatives).
727 bool "Samsung S3C64XX"
728 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select COMMON_CLK_SAMSUNG
736 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
743 select PM_GENERIC_DOMAINS if PM
745 select S3C_GPIO_TRACK
747 select SAMSUNG_WAKEMASK
748 select SAMSUNG_WDT_RESET
750 Samsung S3C64XX series based systems
754 select ARCH_HAS_HOLES_MEMORYMODEL
755 select ARCH_REQUIRE_GPIOLIB
757 select GENERIC_ALLOCATOR
758 select GENERIC_CLOCKEVENTS
759 select GENERIC_IRQ_CHIP
765 Support for TI's DaVinci platform.
770 select ARCH_HAS_HOLES_MEMORYMODEL
772 select ARCH_REQUIRE_GPIOLIB
775 select GENERIC_CLOCKEVENTS
776 select GENERIC_IRQ_CHIP
779 select NEED_MACH_IO_H if PCCARD
780 select NEED_MACH_MEMORY_H
782 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
786 menu "Multiple platform selection"
787 depends on ARCH_MULTIPLATFORM
789 comment "CPU Core family selection"
792 bool "ARMv4 based platforms (FA526)"
793 depends on !ARCH_MULTI_V6_V7
794 select ARCH_MULTI_V4_V5
797 config ARCH_MULTI_V4T
798 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
799 depends on !ARCH_MULTI_V6_V7
800 select ARCH_MULTI_V4_V5
801 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
802 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
803 CPU_ARM925T || CPU_ARM940T)
806 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
807 depends on !ARCH_MULTI_V6_V7
808 select ARCH_MULTI_V4_V5
809 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
810 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
811 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
813 config ARCH_MULTI_V4_V5
817 bool "ARMv6 based platforms (ARM11)"
818 select ARCH_MULTI_V6_V7
822 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
824 select ARCH_MULTI_V6_V7
828 config ARCH_MULTI_V6_V7
830 select MIGHT_HAVE_CACHE_L2X0
832 config ARCH_MULTI_CPU_AUTO
833 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
839 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
843 select HAVE_ARM_ARCH_TIMER
846 # This is sorted alphabetically by mach-* pathname. However, plat-*
847 # Kconfigs may be included either alphabetically (according to the
848 # plat- suffix) or along side the corresponding mach-* source.
850 source "arch/arm/mach-mvebu/Kconfig"
852 source "arch/arm/mach-at91/Kconfig"
854 source "arch/arm/mach-axxia/Kconfig"
856 source "arch/arm/mach-bcm/Kconfig"
858 source "arch/arm/mach-berlin/Kconfig"
860 source "arch/arm/mach-clps711x/Kconfig"
862 source "arch/arm/mach-cns3xxx/Kconfig"
864 source "arch/arm/mach-davinci/Kconfig"
866 source "arch/arm/mach-dove/Kconfig"
868 source "arch/arm/mach-ep93xx/Kconfig"
870 source "arch/arm/mach-footbridge/Kconfig"
872 source "arch/arm/mach-gemini/Kconfig"
874 source "arch/arm/mach-highbank/Kconfig"
876 source "arch/arm/mach-hisi/Kconfig"
878 source "arch/arm/mach-integrator/Kconfig"
880 source "arch/arm/mach-iop32x/Kconfig"
882 source "arch/arm/mach-iop33x/Kconfig"
884 source "arch/arm/mach-iop13xx/Kconfig"
886 source "arch/arm/mach-ixp4xx/Kconfig"
888 source "arch/arm/mach-keystone/Kconfig"
890 source "arch/arm/mach-ks8695/Kconfig"
892 source "arch/arm/mach-msm/Kconfig"
894 source "arch/arm/mach-moxart/Kconfig"
896 source "arch/arm/mach-mv78xx0/Kconfig"
898 source "arch/arm/mach-imx/Kconfig"
900 source "arch/arm/mach-mediatek/Kconfig"
902 source "arch/arm/mach-mxs/Kconfig"
904 source "arch/arm/mach-netx/Kconfig"
906 source "arch/arm/mach-nomadik/Kconfig"
908 source "arch/arm/mach-nspire/Kconfig"
910 source "arch/arm/plat-omap/Kconfig"
912 source "arch/arm/mach-omap1/Kconfig"
914 source "arch/arm/mach-omap2/Kconfig"
916 source "arch/arm/mach-orion5x/Kconfig"
918 source "arch/arm/mach-picoxcell/Kconfig"
920 source "arch/arm/mach-pxa/Kconfig"
921 source "arch/arm/plat-pxa/Kconfig"
923 source "arch/arm/mach-mmp/Kconfig"
925 source "arch/arm/mach-qcom/Kconfig"
927 source "arch/arm/mach-realview/Kconfig"
929 source "arch/arm/mach-rockchip/Kconfig"
931 source "arch/arm/mach-sa1100/Kconfig"
933 source "arch/arm/mach-socfpga/Kconfig"
935 source "arch/arm/mach-spear/Kconfig"
937 source "arch/arm/mach-sti/Kconfig"
939 source "arch/arm/mach-s3c24xx/Kconfig"
941 source "arch/arm/mach-s3c64xx/Kconfig"
943 source "arch/arm/mach-s5pv210/Kconfig"
945 source "arch/arm/mach-exynos/Kconfig"
946 source "arch/arm/plat-samsung/Kconfig"
948 source "arch/arm/mach-shmobile/Kconfig"
950 source "arch/arm/mach-sunxi/Kconfig"
952 source "arch/arm/mach-prima2/Kconfig"
954 source "arch/arm/mach-tegra/Kconfig"
956 source "arch/arm/mach-u300/Kconfig"
958 source "arch/arm/mach-ux500/Kconfig"
960 source "arch/arm/mach-versatile/Kconfig"
962 source "arch/arm/mach-vexpress/Kconfig"
963 source "arch/arm/plat-versatile/Kconfig"
965 source "arch/arm/mach-vt8500/Kconfig"
967 source "arch/arm/mach-w90x900/Kconfig"
969 source "arch/arm/mach-zynq/Kconfig"
971 # Definitions to make life easier
977 select GENERIC_CLOCKEVENTS
983 select GENERIC_IRQ_CHIP
986 config PLAT_ORION_LEGACY
993 config PLAT_VERSATILE
996 config ARM_TIMER_SP804
999 select CLKSRC_OF if OF
1001 source "arch/arm/firmware/Kconfig"
1003 source arch/arm/mm/Kconfig
1006 bool "Enable iWMMXt support"
1007 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1008 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1010 Enable support for iWMMXt context switching at run time if
1011 running on a CPU that supports it.
1013 config MULTI_IRQ_HANDLER
1016 Allow each machine to specify it's own IRQ handler at run time.
1019 source "arch/arm/Kconfig-nommu"
1022 config PJ4B_ERRATA_4742
1023 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1024 depends on CPU_PJ4B && MACH_ARMADA_370
1027 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1028 Event (WFE) IDLE states, a specific timing sensitivity exists between
1029 the retiring WFI/WFE instructions and the newly issued subsequent
1030 instructions. This sensitivity can result in a CPU hang scenario.
1032 The software must insert either a Data Synchronization Barrier (DSB)
1033 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1036 config ARM_ERRATA_326103
1037 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1040 Executing a SWP instruction to read-only memory does not set bit 11
1041 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1042 treat the access as a read, preventing a COW from occurring and
1043 causing the faulting task to livelock.
1045 config ARM_ERRATA_411920
1046 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1047 depends on CPU_V6 || CPU_V6K
1049 Invalidation of the Instruction Cache operation can
1050 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1051 It does not affect the MPCore. This option enables the ARM Ltd.
1052 recommended workaround.
1054 config ARM_ERRATA_430973
1055 bool "ARM errata: Stale prediction on replaced interworking branch"
1058 This option enables the workaround for the 430973 Cortex-A8
1059 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1060 interworking branch is replaced with another code sequence at the
1061 same virtual address, whether due to self-modifying code or virtual
1062 to physical address re-mapping, Cortex-A8 does not recover from the
1063 stale interworking branch prediction. This results in Cortex-A8
1064 executing the new code sequence in the incorrect ARM or Thumb state.
1065 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1066 and also flushes the branch target cache at every context switch.
1067 Note that setting specific bits in the ACTLR register may not be
1068 available in non-secure mode.
1070 config ARM_ERRATA_458693
1071 bool "ARM errata: Processor deadlock when a false hazard is created"
1073 depends on !ARCH_MULTIPLATFORM
1075 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1076 erratum. For very specific sequences of memory operations, it is
1077 possible for a hazard condition intended for a cache line to instead
1078 be incorrectly associated with a different cache line. This false
1079 hazard might then cause a processor deadlock. The workaround enables
1080 the L1 caching of the NEON accesses and disables the PLD instruction
1081 in the ACTLR register. Note that setting specific bits in the ACTLR
1082 register may not be available in non-secure mode.
1084 config ARM_ERRATA_460075
1085 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1087 depends on !ARCH_MULTIPLATFORM
1089 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1090 erratum. Any asynchronous access to the L2 cache may encounter a
1091 situation in which recent store transactions to the L2 cache are lost
1092 and overwritten with stale memory contents from external memory. The
1093 workaround disables the write-allocate mode for the L2 cache via the
1094 ACTLR register. Note that setting specific bits in the ACTLR register
1095 may not be available in non-secure mode.
1097 config ARM_ERRATA_742230
1098 bool "ARM errata: DMB operation may be faulty"
1099 depends on CPU_V7 && SMP
1100 depends on !ARCH_MULTIPLATFORM
1102 This option enables the workaround for the 742230 Cortex-A9
1103 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1104 between two write operations may not ensure the correct visibility
1105 ordering of the two writes. This workaround sets a specific bit in
1106 the diagnostic register of the Cortex-A9 which causes the DMB
1107 instruction to behave as a DSB, ensuring the correct behaviour of
1110 config ARM_ERRATA_742231
1111 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1112 depends on CPU_V7 && SMP
1113 depends on !ARCH_MULTIPLATFORM
1115 This option enables the workaround for the 742231 Cortex-A9
1116 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1117 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1118 accessing some data located in the same cache line, may get corrupted
1119 data due to bad handling of the address hazard when the line gets
1120 replaced from one of the CPUs at the same time as another CPU is
1121 accessing it. This workaround sets specific bits in the diagnostic
1122 register of the Cortex-A9 which reduces the linefill issuing
1123 capabilities of the processor.
1125 config ARM_ERRATA_643719
1126 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1127 depends on CPU_V7 && SMP
1129 This option enables the workaround for the 643719 Cortex-A9 (prior to
1130 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1131 register returns zero when it should return one. The workaround
1132 corrects this value, ensuring cache maintenance operations which use
1133 it behave as intended and avoiding data corruption.
1135 config ARM_ERRATA_720789
1136 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1139 This option enables the workaround for the 720789 Cortex-A9 (prior to
1140 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1141 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1142 As a consequence of this erratum, some TLB entries which should be
1143 invalidated are not, resulting in an incoherency in the system page
1144 tables. The workaround changes the TLB flushing routines to invalidate
1145 entries regardless of the ASID.
1147 config ARM_ERRATA_743622
1148 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1150 depends on !ARCH_MULTIPLATFORM
1152 This option enables the workaround for the 743622 Cortex-A9
1153 (r2p*) erratum. Under very rare conditions, a faulty
1154 optimisation in the Cortex-A9 Store Buffer may lead to data
1155 corruption. This workaround sets a specific bit in the diagnostic
1156 register of the Cortex-A9 which disables the Store Buffer
1157 optimisation, preventing the defect from occurring. This has no
1158 visible impact on the overall performance or power consumption of the
1161 config ARM_ERRATA_751472
1162 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1164 depends on !ARCH_MULTIPLATFORM
1166 This option enables the workaround for the 751472 Cortex-A9 (prior
1167 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1168 completion of a following broadcasted operation if the second
1169 operation is received by a CPU before the ICIALLUIS has completed,
1170 potentially leading to corrupted entries in the cache or TLB.
1172 config ARM_ERRATA_754322
1173 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1176 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1177 r3p*) erratum. A speculative memory access may cause a page table walk
1178 which starts prior to an ASID switch but completes afterwards. This
1179 can populate the micro-TLB with a stale entry which may be hit with
1180 the new ASID. This workaround places two dsb instructions in the mm
1181 switching code so that no page table walks can cross the ASID switch.
1183 config ARM_ERRATA_754327
1184 bool "ARM errata: no automatic Store Buffer drain"
1185 depends on CPU_V7 && SMP
1187 This option enables the workaround for the 754327 Cortex-A9 (prior to
1188 r2p0) erratum. The Store Buffer does not have any automatic draining
1189 mechanism and therefore a livelock may occur if an external agent
1190 continuously polls a memory location waiting to observe an update.
1191 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1192 written polling loops from denying visibility of updates to memory.
1194 config ARM_ERRATA_364296
1195 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1198 This options enables the workaround for the 364296 ARM1136
1199 r0p2 erratum (possible cache data corruption with
1200 hit-under-miss enabled). It sets the undocumented bit 31 in
1201 the auxiliary control register and the FI bit in the control
1202 register, thus disabling hit-under-miss without putting the
1203 processor into full low interrupt latency mode. ARM11MPCore
1206 config ARM_ERRATA_764369
1207 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for erratum 764369
1211 affecting Cortex-A9 MPCore with two or more processors (all
1212 current revisions). Under certain timing circumstances, a data
1213 cache line maintenance operation by MVA targeting an Inner
1214 Shareable memory region may fail to proceed up to either the
1215 Point of Coherency or to the Point of Unification of the
1216 system. This workaround adds a DSB instruction before the
1217 relevant cache maintenance functions and sets a specific bit
1218 in the diagnostic control register of the SCU.
1220 config ARM_ERRATA_775420
1221 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1224 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1225 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1226 operation aborts with MMU exception, it might cause the processor
1227 to deadlock. This workaround puts DSB before executing ISB if
1228 an abort may occur on cache maintenance.
1230 config ARM_ERRATA_798181
1231 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1232 depends on CPU_V7 && SMP
1234 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1235 adequately shooting down all use of the old entries. This
1236 option enables the Linux kernel workaround for this erratum
1237 which sends an IPI to the CPUs that are running the same ASID
1238 as the one being invalidated.
1240 config ARM_ERRATA_773022
1241 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1244 This option enables the workaround for the 773022 Cortex-A15
1245 (up to r0p4) erratum. In certain rare sequences of code, the
1246 loop buffer may deliver incorrect instructions. This
1247 workaround disables the loop buffer to avoid the erratum.
1251 source "arch/arm/common/Kconfig"
1261 Find out whether you have ISA slots on your motherboard. ISA is the
1262 name of a bus system, i.e. the way the CPU talks to the other stuff
1263 inside your box. Other bus systems are PCI, EISA, MicroChannel
1264 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1265 newer boards don't support it. If you have ISA, say Y, otherwise N.
1267 # Select ISA DMA controller support
1272 # Select ISA DMA interface
1277 bool "PCI support" if MIGHT_HAVE_PCI
1279 Find out whether you have a PCI motherboard. PCI is the name of a
1280 bus system, i.e. the way the CPU talks to the other stuff inside
1281 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1282 VESA. If you have PCI, say Y, otherwise N.
1288 config PCI_NANOENGINE
1289 bool "BSE nanoEngine PCI support"
1290 depends on SA1100_NANOENGINE
1292 Enable PCI on the BSE nanoEngine board.
1297 config PCI_HOST_ITE8152
1299 depends on PCI && MACH_ARMCORE
1303 source "drivers/pci/Kconfig"
1304 source "drivers/pci/pcie/Kconfig"
1306 source "drivers/pcmcia/Kconfig"
1310 menu "Kernel Features"
1315 This option should be selected by machines which have an SMP-
1318 The only effect of this option is to make the SMP-related
1319 options available to the user for configuration.
1322 bool "Symmetric Multi-Processing"
1323 depends on CPU_V6K || CPU_V7
1324 depends on GENERIC_CLOCKEVENTS
1326 depends on MMU || ARM_MPU
1328 This enables support for systems with more than one CPU. If you have
1329 a system with only one CPU, say N. If you have a system with more
1330 than one CPU, say Y.
1332 If you say N here, the kernel will run on uni- and multiprocessor
1333 machines, but will use only one CPU of a multiprocessor machine. If
1334 you say Y here, the kernel will run on many, but not all,
1335 uniprocessor machines. On a uniprocessor machine, the kernel
1336 will run faster if you say N here.
1338 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1339 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1340 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1342 If you don't know what to do here, say N.
1345 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1346 depends on SMP && !XIP_KERNEL && MMU
1349 SMP kernels contain instructions which fail on non-SMP processors.
1350 Enabling this option allows the kernel to modify itself to make
1351 these instructions safe. Disabling it allows about 1K of space
1354 If you don't know what to do here, say Y.
1356 config ARM_CPU_TOPOLOGY
1357 bool "Support cpu topology definition"
1358 depends on SMP && CPU_V7
1361 Support ARM cpu topology definition. The MPIDR register defines
1362 affinity between processors which is then used to describe the cpu
1363 topology of an ARM System.
1366 bool "Multi-core scheduler support"
1367 depends on ARM_CPU_TOPOLOGY
1369 Multi-core scheduler support improves the CPU scheduler's decision
1370 making when dealing with multi-core CPU chips at a cost of slightly
1371 increased overhead in some places. If unsure say N here.
1374 bool "SMT scheduler support"
1375 depends on ARM_CPU_TOPOLOGY
1377 Improves the CPU scheduler's decision making when dealing with
1378 MultiThreading at a cost of slightly increased overhead in some
1379 places. If unsure say N here.
1384 This option enables support for the ARM system coherency unit
1386 config HAVE_ARM_ARCH_TIMER
1387 bool "Architected timer support"
1389 select ARM_ARCH_TIMER
1390 select GENERIC_CLOCKEVENTS
1392 This option enables support for the ARM architected timer
1397 select CLKSRC_OF if OF
1399 This options enables support for the ARM timer and watchdog unit
1402 bool "Multi-Cluster Power Management"
1403 depends on CPU_V7 && SMP
1405 This option provides the common power management infrastructure
1406 for (multi-)cluster based systems, such as big.LITTLE based
1410 bool "big.LITTLE support (Experimental)"
1411 depends on CPU_V7 && SMP
1414 This option enables support selections for the big.LITTLE
1415 system architecture.
1418 bool "big.LITTLE switcher support"
1419 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1420 select ARM_CPU_SUSPEND
1423 The big.LITTLE "switcher" provides the core functionality to
1424 transparently handle transition between a cluster of A15's
1425 and a cluster of A7's in a big.LITTLE system.
1427 config BL_SWITCHER_DUMMY_IF
1428 tristate "Simple big.LITTLE switcher user interface"
1429 depends on BL_SWITCHER && DEBUG_KERNEL
1431 This is a simple and dummy char dev interface to control
1432 the big.LITTLE switcher core code. It is meant for
1433 debugging purposes only.
1436 prompt "Memory split"
1440 Select the desired split between kernel and user memory.
1442 If you are not absolutely sure what you are doing, leave this
1446 bool "3G/1G user/kernel split"
1448 bool "2G/2G user/kernel split"
1450 bool "1G/3G user/kernel split"
1455 default PHYS_OFFSET if !MMU
1456 default 0x40000000 if VMSPLIT_1G
1457 default 0x80000000 if VMSPLIT_2G
1461 int "Maximum number of CPUs (2-32)"
1467 bool "Support for hot-pluggable CPUs"
1470 Say Y here to experiment with turning CPUs off and on. CPUs
1471 can be controlled through /sys/devices/system/cpu.
1474 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1477 Say Y here if you want Linux to communicate with system firmware
1478 implementing the PSCI specification for CPU-centric power
1479 management operations described in ARM document number ARM DEN
1480 0022A ("Power State Coordination Interface System Software on
1483 # The GPIO number here must be sorted by descending number. In case of
1484 # a multiplatform kernel, we just want the highest value required by the
1485 # selected platforms.
1488 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1489 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1490 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1491 default 416 if ARCH_SUNXI
1492 default 392 if ARCH_U8500
1493 default 352 if ARCH_VT8500
1494 default 288 if ARCH_ROCKCHIP
1495 default 264 if MACH_H4700
1498 Maximum number of GPIOs in the system.
1500 If unsure, leave the default value.
1502 source kernel/Kconfig.preempt
1506 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1507 ARCH_S5PV210 || ARCH_EXYNOS4
1508 default AT91_TIMER_HZ if ARCH_AT91
1509 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1513 depends on HZ_FIXED = 0
1514 prompt "Timer frequency"
1538 default HZ_FIXED if HZ_FIXED != 0
1539 default 100 if HZ_100
1540 default 200 if HZ_200
1541 default 250 if HZ_250
1542 default 300 if HZ_300
1543 default 500 if HZ_500
1547 def_bool HIGH_RES_TIMERS
1549 config THUMB2_KERNEL
1550 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1551 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1552 default y if CPU_THUMBONLY
1554 select ARM_ASM_UNIFIED
1557 By enabling this option, the kernel will be compiled in
1558 Thumb-2 mode. A compiler/assembler that understand the unified
1559 ARM-Thumb syntax is needed.
1563 config THUMB2_AVOID_R_ARM_THM_JUMP11
1564 bool "Work around buggy Thumb-2 short branch relocations in gas"
1565 depends on THUMB2_KERNEL && MODULES
1568 Various binutils versions can resolve Thumb-2 branches to
1569 locally-defined, preemptible global symbols as short-range "b.n"
1570 branch instructions.
1572 This is a problem, because there's no guarantee the final
1573 destination of the symbol, or any candidate locations for a
1574 trampoline, are within range of the branch. For this reason, the
1575 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1576 relocation in modules at all, and it makes little sense to add
1579 The symptom is that the kernel fails with an "unsupported
1580 relocation" error when loading some modules.
1582 Until fixed tools are available, passing
1583 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1584 code which hits this problem, at the cost of a bit of extra runtime
1585 stack usage in some cases.
1587 The problem is described in more detail at:
1588 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1590 Only Thumb-2 kernels are affected.
1592 Unless you are sure your tools don't have this problem, say Y.
1594 config ARM_ASM_UNIFIED
1598 bool "Use the ARM EABI to compile the kernel"
1600 This option allows for the kernel to be compiled using the latest
1601 ARM ABI (aka EABI). This is only useful if you are using a user
1602 space environment that is also compiled with EABI.
1604 Since there are major incompatibilities between the legacy ABI and
1605 EABI, especially with regard to structure member alignment, this
1606 option also changes the kernel syscall calling convention to
1607 disambiguate both ABIs and allow for backward compatibility support
1608 (selected with CONFIG_OABI_COMPAT).
1610 To use this you need GCC version 4.0.0 or later.
1613 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1614 depends on AEABI && !THUMB2_KERNEL
1616 This option preserves the old syscall interface along with the
1617 new (ARM EABI) one. It also provides a compatibility layer to
1618 intercept syscalls that have structure arguments which layout
1619 in memory differs between the legacy ABI and the new ARM EABI
1620 (only for non "thumb" binaries). This option adds a tiny
1621 overhead to all syscalls and produces a slightly larger kernel.
1623 The seccomp filter system will not be available when this is
1624 selected, since there is no way yet to sensibly distinguish
1625 between calling conventions during filtering.
1627 If you know you'll be using only pure EABI user space then you
1628 can say N here. If this option is not selected and you attempt
1629 to execute a legacy ABI binary then the result will be
1630 UNPREDICTABLE (in fact it can be predicted that it won't work
1631 at all). If in doubt say N.
1633 config ARCH_HAS_HOLES_MEMORYMODEL
1636 config ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SPARSEMEM_DEFAULT
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config ARCH_SELECT_MEMORY_MODEL
1643 def_bool ARCH_SPARSEMEM_ENABLE
1645 config HAVE_ARCH_PFN_VALID
1646 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1649 bool "High Memory Support"
1652 The address space of ARM processors is only 4 Gigabytes large
1653 and it has to accommodate user address space, kernel address
1654 space as well as some memory mapped IO. That means that, if you
1655 have a large amount of physical memory and/or IO, not all of the
1656 memory can be "permanently mapped" by the kernel. The physical
1657 memory that is not permanently mapped is called "high memory".
1659 Depending on the selected kernel/user memory split, minimum
1660 vmalloc space and actual amount of RAM, you may not need this
1661 option which should result in a slightly faster kernel.
1666 bool "Allocate 2nd-level pagetables from highmem"
1669 config HW_PERF_EVENTS
1670 bool "Enable hardware performance counter support for perf events"
1671 depends on PERF_EVENTS
1674 Enable hardware performance counter support for perf events. If
1675 disabled, perf events will use software events only.
1677 config SYS_SUPPORTS_HUGETLBFS
1681 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1685 config ARCH_WANT_GENERAL_HUGETLB
1690 config FORCE_MAX_ZONEORDER
1691 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1692 range 11 64 if ARCH_SHMOBILE_LEGACY
1693 default "12" if SOC_AM33XX
1694 default "9" if SA1111 || ARCH_EFM32
1697 The kernel memory allocator divides physically contiguous memory
1698 blocks into "zones", where each zone is a power of two number of
1699 pages. This option selects the largest power of two that the kernel
1700 keeps in the memory allocator. If you need to allocate very large
1701 blocks of physically contiguous memory, then you may need to
1702 increase this value.
1704 This config option is actually maximum order plus one. For example,
1705 a value of 11 means that the largest free memory block is 2^10 pages.
1707 config ALIGNMENT_TRAP
1709 depends on CPU_CP15_MMU
1710 default y if !ARCH_EBSA110
1711 select HAVE_PROC_CPU if PROC_FS
1713 ARM processors cannot fetch/store information which is not
1714 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1715 address divisible by 4. On 32-bit ARM processors, these non-aligned
1716 fetch/store instructions will be emulated in software if you say
1717 here, which has a severe performance impact. This is necessary for
1718 correct operation of some network protocols. With an IP-only
1719 configuration it is safe to say N, otherwise say Y.
1721 config UACCESS_WITH_MEMCPY
1722 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1724 default y if CPU_FEROCEON
1726 Implement faster copy_to_user and clear_user methods for CPU
1727 cores where a 8-word STM instruction give significantly higher
1728 memory write throughput than a sequence of individual 32bit stores.
1730 A possible side effect is a slight increase in scheduling latency
1731 between threads sharing the same address space if they invoke
1732 such copy operations with large buffers.
1734 However, if the CPU data cache is using a write-allocate mode,
1735 this option is unlikely to provide any performance gain.
1739 prompt "Enable seccomp to safely compute untrusted bytecode"
1741 This kernel feature is useful for number crunching applications
1742 that may need to compute untrusted bytecode during their
1743 execution. By using pipes or other transports made available to
1744 the process as file descriptors supporting the read/write
1745 syscalls, it's possible to isolate those applications in
1746 their own address space using seccomp. Once seccomp is
1747 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1748 and the task is only allowed to execute a few safe syscalls
1749 defined by each seccomp mode.
1762 bool "Xen guest support on ARM (EXPERIMENTAL)"
1763 depends on ARM && AEABI && OF
1764 depends on CPU_V7 && !CPU_V6
1765 depends on !GENERIC_ATOMIC64
1767 select ARCH_DMA_ADDR_T_64BIT
1771 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1778 bool "Flattened Device Tree support"
1781 select OF_EARLY_FLATTREE
1782 select OF_RESERVED_MEM
1784 Include support for flattened device tree machine descriptions.
1787 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1790 This is the traditional way of passing data to the kernel at boot
1791 time. If you are solely relying on the flattened device tree (or
1792 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1793 to remove ATAGS support from your kernel binary. If unsure,
1796 config DEPRECATED_PARAM_STRUCT
1797 bool "Provide old way to pass kernel parameters"
1800 This was deprecated in 2001 and announced to live on for 5 years.
1801 Some old boot loaders still use this way.
1803 # Compressed boot loader in ROM. Yes, we really want to ask about
1804 # TEXT and BSS so we preserve their values in the config files.
1805 config ZBOOT_ROM_TEXT
1806 hex "Compressed ROM boot loader base address"
1809 The physical address at which the ROM-able zImage is to be
1810 placed in the target. Platforms which normally make use of
1811 ROM-able zImage formats normally set this to a suitable
1812 value in their defconfig file.
1814 If ZBOOT_ROM is not enabled, this has no effect.
1816 config ZBOOT_ROM_BSS
1817 hex "Compressed ROM boot loader BSS address"
1820 The base address of an area of read/write memory in the target
1821 for the ROM-able zImage which must be available while the
1822 decompressor is running. It must be large enough to hold the
1823 entire decompressed kernel plus an additional 128 KiB.
1824 Platforms which normally make use of ROM-able zImage formats
1825 normally set this to a suitable value in their defconfig file.
1827 If ZBOOT_ROM is not enabled, this has no effect.
1830 bool "Compressed boot loader in ROM/flash"
1831 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1832 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1834 Say Y here if you intend to execute your compressed kernel image
1835 (zImage) directly from ROM or flash. If unsure, say N.
1838 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1839 depends on ZBOOT_ROM && ARCH_SH7372
1840 default ZBOOT_ROM_NONE
1842 Include experimental SD/MMC loading code in the ROM-able zImage.
1843 With this enabled it is possible to write the ROM-able zImage
1844 kernel image to an MMC or SD card and boot the kernel straight
1845 from the reset vector. At reset the processor Mask ROM will load
1846 the first part of the ROM-able zImage which in turn loads the
1847 rest the kernel image to RAM.
1849 config ZBOOT_ROM_NONE
1850 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1852 Do not load image from SD or MMC
1854 config ZBOOT_ROM_MMCIF
1855 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1857 Load image from MMCIF hardware block.
1859 config ZBOOT_ROM_SH_MOBILE_SDHI
1860 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1862 Load image from SDHI hardware block
1866 config ARM_APPENDED_DTB
1867 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1870 With this option, the boot code will look for a device tree binary
1871 (DTB) appended to zImage
1872 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1874 This is meant as a backward compatibility convenience for those
1875 systems with a bootloader that can't be upgraded to accommodate
1876 the documented boot protocol using a device tree.
1878 Beware that there is very little in terms of protection against
1879 this option being confused by leftover garbage in memory that might
1880 look like a DTB header after a reboot if no actual DTB is appended
1881 to zImage. Do not leave this option active in a production kernel
1882 if you don't intend to always append a DTB. Proper passing of the
1883 location into r2 of a bootloader provided DTB is always preferable
1886 config ARM_ATAG_DTB_COMPAT
1887 bool "Supplement the appended DTB with traditional ATAG information"
1888 depends on ARM_APPENDED_DTB
1890 Some old bootloaders can't be updated to a DTB capable one, yet
1891 they provide ATAGs with memory configuration, the ramdisk address,
1892 the kernel cmdline string, etc. Such information is dynamically
1893 provided by the bootloader and can't always be stored in a static
1894 DTB. To allow a device tree enabled kernel to be used with such
1895 bootloaders, this option allows zImage to extract the information
1896 from the ATAG list and store it at run time into the appended DTB.
1899 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1900 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1902 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1903 bool "Use bootloader kernel arguments if available"
1905 Uses the command-line options passed by the boot loader instead of
1906 the device tree bootargs property. If the boot loader doesn't provide
1907 any, the device tree bootargs property will be used.
1909 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1910 bool "Extend with bootloader kernel arguments"
1912 The command-line arguments provided by the boot loader will be
1913 appended to the the device tree bootargs property.
1918 string "Default kernel command string"
1921 On some architectures (EBSA110 and CATS), there is currently no way
1922 for the boot loader to pass arguments to the kernel. For these
1923 architectures, you should supply some command-line options at build
1924 time by entering them here. As a minimum, you should specify the
1925 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1928 prompt "Kernel command line type" if CMDLINE != ""
1929 default CMDLINE_FROM_BOOTLOADER
1932 config CMDLINE_FROM_BOOTLOADER
1933 bool "Use bootloader kernel arguments if available"
1935 Uses the command-line options passed by the boot loader. If
1936 the boot loader doesn't provide any, the default kernel command
1937 string provided in CMDLINE will be used.
1939 config CMDLINE_EXTEND
1940 bool "Extend bootloader kernel arguments"
1942 The command-line arguments provided by the boot loader will be
1943 appended to the default kernel command string.
1945 config CMDLINE_FORCE
1946 bool "Always use the default kernel command string"
1948 Always use the default kernel command string, even if the boot
1949 loader passes other arguments to the kernel.
1950 This is useful if you cannot or don't want to change the
1951 command-line options your boot loader passes to the kernel.
1955 bool "Kernel Execute-In-Place from ROM"
1956 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1958 Execute-In-Place allows the kernel to run from non-volatile storage
1959 directly addressable by the CPU, such as NOR flash. This saves RAM
1960 space since the text section of the kernel is not loaded from flash
1961 to RAM. Read-write sections, such as the data section and stack,
1962 are still copied to RAM. The XIP kernel is not compressed since
1963 it has to run directly from flash, so it will take more space to
1964 store it. The flash address used to link the kernel object files,
1965 and for storing it, is configuration dependent. Therefore, if you
1966 say Y here, you must know the proper physical address where to
1967 store the kernel image depending on your own flash memory usage.
1969 Also note that the make target becomes "make xipImage" rather than
1970 "make zImage" or "make Image". The final kernel binary to put in
1971 ROM memory will be arch/arm/boot/xipImage.
1975 config XIP_PHYS_ADDR
1976 hex "XIP Kernel Physical Location"
1977 depends on XIP_KERNEL
1978 default "0x00080000"
1980 This is the physical address in your flash memory the kernel will
1981 be linked for and stored to. This address is dependent on your
1985 bool "Kexec system call (EXPERIMENTAL)"
1986 depends on (!SMP || PM_SLEEP_SMP)
1988 select CRYPTO_SHA256
1990 kexec is a system call that implements the ability to shutdown your
1991 current kernel, and to start another kernel. It is like a reboot
1992 but it is independent of the system firmware. And like a reboot
1993 you can start any kernel with it, not just Linux.
1995 It is an ongoing process to be certain the hardware in a machine
1996 is properly shutdown, so do not be surprised if this code does not
1997 initially work for you.
2000 bool "Export atags in procfs"
2001 depends on ATAGS && KEXEC
2004 Should the atags used to boot the kernel be exported in an "atags"
2005 file in procfs. Useful with kexec.
2008 bool "Build kdump crash kernel (EXPERIMENTAL)"
2010 Generate crash dump after being started by kexec. This should
2011 be normally only set in special crash dump kernels which are
2012 loaded in the main kernel with kexec-tools into a specially
2013 reserved region and then later executed after a crash by
2014 kdump/kexec. The crash dump kernel must be compiled to a
2015 memory address not used by the main kernel
2017 For more details see Documentation/kdump/kdump.txt
2019 config AUTO_ZRELADDR
2020 bool "Auto calculation of the decompressed kernel image address"
2022 ZRELADDR is the physical address where the decompressed kernel
2023 image will be placed. If AUTO_ZRELADDR is selected, the address
2024 will be determined at run-time by masking the current IP with
2025 0xf8000000. This assumes the zImage being placed in the first 128MB
2026 from start of memory.
2030 menu "CPU Power Management"
2032 source "drivers/cpufreq/Kconfig"
2034 source "drivers/cpuidle/Kconfig"
2038 menu "Floating point emulation"
2040 comment "At least one emulation must be selected"
2043 bool "NWFPE math emulation"
2044 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2046 Say Y to include the NWFPE floating point emulator in the kernel.
2047 This is necessary to run most binaries. Linux does not currently
2048 support floating point hardware so you need to say Y here even if
2049 your machine has an FPA or floating point co-processor podule.
2051 You may say N here if you are going to load the Acorn FPEmulator
2052 early in the bootup.
2055 bool "Support extended precision"
2056 depends on FPE_NWFPE
2058 Say Y to include 80-bit support in the kernel floating-point
2059 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2060 Note that gcc does not generate 80-bit operations by default,
2061 so in most cases this option only enlarges the size of the
2062 floating point emulator without any good reason.
2064 You almost surely want to say N here.
2067 bool "FastFPE math emulation (EXPERIMENTAL)"
2068 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2070 Say Y here to include the FAST floating point emulator in the kernel.
2071 This is an experimental much faster emulator which now also has full
2072 precision for the mantissa. It does not support any exceptions.
2073 It is very simple, and approximately 3-6 times faster than NWFPE.
2075 It should be sufficient for most programs. It may be not suitable
2076 for scientific calculations, but you have to check this for yourself.
2077 If you do not feel you need a faster FP emulation you should better
2081 bool "VFP-format floating point maths"
2082 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2084 Say Y to include VFP support code in the kernel. This is needed
2085 if your hardware includes a VFP unit.
2087 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2088 release notes and additional status information.
2090 Say N if your target does not have VFP hardware.
2098 bool "Advanced SIMD (NEON) Extension support"
2099 depends on VFPv3 && CPU_V7
2101 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2104 config KERNEL_MODE_NEON
2105 bool "Support for NEON in kernel mode"
2106 depends on NEON && AEABI
2108 Say Y to include support for NEON in kernel mode.
2112 menu "Userspace binary formats"
2114 source "fs/Kconfig.binfmt"
2117 tristate "RISC OS personality"
2120 Say Y here to include the kernel code necessary if you want to run
2121 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2122 experimental; if this sounds frightening, say N and sleep in peace.
2123 You can also say M here to compile this support as a module (which
2124 will be called arthur).
2128 menu "Power management options"
2130 source "kernel/power/Kconfig"
2132 config ARCH_SUSPEND_POSSIBLE
2133 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2134 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2137 config ARM_CPU_SUSPEND
2140 config ARCH_HIBERNATION_POSSIBLE
2143 default y if ARCH_SUSPEND_POSSIBLE
2147 source "net/Kconfig"
2149 source "drivers/Kconfig"
2153 source "arch/arm/Kconfig.debug"
2155 source "security/Kconfig"
2157 source "crypto/Kconfig"
2159 source "lib/Kconfig"
2161 source "arch/arm/kvm/Kconfig"