4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
8 select ARCH_HAS_STRICT_MODULE_RWX if MMU
9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
10 select ARCH_HAVE_CUSTOM_GPIO_H
11 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_MIGHT_HAVE_PC_PARPORT
13 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
14 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
15 select ARCH_SUPPORTS_ATOMIC_RMW
16 select ARCH_USE_BUILTIN_BSWAP
17 select ARCH_USE_CMPXCHG_LOCKREF
18 select ARCH_WANT_IPC_PARSE_VERSION
19 select BUILDTIME_EXTABLE_SORT if MMU
20 select CLONE_BACKWARDS
21 select CPU_PM if (SUSPEND || CPU_IDLE)
22 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
24 select EDAC_ATOMIC_SCRUB
25 select GENERIC_ALLOCATOR
26 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_EARLY_IOREMAP
29 select GENERIC_IDLE_POLL_SETUP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_IRQ_SHOW_LEVEL
33 select GENERIC_PCI_IOMAP
34 select GENERIC_SCHED_CLOCK
35 select GENERIC_SMP_IDLE_THREAD
36 select GENERIC_STRNCPY_FROM_USER
37 select GENERIC_STRNLEN_USER
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
41 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
42 select HAVE_ARCH_HARDENED_USERCOPY
43 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
44 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
45 select HAVE_ARCH_MMAP_RND_BITS if MMU
46 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
47 select HAVE_ARCH_TRACEHOOK
48 select HAVE_ARM_SMCCC if CPU_V7
50 select HAVE_CC_STACKPROTECTOR
51 select HAVE_CONTEXT_TRACKING
52 select HAVE_C_RECORDMCOUNT
53 select HAVE_DEBUG_KMEMLEAK
54 select HAVE_DMA_API_DEBUG
55 select HAVE_DMA_CONTIGUOUS if MMU
56 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
58 select HAVE_EXIT_THREAD
59 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
60 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
61 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
62 select HAVE_GCC_PLUGINS
63 select HAVE_GENERIC_DMA_COHERENT
64 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
65 select HAVE_IDE if PCI || ISA || PCMCIA
66 select HAVE_IRQ_TIME_ACCOUNTING
67 select HAVE_KERNEL_GZIP
68 select HAVE_KERNEL_LZ4
69 select HAVE_KERNEL_LZMA
70 select HAVE_KERNEL_LZO
72 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
73 select HAVE_KRETPROBES if (HAVE_KPROBES)
75 select HAVE_MOD_ARCH_SPECIFIC
77 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
78 select HAVE_OPTPROBES if !THUMB2_KERNEL
79 select HAVE_PERF_EVENTS
81 select HAVE_PERF_USER_STACK_DUMP
82 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
83 select HAVE_REGS_AND_STACK_ACCESS_API
84 select HAVE_SYSCALL_TRACEPOINTS
86 select HAVE_VIRT_CPU_ACCOUNTING_GEN
87 select IRQ_FORCED_THREADING
88 select MODULES_USE_ELF_REL
90 select OF_EARLY_FLATTREE if OF
91 select OF_RESERVED_MEM if OF
93 select OLD_SIGSUSPEND3
94 select PERF_USE_VMALLOC
96 select SYS_SUPPORTS_APM_EMULATION
97 # Above selects are sorted alphabetically; please add new ones
98 # according to that. Thanks.
100 The ARM series is a line of low-power-consumption RISC chip designs
101 licensed by ARM Ltd and targeted at embedded applications and
102 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
103 manufactured, but legacy ARM-based PC hardware remains popular in
104 Europe. There is an ARM Linux project with a web page at
105 <http://www.arm.linux.org.uk/>.
107 config ARM_HAS_SG_CHAIN
108 select ARCH_HAS_SG_CHAIN
111 config NEED_SG_DMA_LENGTH
114 config ARM_DMA_USE_IOMMU
116 select ARM_HAS_SG_CHAIN
117 select NEED_SG_DMA_LENGTH
121 config ARM_DMA_IOMMU_ALIGNMENT
122 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
126 DMA mapping framework by default aligns all buffers to the smallest
127 PAGE_SIZE order which is greater than or equal to the requested buffer
128 size. This works well for buffers up to a few hundreds kilobytes, but
129 for larger buffers it just a waste of address space. Drivers which has
130 relatively small addressing window (like 64Mib) might run out of
131 virtual space with just a few allocations.
133 With this parameter you can specify the maximum PAGE_SIZE order for
134 DMA IOMMU buffers. Larger buffers will be aligned only to this
135 specified order. The order is expressed as a power of two multiplied
140 config MIGHT_HAVE_PCI
143 config SYS_SUPPORTS_APM_EMULATION
148 select GENERIC_ALLOCATOR
159 The Extended Industry Standard Architecture (EISA) bus was
160 developed as an open alternative to the IBM MicroChannel bus.
162 The EISA bus provided some of the features of the IBM MicroChannel
163 bus while maintaining backward compatibility with cards made for
164 the older ISA bus. The EISA bus saw limited use between 1988 and
165 1995 when it was made obsolete by the PCI bus.
167 Say Y here if you are building a kernel for an EISA-based machine.
174 config STACKTRACE_SUPPORT
178 config LOCKDEP_SUPPORT
182 config TRACE_IRQFLAGS_SUPPORT
186 config RWSEM_XCHGADD_ALGORITHM
190 config ARCH_HAS_ILOG2_U32
193 config ARCH_HAS_ILOG2_U64
196 config ARCH_HAS_BANDGAP
199 config FIX_EARLYCON_MEM
202 config GENERIC_HWEIGHT
206 config GENERIC_CALIBRATE_DELAY
210 config ARCH_MAY_HAVE_PC_FDC
216 config NEED_DMA_MAP_STATE
219 config ARCH_SUPPORTS_UPROBES
222 config ARCH_HAS_DMA_SET_COHERENT_MASK
225 config GENERIC_ISA_DMA
231 config NEED_RET_TO_USER
239 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
240 default DRAM_BASE if REMAP_VECTORS_TO_RAM
243 The base address of exception vectors. This must be two pages
246 config ARM_PATCH_PHYS_VIRT
247 bool "Patch physical to virtual translations at runtime" if EMBEDDED
249 depends on !XIP_KERNEL && MMU
251 Patch phys-to-virt and virt-to-phys translation functions at
252 boot and module load time according to the position of the
253 kernel in system memory.
255 This can only be used with non-XIP MMU kernels where the base
256 of physical memory is at a 16MB boundary.
258 Only disable this option if you know that you do not require
259 this feature (eg, building a kernel for a single machine) and
260 you need to shrink the kernel to the minimal size.
262 config NEED_MACH_IO_H
265 Select this when mach/io.h is required to provide special
266 definitions for this platform. The need for mach/io.h should
267 be avoided when possible.
269 config NEED_MACH_MEMORY_H
272 Select this when mach/memory.h is required to provide special
273 definitions for this platform. The need for mach/memory.h should
274 be avoided when possible.
277 hex "Physical address of main memory" if MMU
278 depends on !ARM_PATCH_PHYS_VIRT
279 default DRAM_BASE if !MMU
280 default 0x00000000 if ARCH_EBSA110 || \
286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
287 default 0x20000000 if ARCH_S5PV210
288 default 0xc0000000 if ARCH_SA1100
290 Please provide the physical address corresponding to the
291 location of main memory in your system.
297 config PGTABLE_LEVELS
299 default 3 if ARM_LPAE
302 source "init/Kconfig"
304 source "kernel/Kconfig.freezer"
309 bool "MMU-based Paged Memory Management Support"
312 Select if you want MMU-based virtualised addressing space
313 support by paged memory management. If unsure, say 'Y'.
315 config ARCH_MMAP_RND_BITS_MIN
318 config ARCH_MMAP_RND_BITS_MAX
319 default 14 if PAGE_OFFSET=0x40000000
320 default 15 if PAGE_OFFSET=0x80000000
324 # The "ARM system type" choice list is ordered alphabetically by option
325 # text. Please add new entries in the option alphabetic order.
328 prompt "ARM system type"
329 default ARM_SINGLE_ARMV7M if !MMU
330 default ARCH_MULTIPLATFORM if MMU
332 config ARCH_MULTIPLATFORM
333 bool "Allow multiple platforms to be selected"
335 select ARM_HAS_SG_CHAIN
336 select ARM_PATCH_PHYS_VIRT
340 select GENERIC_CLOCKEVENTS
341 select MIGHT_HAVE_PCI
342 select MULTI_IRQ_HANDLER
343 select PCI_DOMAINS if PCI
347 config ARM_SINGLE_ARMV7M
348 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
355 select GENERIC_CLOCKEVENTS
361 bool "Cortina Systems Gemini"
364 select GENERIC_CLOCKEVENTS
367 Support for the Cortina Systems Gemini family SoCs
371 select ARCH_USES_GETTIMEOFFSET
374 select NEED_MACH_IO_H
375 select NEED_MACH_MEMORY_H
378 This is an evaluation board for the StrongARM processor available
379 from Digital. It has limited hardware on-board, including an
380 Ethernet interface, two PCMCIA sockets, two serial ports and a
385 select ARCH_HAS_HOLES_MEMORYMODEL
387 select ARM_PATCH_PHYS_VIRT
393 select GENERIC_CLOCKEVENTS
396 This enables support for the Cirrus EP93xx series of CPUs.
398 config ARCH_FOOTBRIDGE
402 select GENERIC_CLOCKEVENTS
404 select NEED_MACH_IO_H if !MMU
405 select NEED_MACH_MEMORY_H
407 Support for systems based on the DC21285 companion chip
408 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
411 bool "Hilscher NetX based"
415 select GENERIC_CLOCKEVENTS
417 This enables support for systems based on the Hilscher NetX Soc
423 select NEED_MACH_MEMORY_H
424 select NEED_RET_TO_USER
430 Support for Intel's IOP13XX (XScale) family of processors.
438 select NEED_RET_TO_USER
442 Support for Intel's 80219 and IOP32X (XScale) family of
451 select NEED_RET_TO_USER
455 Support for Intel's IOP33X (XScale) family of processors.
460 select ARCH_HAS_DMA_SET_COHERENT_MASK
461 select ARCH_SUPPORTS_BIG_ENDIAN
464 select DMABOUNCE if PCI
465 select GENERIC_CLOCKEVENTS
467 select MIGHT_HAVE_PCI
468 select NEED_MACH_IO_H
469 select USB_EHCI_BIG_ENDIAN_DESC
470 select USB_EHCI_BIG_ENDIAN_MMIO
472 Support for Intel's IXP4XX (XScale) family of processors.
477 select GENERIC_CLOCKEVENTS
479 select MIGHT_HAVE_PCI
480 select MULTI_IRQ_HANDLER
484 select PLAT_ORION_LEGACY
486 select PM_GENERIC_DOMAINS if PM
488 Support for the Marvell Dove SoC 88AP510
491 bool "Micrel/Kendin KS8695"
494 select GENERIC_CLOCKEVENTS
496 select NEED_MACH_MEMORY_H
498 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
499 System-on-Chip devices.
502 bool "Nuvoton W90X900 CPU"
506 select GENERIC_CLOCKEVENTS
509 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
510 At present, the w90x900 has been renamed nuc900, regarding
511 the ARM series product line, you can login the following
512 link address to know more.
514 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
515 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
521 select CLKSRC_LPC32XX
524 select GENERIC_CLOCKEVENTS
526 select MULTI_IRQ_HANDLER
530 Support for the NXP LPC32XX family of processors
533 bool "PXA2xx/PXA3xx-based"
536 select ARM_CPU_SUSPEND if PM
543 select CPU_XSCALE if !CPU_XSC3
544 select GENERIC_CLOCKEVENTS
549 select MULTI_IRQ_HANDLER
553 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
559 select ARCH_MAY_HAVE_PC_FDC
560 select ARCH_SPARSEMEM_ENABLE
561 select ARCH_USES_GETTIMEOFFSET
565 select HAVE_PATA_PLATFORM
567 select NEED_MACH_IO_H
568 select NEED_MACH_MEMORY_H
571 On the Acorn Risc-PC, Linux can support the internal IDE disk and
572 CD-ROM interface, serial and parallel port, and the floppy drive.
577 select ARCH_SPARSEMEM_ENABLE
581 select CLKSRC_OF if OF
584 select GENERIC_CLOCKEVENTS
589 select MULTI_IRQ_HANDLER
590 select NEED_MACH_MEMORY_H
593 Support for StrongARM 11x0 based boards.
596 bool "Samsung S3C24XX SoCs"
599 select CLKSRC_SAMSUNG_PWM
600 select GENERIC_CLOCKEVENTS
603 select HAVE_S3C2410_I2C if I2C
604 select HAVE_S3C2410_WATCHDOG if WATCHDOG
605 select HAVE_S3C_RTC if RTC_CLASS
606 select MULTI_IRQ_HANDLER
607 select NEED_MACH_IO_H
610 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
611 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
612 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
613 Samsung SMDK2410 development board (and derivatives).
617 select ARCH_HAS_HOLES_MEMORYMODEL
620 select GENERIC_ALLOCATOR
621 select GENERIC_CLOCKEVENTS
622 select GENERIC_IRQ_CHIP
628 Support for TI's DaVinci platform.
633 select ARCH_HAS_HOLES_MEMORYMODEL
637 select GENERIC_CLOCKEVENTS
638 select GENERIC_IRQ_CHIP
642 select MULTI_IRQ_HANDLER
643 select NEED_MACH_IO_H if PCCARD
644 select NEED_MACH_MEMORY_H
647 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
651 menu "Multiple platform selection"
652 depends on ARCH_MULTIPLATFORM
654 comment "CPU Core family selection"
657 bool "ARMv4 based platforms (FA526)"
658 depends on !ARCH_MULTI_V6_V7
659 select ARCH_MULTI_V4_V5
662 config ARCH_MULTI_V4T
663 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
664 depends on !ARCH_MULTI_V6_V7
665 select ARCH_MULTI_V4_V5
666 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
667 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
668 CPU_ARM925T || CPU_ARM940T)
671 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
672 depends on !ARCH_MULTI_V6_V7
673 select ARCH_MULTI_V4_V5
674 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
675 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
676 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
678 config ARCH_MULTI_V4_V5
682 bool "ARMv6 based platforms (ARM11)"
683 select ARCH_MULTI_V6_V7
687 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
689 select ARCH_MULTI_V6_V7
693 config ARCH_MULTI_V6_V7
695 select MIGHT_HAVE_CACHE_L2X0
697 config ARCH_MULTI_CPU_AUTO
698 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
704 bool "Dummy Virtual Machine"
705 depends on ARCH_MULTI_V7
708 select ARM_GIC_V2M if PCI
710 select ARM_GIC_V3_ITS if PCI
712 select HAVE_ARM_ARCH_TIMER
715 # This is sorted alphabetically by mach-* pathname. However, plat-*
716 # Kconfigs may be included either alphabetically (according to the
717 # plat- suffix) or along side the corresponding mach-* source.
719 source "arch/arm/mach-mvebu/Kconfig"
721 source "arch/arm/mach-alpine/Kconfig"
723 source "arch/arm/mach-artpec/Kconfig"
725 source "arch/arm/mach-asm9260/Kconfig"
727 source "arch/arm/mach-at91/Kconfig"
729 source "arch/arm/mach-axxia/Kconfig"
731 source "arch/arm/mach-bcm/Kconfig"
733 source "arch/arm/mach-berlin/Kconfig"
735 source "arch/arm/mach-clps711x/Kconfig"
737 source "arch/arm/mach-cns3xxx/Kconfig"
739 source "arch/arm/mach-davinci/Kconfig"
741 source "arch/arm/mach-digicolor/Kconfig"
743 source "arch/arm/mach-dove/Kconfig"
745 source "arch/arm/mach-ep93xx/Kconfig"
747 source "arch/arm/mach-footbridge/Kconfig"
749 source "arch/arm/mach-gemini/Kconfig"
751 source "arch/arm/mach-highbank/Kconfig"
753 source "arch/arm/mach-hisi/Kconfig"
755 source "arch/arm/mach-integrator/Kconfig"
757 source "arch/arm/mach-iop32x/Kconfig"
759 source "arch/arm/mach-iop33x/Kconfig"
761 source "arch/arm/mach-iop13xx/Kconfig"
763 source "arch/arm/mach-ixp4xx/Kconfig"
765 source "arch/arm/mach-keystone/Kconfig"
767 source "arch/arm/mach-ks8695/Kconfig"
769 source "arch/arm/mach-meson/Kconfig"
771 source "arch/arm/mach-moxart/Kconfig"
773 source "arch/arm/mach-aspeed/Kconfig"
775 source "arch/arm/mach-mv78xx0/Kconfig"
777 source "arch/arm/mach-imx/Kconfig"
779 source "arch/arm/mach-mediatek/Kconfig"
781 source "arch/arm/mach-mxs/Kconfig"
783 source "arch/arm/mach-netx/Kconfig"
785 source "arch/arm/mach-nomadik/Kconfig"
787 source "arch/arm/mach-nspire/Kconfig"
789 source "arch/arm/plat-omap/Kconfig"
791 source "arch/arm/mach-omap1/Kconfig"
793 source "arch/arm/mach-omap2/Kconfig"
795 source "arch/arm/mach-orion5x/Kconfig"
797 source "arch/arm/mach-picoxcell/Kconfig"
799 source "arch/arm/mach-pxa/Kconfig"
800 source "arch/arm/plat-pxa/Kconfig"
802 source "arch/arm/mach-mmp/Kconfig"
804 source "arch/arm/mach-oxnas/Kconfig"
806 source "arch/arm/mach-qcom/Kconfig"
808 source "arch/arm/mach-realview/Kconfig"
810 source "arch/arm/mach-rockchip/Kconfig"
812 source "arch/arm/mach-sa1100/Kconfig"
814 source "arch/arm/mach-socfpga/Kconfig"
816 source "arch/arm/mach-spear/Kconfig"
818 source "arch/arm/mach-sti/Kconfig"
820 source "arch/arm/mach-s3c24xx/Kconfig"
822 source "arch/arm/mach-s3c64xx/Kconfig"
824 source "arch/arm/mach-s5pv210/Kconfig"
826 source "arch/arm/mach-exynos/Kconfig"
827 source "arch/arm/plat-samsung/Kconfig"
829 source "arch/arm/mach-shmobile/Kconfig"
831 source "arch/arm/mach-sunxi/Kconfig"
833 source "arch/arm/mach-prima2/Kconfig"
835 source "arch/arm/mach-tango/Kconfig"
837 source "arch/arm/mach-tegra/Kconfig"
839 source "arch/arm/mach-u300/Kconfig"
841 source "arch/arm/mach-uniphier/Kconfig"
843 source "arch/arm/mach-ux500/Kconfig"
845 source "arch/arm/mach-versatile/Kconfig"
847 source "arch/arm/mach-vexpress/Kconfig"
848 source "arch/arm/plat-versatile/Kconfig"
850 source "arch/arm/mach-vt8500/Kconfig"
852 source "arch/arm/mach-w90x900/Kconfig"
854 source "arch/arm/mach-zx/Kconfig"
856 source "arch/arm/mach-zynq/Kconfig"
858 # ARMv7-M architecture
860 bool "Energy Micro efm32"
861 depends on ARM_SINGLE_ARMV7M
864 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
868 bool "NXP LPC18xx/LPC43xx"
869 depends on ARM_SINGLE_ARMV7M
870 select ARCH_HAS_RESET_CONTROLLER
872 select CLKSRC_LPC32XX
875 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
876 high performance microcontrollers.
879 bool "STMicrolectronics STM32"
880 depends on ARM_SINGLE_ARMV7M
881 select ARCH_HAS_RESET_CONTROLLER
882 select ARMV7M_SYSTICK
885 select RESET_CONTROLLER
888 Support for STMicroelectronics STM32 processors.
890 config MACH_STM32F429
891 bool "STMicrolectronics STM32F429"
892 depends on ARCH_STM32
895 config MACH_STM32F746
896 bool "STMicrolectronics STM32F746"
897 depends on ARCH_STM32
901 bool "ARM MPS2 platform"
902 depends on ARM_SINGLE_ARMV7M
906 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
907 with a range of available cores like Cortex-M3/M4/M7.
909 Please, note that depends which Application Note is used memory map
910 for the platform may vary, so adjustment of RAM base might be needed.
912 # Definitions to make life easier
918 select GENERIC_CLOCKEVENTS
924 select GENERIC_IRQ_CHIP
927 config PLAT_ORION_LEGACY
934 config PLAT_VERSATILE
937 source "arch/arm/firmware/Kconfig"
939 source arch/arm/mm/Kconfig
942 bool "Enable iWMMXt support"
943 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
944 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
946 Enable support for iWMMXt context switching at run time if
947 running on a CPU that supports it.
949 config MULTI_IRQ_HANDLER
952 Allow each machine to specify it's own IRQ handler at run time.
955 source "arch/arm/Kconfig-nommu"
958 config PJ4B_ERRATA_4742
959 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
960 depends on CPU_PJ4B && MACH_ARMADA_370
963 When coming out of either a Wait for Interrupt (WFI) or a Wait for
964 Event (WFE) IDLE states, a specific timing sensitivity exists between
965 the retiring WFI/WFE instructions and the newly issued subsequent
966 instructions. This sensitivity can result in a CPU hang scenario.
968 The software must insert either a Data Synchronization Barrier (DSB)
969 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
972 config ARM_ERRATA_326103
973 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
976 Executing a SWP instruction to read-only memory does not set bit 11
977 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
978 treat the access as a read, preventing a COW from occurring and
979 causing the faulting task to livelock.
981 config ARM_ERRATA_411920
982 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
983 depends on CPU_V6 || CPU_V6K
985 Invalidation of the Instruction Cache operation can
986 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
987 It does not affect the MPCore. This option enables the ARM Ltd.
988 recommended workaround.
990 config ARM_ERRATA_430973
991 bool "ARM errata: Stale prediction on replaced interworking branch"
994 This option enables the workaround for the 430973 Cortex-A8
995 r1p* erratum. If a code sequence containing an ARM/Thumb
996 interworking branch is replaced with another code sequence at the
997 same virtual address, whether due to self-modifying code or virtual
998 to physical address re-mapping, Cortex-A8 does not recover from the
999 stale interworking branch prediction. This results in Cortex-A8
1000 executing the new code sequence in the incorrect ARM or Thumb state.
1001 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1002 and also flushes the branch target cache at every context switch.
1003 Note that setting specific bits in the ACTLR register may not be
1004 available in non-secure mode.
1006 config ARM_ERRATA_458693
1007 bool "ARM errata: Processor deadlock when a false hazard is created"
1009 depends on !ARCH_MULTIPLATFORM
1011 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1012 erratum. For very specific sequences of memory operations, it is
1013 possible for a hazard condition intended for a cache line to instead
1014 be incorrectly associated with a different cache line. This false
1015 hazard might then cause a processor deadlock. The workaround enables
1016 the L1 caching of the NEON accesses and disables the PLD instruction
1017 in the ACTLR register. Note that setting specific bits in the ACTLR
1018 register may not be available in non-secure mode.
1020 config ARM_ERRATA_460075
1021 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1023 depends on !ARCH_MULTIPLATFORM
1025 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1026 erratum. Any asynchronous access to the L2 cache may encounter a
1027 situation in which recent store transactions to the L2 cache are lost
1028 and overwritten with stale memory contents from external memory. The
1029 workaround disables the write-allocate mode for the L2 cache via the
1030 ACTLR register. Note that setting specific bits in the ACTLR register
1031 may not be available in non-secure mode.
1033 config ARM_ERRATA_742230
1034 bool "ARM errata: DMB operation may be faulty"
1035 depends on CPU_V7 && SMP
1036 depends on !ARCH_MULTIPLATFORM
1038 This option enables the workaround for the 742230 Cortex-A9
1039 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1040 between two write operations may not ensure the correct visibility
1041 ordering of the two writes. This workaround sets a specific bit in
1042 the diagnostic register of the Cortex-A9 which causes the DMB
1043 instruction to behave as a DSB, ensuring the correct behaviour of
1046 config ARM_ERRATA_742231
1047 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1048 depends on CPU_V7 && SMP
1049 depends on !ARCH_MULTIPLATFORM
1051 This option enables the workaround for the 742231 Cortex-A9
1052 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1053 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1054 accessing some data located in the same cache line, may get corrupted
1055 data due to bad handling of the address hazard when the line gets
1056 replaced from one of the CPUs at the same time as another CPU is
1057 accessing it. This workaround sets specific bits in the diagnostic
1058 register of the Cortex-A9 which reduces the linefill issuing
1059 capabilities of the processor.
1061 config ARM_ERRATA_643719
1062 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1063 depends on CPU_V7 && SMP
1066 This option enables the workaround for the 643719 Cortex-A9 (prior to
1067 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1068 register returns zero when it should return one. The workaround
1069 corrects this value, ensuring cache maintenance operations which use
1070 it behave as intended and avoiding data corruption.
1072 config ARM_ERRATA_720789
1073 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1076 This option enables the workaround for the 720789 Cortex-A9 (prior to
1077 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1078 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1079 As a consequence of this erratum, some TLB entries which should be
1080 invalidated are not, resulting in an incoherency in the system page
1081 tables. The workaround changes the TLB flushing routines to invalidate
1082 entries regardless of the ASID.
1084 config ARM_ERRATA_743622
1085 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1087 depends on !ARCH_MULTIPLATFORM
1089 This option enables the workaround for the 743622 Cortex-A9
1090 (r2p*) erratum. Under very rare conditions, a faulty
1091 optimisation in the Cortex-A9 Store Buffer may lead to data
1092 corruption. This workaround sets a specific bit in the diagnostic
1093 register of the Cortex-A9 which disables the Store Buffer
1094 optimisation, preventing the defect from occurring. This has no
1095 visible impact on the overall performance or power consumption of the
1098 config ARM_ERRATA_751472
1099 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1101 depends on !ARCH_MULTIPLATFORM
1103 This option enables the workaround for the 751472 Cortex-A9 (prior
1104 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1105 completion of a following broadcasted operation if the second
1106 operation is received by a CPU before the ICIALLUIS has completed,
1107 potentially leading to corrupted entries in the cache or TLB.
1109 config ARM_ERRATA_754322
1110 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1113 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1114 r3p*) erratum. A speculative memory access may cause a page table walk
1115 which starts prior to an ASID switch but completes afterwards. This
1116 can populate the micro-TLB with a stale entry which may be hit with
1117 the new ASID. This workaround places two dsb instructions in the mm
1118 switching code so that no page table walks can cross the ASID switch.
1120 config ARM_ERRATA_754327
1121 bool "ARM errata: no automatic Store Buffer drain"
1122 depends on CPU_V7 && SMP
1124 This option enables the workaround for the 754327 Cortex-A9 (prior to
1125 r2p0) erratum. The Store Buffer does not have any automatic draining
1126 mechanism and therefore a livelock may occur if an external agent
1127 continuously polls a memory location waiting to observe an update.
1128 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1129 written polling loops from denying visibility of updates to memory.
1131 config ARM_ERRATA_364296
1132 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1135 This options enables the workaround for the 364296 ARM1136
1136 r0p2 erratum (possible cache data corruption with
1137 hit-under-miss enabled). It sets the undocumented bit 31 in
1138 the auxiliary control register and the FI bit in the control
1139 register, thus disabling hit-under-miss without putting the
1140 processor into full low interrupt latency mode. ARM11MPCore
1143 config ARM_ERRATA_764369
1144 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1145 depends on CPU_V7 && SMP
1147 This option enables the workaround for erratum 764369
1148 affecting Cortex-A9 MPCore with two or more processors (all
1149 current revisions). Under certain timing circumstances, a data
1150 cache line maintenance operation by MVA targeting an Inner
1151 Shareable memory region may fail to proceed up to either the
1152 Point of Coherency or to the Point of Unification of the
1153 system. This workaround adds a DSB instruction before the
1154 relevant cache maintenance functions and sets a specific bit
1155 in the diagnostic control register of the SCU.
1157 config ARM_ERRATA_775420
1158 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1161 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1162 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1163 operation aborts with MMU exception, it might cause the processor
1164 to deadlock. This workaround puts DSB before executing ISB if
1165 an abort may occur on cache maintenance.
1167 config ARM_ERRATA_798181
1168 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1169 depends on CPU_V7 && SMP
1171 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1172 adequately shooting down all use of the old entries. This
1173 option enables the Linux kernel workaround for this erratum
1174 which sends an IPI to the CPUs that are running the same ASID
1175 as the one being invalidated.
1177 config ARM_ERRATA_773022
1178 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1181 This option enables the workaround for the 773022 Cortex-A15
1182 (up to r0p4) erratum. In certain rare sequences of code, the
1183 loop buffer may deliver incorrect instructions. This
1184 workaround disables the loop buffer to avoid the erratum.
1186 config ARM_ERRATA_818325_852422
1187 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1190 This option enables the workaround for:
1191 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1192 instruction might deadlock. Fixed in r0p1.
1193 - Cortex-A12 852422: Execution of a sequence of instructions might
1194 lead to either a data corruption or a CPU deadlock. Not fixed in
1195 any Cortex-A12 cores yet.
1196 This workaround for all both errata involves setting bit[12] of the
1197 Feature Register. This bit disables an optimisation applied to a
1198 sequence of 2 instructions that use opposing condition codes.
1200 config ARM_ERRATA_821420
1201 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1204 This option enables the workaround for the 821420 Cortex-A12
1205 (all revs) erratum. In very rare timing conditions, a sequence
1206 of VMOV to Core registers instructions, for which the second
1207 one is in the shadow of a branch or abort, can lead to a
1208 deadlock when the VMOV instructions are issued out-of-order.
1210 config ARM_ERRATA_825619
1211 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1214 This option enables the workaround for the 825619 Cortex-A12
1215 (all revs) erratum. Within rare timing constraints, executing a
1216 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1217 and Device/Strongly-Ordered loads and stores might cause deadlock
1219 config ARM_ERRATA_852421
1220 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1223 This option enables the workaround for the 852421 Cortex-A17
1224 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1225 execution of a DMB ST instruction might fail to properly order
1226 stores from GroupA and stores from GroupB.
1228 config ARM_ERRATA_852423
1229 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1232 This option enables the workaround for:
1233 - Cortex-A17 852423: Execution of a sequence of instructions might
1234 lead to either a data corruption or a CPU deadlock. Not fixed in
1235 any Cortex-A17 cores yet.
1236 This is identical to Cortex-A12 erratum 852422. It is a separate
1237 config option from the A12 erratum due to the way errata are checked
1242 source "arch/arm/common/Kconfig"
1249 Find out whether you have ISA slots on your motherboard. ISA is the
1250 name of a bus system, i.e. the way the CPU talks to the other stuff
1251 inside your box. Other bus systems are PCI, EISA, MicroChannel
1252 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1253 newer boards don't support it. If you have ISA, say Y, otherwise N.
1255 # Select ISA DMA controller support
1260 # Select ISA DMA interface
1265 bool "PCI support" if MIGHT_HAVE_PCI
1267 Find out whether you have a PCI motherboard. PCI is the name of a
1268 bus system, i.e. the way the CPU talks to the other stuff inside
1269 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1270 VESA. If you have PCI, say Y, otherwise N.
1276 config PCI_DOMAINS_GENERIC
1277 def_bool PCI_DOMAINS
1279 config PCI_NANOENGINE
1280 bool "BSE nanoEngine PCI support"
1281 depends on SA1100_NANOENGINE
1283 Enable PCI on the BSE nanoEngine board.
1288 config PCI_HOST_ITE8152
1290 depends on PCI && MACH_ARMCORE
1294 source "drivers/pci/Kconfig"
1296 source "drivers/pcmcia/Kconfig"
1300 menu "Kernel Features"
1305 This option should be selected by machines which have an SMP-
1308 The only effect of this option is to make the SMP-related
1309 options available to the user for configuration.
1312 bool "Symmetric Multi-Processing"
1313 depends on CPU_V6K || CPU_V7
1314 depends on GENERIC_CLOCKEVENTS
1316 depends on MMU || ARM_MPU
1319 This enables support for systems with more than one CPU. If you have
1320 a system with only one CPU, say N. If you have a system with more
1321 than one CPU, say Y.
1323 If you say N here, the kernel will run on uni- and multiprocessor
1324 machines, but will use only one CPU of a multiprocessor machine. If
1325 you say Y here, the kernel will run on many, but not all,
1326 uniprocessor machines. On a uniprocessor machine, the kernel
1327 will run faster if you say N here.
1329 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1330 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1331 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1333 If you don't know what to do here, say N.
1336 bool "Allow booting SMP kernel on uniprocessor systems"
1337 depends on SMP && !XIP_KERNEL && MMU
1340 SMP kernels contain instructions which fail on non-SMP processors.
1341 Enabling this option allows the kernel to modify itself to make
1342 these instructions safe. Disabling it allows about 1K of space
1345 If you don't know what to do here, say Y.
1347 config ARM_CPU_TOPOLOGY
1348 bool "Support cpu topology definition"
1349 depends on SMP && CPU_V7
1352 Support ARM cpu topology definition. The MPIDR register defines
1353 affinity between processors which is then used to describe the cpu
1354 topology of an ARM System.
1357 bool "Multi-core scheduler support"
1358 depends on ARM_CPU_TOPOLOGY
1360 Multi-core scheduler support improves the CPU scheduler's decision
1361 making when dealing with multi-core CPU chips at a cost of slightly
1362 increased overhead in some places. If unsure say N here.
1365 bool "SMT scheduler support"
1366 depends on ARM_CPU_TOPOLOGY
1368 Improves the CPU scheduler's decision making when dealing with
1369 MultiThreading at a cost of slightly increased overhead in some
1370 places. If unsure say N here.
1375 This option enables support for the ARM system coherency unit
1377 config HAVE_ARM_ARCH_TIMER
1378 bool "Architected timer support"
1380 select ARM_ARCH_TIMER
1381 select GENERIC_CLOCKEVENTS
1383 This option enables support for the ARM architected timer
1387 select CLKSRC_OF if OF
1389 This options enables support for the ARM timer and watchdog unit
1392 bool "Multi-Cluster Power Management"
1393 depends on CPU_V7 && SMP
1395 This option provides the common power management infrastructure
1396 for (multi-)cluster based systems, such as big.LITTLE based
1399 config MCPM_QUAD_CLUSTER
1403 To avoid wasting resources unnecessarily, MCPM only supports up
1404 to 2 clusters by default.
1405 Platforms with 3 or 4 clusters that use MCPM must select this
1406 option to allow the additional clusters to be managed.
1409 bool "big.LITTLE support (Experimental)"
1410 depends on CPU_V7 && SMP
1413 This option enables support selections for the big.LITTLE
1414 system architecture.
1417 bool "big.LITTLE switcher support"
1418 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1421 The big.LITTLE "switcher" provides the core functionality to
1422 transparently handle transition between a cluster of A15's
1423 and a cluster of A7's in a big.LITTLE system.
1425 config BL_SWITCHER_DUMMY_IF
1426 tristate "Simple big.LITTLE switcher user interface"
1427 depends on BL_SWITCHER && DEBUG_KERNEL
1429 This is a simple and dummy char dev interface to control
1430 the big.LITTLE switcher core code. It is meant for
1431 debugging purposes only.
1434 prompt "Memory split"
1438 Select the desired split between kernel and user memory.
1440 If you are not absolutely sure what you are doing, leave this
1444 bool "3G/1G user/kernel split"
1445 config VMSPLIT_3G_OPT
1446 bool "3G/1G user/kernel split (for full 1G low memory)"
1448 bool "2G/2G user/kernel split"
1450 bool "1G/3G user/kernel split"
1455 default PHYS_OFFSET if !MMU
1456 default 0x40000000 if VMSPLIT_1G
1457 default 0x80000000 if VMSPLIT_2G
1458 default 0xB0000000 if VMSPLIT_3G_OPT
1462 int "Maximum number of CPUs (2-32)"
1468 bool "Support for hot-pluggable CPUs"
1471 Say Y here to experiment with turning CPUs off and on. CPUs
1472 can be controlled through /sys/devices/system/cpu.
1475 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1476 depends on HAVE_ARM_SMCCC
1479 Say Y here if you want Linux to communicate with system firmware
1480 implementing the PSCI specification for CPU-centric power
1481 management operations described in ARM document number ARM DEN
1482 0022A ("Power State Coordination Interface System Software on
1485 # The GPIO number here must be sorted by descending number. In case of
1486 # a multiplatform kernel, we just want the highest value required by the
1487 # selected platforms.
1490 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1492 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1493 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1494 default 416 if ARCH_SUNXI
1495 default 392 if ARCH_U8500
1496 default 352 if ARCH_VT8500
1497 default 288 if ARCH_ROCKCHIP
1498 default 264 if MACH_H4700
1501 Maximum number of GPIOs in the system.
1503 If unsure, leave the default value.
1505 source kernel/Kconfig.preempt
1509 default 200 if ARCH_EBSA110
1510 default 128 if SOC_AT91RM9200
1514 depends on HZ_FIXED = 0
1515 prompt "Timer frequency"
1539 default HZ_FIXED if HZ_FIXED != 0
1540 default 100 if HZ_100
1541 default 200 if HZ_200
1542 default 250 if HZ_250
1543 default 300 if HZ_300
1544 default 500 if HZ_500
1548 def_bool HIGH_RES_TIMERS
1550 config THUMB2_KERNEL
1551 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1552 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1553 default y if CPU_THUMBONLY
1555 select ARM_ASM_UNIFIED
1558 By enabling this option, the kernel will be compiled in
1559 Thumb-2 mode. A compiler/assembler that understand the unified
1560 ARM-Thumb syntax is needed.
1564 config THUMB2_AVOID_R_ARM_THM_JUMP11
1565 bool "Work around buggy Thumb-2 short branch relocations in gas"
1566 depends on THUMB2_KERNEL && MODULES
1569 Various binutils versions can resolve Thumb-2 branches to
1570 locally-defined, preemptible global symbols as short-range "b.n"
1571 branch instructions.
1573 This is a problem, because there's no guarantee the final
1574 destination of the symbol, or any candidate locations for a
1575 trampoline, are within range of the branch. For this reason, the
1576 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1577 relocation in modules at all, and it makes little sense to add
1580 The symptom is that the kernel fails with an "unsupported
1581 relocation" error when loading some modules.
1583 Until fixed tools are available, passing
1584 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1585 code which hits this problem, at the cost of a bit of extra runtime
1586 stack usage in some cases.
1588 The problem is described in more detail at:
1589 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1591 Only Thumb-2 kernels are affected.
1593 Unless you are sure your tools don't have this problem, say Y.
1595 config ARM_ASM_UNIFIED
1598 config ARM_PATCH_IDIV
1599 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1600 depends on CPU_32v7 && !XIP_KERNEL
1603 The ARM compiler inserts calls to __aeabi_idiv() and
1604 __aeabi_uidiv() when it needs to perform division on signed
1605 and unsigned integers. Some v7 CPUs have support for the sdiv
1606 and udiv instructions that can be used to implement those
1609 Enabling this option allows the kernel to modify itself to
1610 replace the first two instructions of these library functions
1611 with the sdiv or udiv plus "bx lr" instructions when the CPU
1612 it is running on supports them. Typically this will be faster
1613 and less power intensive than running the original library
1614 code to do integer division.
1617 bool "Use the ARM EABI to compile the kernel"
1619 This option allows for the kernel to be compiled using the latest
1620 ARM ABI (aka EABI). This is only useful if you are using a user
1621 space environment that is also compiled with EABI.
1623 Since there are major incompatibilities between the legacy ABI and
1624 EABI, especially with regard to structure member alignment, this
1625 option also changes the kernel syscall calling convention to
1626 disambiguate both ABIs and allow for backward compatibility support
1627 (selected with CONFIG_OABI_COMPAT).
1629 To use this you need GCC version 4.0.0 or later.
1632 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1633 depends on AEABI && !THUMB2_KERNEL
1635 This option preserves the old syscall interface along with the
1636 new (ARM EABI) one. It also provides a compatibility layer to
1637 intercept syscalls that have structure arguments which layout
1638 in memory differs between the legacy ABI and the new ARM EABI
1639 (only for non "thumb" binaries). This option adds a tiny
1640 overhead to all syscalls and produces a slightly larger kernel.
1642 The seccomp filter system will not be available when this is
1643 selected, since there is no way yet to sensibly distinguish
1644 between calling conventions during filtering.
1646 If you know you'll be using only pure EABI user space then you
1647 can say N here. If this option is not selected and you attempt
1648 to execute a legacy ABI binary then the result will be
1649 UNPREDICTABLE (in fact it can be predicted that it won't work
1650 at all). If in doubt say N.
1652 config ARCH_HAS_HOLES_MEMORYMODEL
1655 config ARCH_SPARSEMEM_ENABLE
1658 config ARCH_SPARSEMEM_DEFAULT
1659 def_bool ARCH_SPARSEMEM_ENABLE
1661 config ARCH_SELECT_MEMORY_MODEL
1662 def_bool ARCH_SPARSEMEM_ENABLE
1664 config HAVE_ARCH_PFN_VALID
1665 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1667 config HAVE_GENERIC_RCU_GUP
1672 bool "High Memory Support"
1675 The address space of ARM processors is only 4 Gigabytes large
1676 and it has to accommodate user address space, kernel address
1677 space as well as some memory mapped IO. That means that, if you
1678 have a large amount of physical memory and/or IO, not all of the
1679 memory can be "permanently mapped" by the kernel. The physical
1680 memory that is not permanently mapped is called "high memory".
1682 Depending on the selected kernel/user memory split, minimum
1683 vmalloc space and actual amount of RAM, you may not need this
1684 option which should result in a slightly faster kernel.
1689 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1693 The VM uses one page of physical memory for each page table.
1694 For systems with a lot of processes, this can use a lot of
1695 precious low memory, eventually leading to low memory being
1696 consumed by page tables. Setting this option will allow
1697 user-space 2nd level page tables to reside in high memory.
1699 config CPU_SW_DOMAIN_PAN
1700 bool "Enable use of CPU domains to implement privileged no-access"
1701 depends on MMU && !ARM_LPAE
1704 Increase kernel security by ensuring that normal kernel accesses
1705 are unable to access userspace addresses. This can help prevent
1706 use-after-free bugs becoming an exploitable privilege escalation
1707 by ensuring that magic values (such as LIST_POISON) will always
1708 fault when dereferenced.
1710 CPUs with low-vector mappings use a best-efforts implementation.
1711 Their lower 1MB needs to remain accessible for the vectors, but
1712 the remainder of userspace will become appropriately inaccessible.
1714 config HW_PERF_EVENTS
1718 config SYS_SUPPORTS_HUGETLBFS
1722 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1726 config ARCH_WANT_GENERAL_HUGETLB
1729 config ARM_MODULE_PLTS
1730 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1733 Allocate PLTs when loading modules so that jumps and calls whose
1734 targets are too far away for their relative offsets to be encoded
1735 in the instructions themselves can be bounced via veneers in the
1736 module's PLT. This allows modules to be allocated in the generic
1737 vmalloc area after the dedicated module memory area has been
1738 exhausted. The modules will use slightly more memory, but after
1739 rounding up to page size, the actual memory footprint is usually
1742 Say y if you are getting out of memory errors while loading modules
1746 config FORCE_MAX_ZONEORDER
1747 int "Maximum zone order"
1748 default "12" if SOC_AM33XX
1749 default "9" if SA1111 || ARCH_EFM32
1752 The kernel memory allocator divides physically contiguous memory
1753 blocks into "zones", where each zone is a power of two number of
1754 pages. This option selects the largest power of two that the kernel
1755 keeps in the memory allocator. If you need to allocate very large
1756 blocks of physically contiguous memory, then you may need to
1757 increase this value.
1759 This config option is actually maximum order plus one. For example,
1760 a value of 11 means that the largest free memory block is 2^10 pages.
1762 config ALIGNMENT_TRAP
1764 depends on CPU_CP15_MMU
1765 default y if !ARCH_EBSA110
1766 select HAVE_PROC_CPU if PROC_FS
1768 ARM processors cannot fetch/store information which is not
1769 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1770 address divisible by 4. On 32-bit ARM processors, these non-aligned
1771 fetch/store instructions will be emulated in software if you say
1772 here, which has a severe performance impact. This is necessary for
1773 correct operation of some network protocols. With an IP-only
1774 configuration it is safe to say N, otherwise say Y.
1776 config UACCESS_WITH_MEMCPY
1777 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1779 default y if CPU_FEROCEON
1781 Implement faster copy_to_user and clear_user methods for CPU
1782 cores where a 8-word STM instruction give significantly higher
1783 memory write throughput than a sequence of individual 32bit stores.
1785 A possible side effect is a slight increase in scheduling latency
1786 between threads sharing the same address space if they invoke
1787 such copy operations with large buffers.
1789 However, if the CPU data cache is using a write-allocate mode,
1790 this option is unlikely to provide any performance gain.
1794 prompt "Enable seccomp to safely compute untrusted bytecode"
1796 This kernel feature is useful for number crunching applications
1797 that may need to compute untrusted bytecode during their
1798 execution. By using pipes or other transports made available to
1799 the process as file descriptors supporting the read/write
1800 syscalls, it's possible to isolate those applications in
1801 their own address space using seccomp. Once seccomp is
1802 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1803 and the task is only allowed to execute a few safe syscalls
1804 defined by each seccomp mode.
1813 bool "Enable paravirtualization code"
1815 This changes the kernel so it can modify itself when it is run
1816 under a hypervisor, potentially improving performance significantly
1817 over full virtualization.
1819 config PARAVIRT_TIME_ACCOUNTING
1820 bool "Paravirtual steal time accounting"
1824 Select this option to enable fine granularity task steal time
1825 accounting. Time spent executing other tasks in parallel with
1826 the current vCPU is discounted from the vCPU power. To account for
1827 that, there can be a small performance impact.
1829 If in doubt, say N here.
1836 bool "Xen guest support on ARM"
1837 depends on ARM && AEABI && OF
1838 depends on CPU_V7 && !CPU_V6
1839 depends on !GENERIC_ATOMIC64
1841 select ARCH_DMA_ADDR_T_64BIT
1846 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1853 bool "Flattened Device Tree support"
1857 Include support for flattened device tree machine descriptions.
1860 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1863 This is the traditional way of passing data to the kernel at boot
1864 time. If you are solely relying on the flattened device tree (or
1865 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1866 to remove ATAGS support from your kernel binary. If unsure,
1869 config DEPRECATED_PARAM_STRUCT
1870 bool "Provide old way to pass kernel parameters"
1873 This was deprecated in 2001 and announced to live on for 5 years.
1874 Some old boot loaders still use this way.
1876 # Compressed boot loader in ROM. Yes, we really want to ask about
1877 # TEXT and BSS so we preserve their values in the config files.
1878 config ZBOOT_ROM_TEXT
1879 hex "Compressed ROM boot loader base address"
1882 The physical address at which the ROM-able zImage is to be
1883 placed in the target. Platforms which normally make use of
1884 ROM-able zImage formats normally set this to a suitable
1885 value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1889 config ZBOOT_ROM_BSS
1890 hex "Compressed ROM boot loader BSS address"
1893 The base address of an area of read/write memory in the target
1894 for the ROM-able zImage which must be available while the
1895 decompressor is running. It must be large enough to hold the
1896 entire decompressed kernel plus an additional 128 KiB.
1897 Platforms which normally make use of ROM-able zImage formats
1898 normally set this to a suitable value in their defconfig file.
1900 If ZBOOT_ROM is not enabled, this has no effect.
1903 bool "Compressed boot loader in ROM/flash"
1904 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1905 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1907 Say Y here if you intend to execute your compressed kernel image
1908 (zImage) directly from ROM or flash. If unsure, say N.
1910 config ARM_APPENDED_DTB
1911 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1914 With this option, the boot code will look for a device tree binary
1915 (DTB) appended to zImage
1916 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1918 This is meant as a backward compatibility convenience for those
1919 systems with a bootloader that can't be upgraded to accommodate
1920 the documented boot protocol using a device tree.
1922 Beware that there is very little in terms of protection against
1923 this option being confused by leftover garbage in memory that might
1924 look like a DTB header after a reboot if no actual DTB is appended
1925 to zImage. Do not leave this option active in a production kernel
1926 if you don't intend to always append a DTB. Proper passing of the
1927 location into r2 of a bootloader provided DTB is always preferable
1930 config ARM_ATAG_DTB_COMPAT
1931 bool "Supplement the appended DTB with traditional ATAG information"
1932 depends on ARM_APPENDED_DTB
1934 Some old bootloaders can't be updated to a DTB capable one, yet
1935 they provide ATAGs with memory configuration, the ramdisk address,
1936 the kernel cmdline string, etc. Such information is dynamically
1937 provided by the bootloader and can't always be stored in a static
1938 DTB. To allow a device tree enabled kernel to be used with such
1939 bootloaders, this option allows zImage to extract the information
1940 from the ATAG list and store it at run time into the appended DTB.
1943 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1944 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1946 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1947 bool "Use bootloader kernel arguments if available"
1949 Uses the command-line options passed by the boot loader instead of
1950 the device tree bootargs property. If the boot loader doesn't provide
1951 any, the device tree bootargs property will be used.
1953 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1954 bool "Extend with bootloader kernel arguments"
1956 The command-line arguments provided by the boot loader will be
1957 appended to the the device tree bootargs property.
1962 string "Default kernel command string"
1965 On some architectures (EBSA110 and CATS), there is currently no way
1966 for the boot loader to pass arguments to the kernel. For these
1967 architectures, you should supply some command-line options at build
1968 time by entering them here. As a minimum, you should specify the
1969 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1972 prompt "Kernel command line type" if CMDLINE != ""
1973 default CMDLINE_FROM_BOOTLOADER
1976 config CMDLINE_FROM_BOOTLOADER
1977 bool "Use bootloader kernel arguments if available"
1979 Uses the command-line options passed by the boot loader. If
1980 the boot loader doesn't provide any, the default kernel command
1981 string provided in CMDLINE will be used.
1983 config CMDLINE_EXTEND
1984 bool "Extend bootloader kernel arguments"
1986 The command-line arguments provided by the boot loader will be
1987 appended to the default kernel command string.
1989 config CMDLINE_FORCE
1990 bool "Always use the default kernel command string"
1992 Always use the default kernel command string, even if the boot
1993 loader passes other arguments to the kernel.
1994 This is useful if you cannot or don't want to change the
1995 command-line options your boot loader passes to the kernel.
1999 bool "Kernel Execute-In-Place from ROM"
2000 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2002 Execute-In-Place allows the kernel to run from non-volatile storage
2003 directly addressable by the CPU, such as NOR flash. This saves RAM
2004 space since the text section of the kernel is not loaded from flash
2005 to RAM. Read-write sections, such as the data section and stack,
2006 are still copied to RAM. The XIP kernel is not compressed since
2007 it has to run directly from flash, so it will take more space to
2008 store it. The flash address used to link the kernel object files,
2009 and for storing it, is configuration dependent. Therefore, if you
2010 say Y here, you must know the proper physical address where to
2011 store the kernel image depending on your own flash memory usage.
2013 Also note that the make target becomes "make xipImage" rather than
2014 "make zImage" or "make Image". The final kernel binary to put in
2015 ROM memory will be arch/arm/boot/xipImage.
2019 config XIP_PHYS_ADDR
2020 hex "XIP Kernel Physical Location"
2021 depends on XIP_KERNEL
2022 default "0x00080000"
2024 This is the physical address in your flash memory the kernel will
2025 be linked for and stored to. This address is dependent on your
2029 bool "Kexec system call (EXPERIMENTAL)"
2030 depends on (!SMP || PM_SLEEP_SMP)
2034 kexec is a system call that implements the ability to shutdown your
2035 current kernel, and to start another kernel. It is like a reboot
2036 but it is independent of the system firmware. And like a reboot
2037 you can start any kernel with it, not just Linux.
2039 It is an ongoing process to be certain the hardware in a machine
2040 is properly shutdown, so do not be surprised if this code does not
2041 initially work for you.
2044 bool "Export atags in procfs"
2045 depends on ATAGS && KEXEC
2048 Should the atags used to boot the kernel be exported in an "atags"
2049 file in procfs. Useful with kexec.
2052 bool "Build kdump crash kernel (EXPERIMENTAL)"
2054 Generate crash dump after being started by kexec. This should
2055 be normally only set in special crash dump kernels which are
2056 loaded in the main kernel with kexec-tools into a specially
2057 reserved region and then later executed after a crash by
2058 kdump/kexec. The crash dump kernel must be compiled to a
2059 memory address not used by the main kernel
2061 For more details see Documentation/kdump/kdump.txt
2063 config AUTO_ZRELADDR
2064 bool "Auto calculation of the decompressed kernel image address"
2066 ZRELADDR is the physical address where the decompressed kernel
2067 image will be placed. If AUTO_ZRELADDR is selected, the address
2068 will be determined at run-time by masking the current IP with
2069 0xf8000000. This assumes the zImage being placed in the first 128MB
2070 from start of memory.
2076 bool "UEFI runtime support"
2077 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2079 select EFI_PARAMS_FROM_FDT
2082 select EFI_RUNTIME_WRAPPERS
2084 This option provides support for runtime services provided
2085 by UEFI firmware (such as non-volatile variables, realtime
2086 clock, and platform reset). A UEFI stub is also provided to
2087 allow the kernel to be booted as an EFI application. This
2088 is only useful for kernels that may run on systems that have
2093 menu "CPU Power Management"
2095 source "drivers/cpufreq/Kconfig"
2097 source "drivers/cpuidle/Kconfig"
2101 menu "Floating point emulation"
2103 comment "At least one emulation must be selected"
2106 bool "NWFPE math emulation"
2107 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2109 Say Y to include the NWFPE floating point emulator in the kernel.
2110 This is necessary to run most binaries. Linux does not currently
2111 support floating point hardware so you need to say Y here even if
2112 your machine has an FPA or floating point co-processor podule.
2114 You may say N here if you are going to load the Acorn FPEmulator
2115 early in the bootup.
2118 bool "Support extended precision"
2119 depends on FPE_NWFPE
2121 Say Y to include 80-bit support in the kernel floating-point
2122 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2123 Note that gcc does not generate 80-bit operations by default,
2124 so in most cases this option only enlarges the size of the
2125 floating point emulator without any good reason.
2127 You almost surely want to say N here.
2130 bool "FastFPE math emulation (EXPERIMENTAL)"
2131 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2133 Say Y here to include the FAST floating point emulator in the kernel.
2134 This is an experimental much faster emulator which now also has full
2135 precision for the mantissa. It does not support any exceptions.
2136 It is very simple, and approximately 3-6 times faster than NWFPE.
2138 It should be sufficient for most programs. It may be not suitable
2139 for scientific calculations, but you have to check this for yourself.
2140 If you do not feel you need a faster FP emulation you should better
2144 bool "VFP-format floating point maths"
2145 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2147 Say Y to include VFP support code in the kernel. This is needed
2148 if your hardware includes a VFP unit.
2150 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2151 release notes and additional status information.
2153 Say N if your target does not have VFP hardware.
2161 bool "Advanced SIMD (NEON) Extension support"
2162 depends on VFPv3 && CPU_V7
2164 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2167 config KERNEL_MODE_NEON
2168 bool "Support for NEON in kernel mode"
2169 depends on NEON && AEABI
2171 Say Y to include support for NEON in kernel mode.
2175 menu "Userspace binary formats"
2177 source "fs/Kconfig.binfmt"
2181 menu "Power management options"
2183 source "kernel/power/Kconfig"
2185 config ARCH_SUSPEND_POSSIBLE
2186 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2187 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2190 config ARM_CPU_SUSPEND
2191 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2192 depends on ARCH_SUSPEND_POSSIBLE
2194 config ARCH_HIBERNATION_POSSIBLE
2197 default y if ARCH_SUSPEND_POSSIBLE
2201 source "net/Kconfig"
2203 source "drivers/Kconfig"
2205 source "drivers/firmware/Kconfig"
2209 source "arch/arm/Kconfig.debug"
2211 source "security/Kconfig"
2213 source "crypto/Kconfig"
2215 source "arch/arm/crypto/Kconfig"
2218 source "lib/Kconfig"
2220 source "arch/arm/kvm/Kconfig"