4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
52 select HAVE_VIRT_TO_BUS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
416 Support for the Cortina Systems Gemini family SoCs
420 select ARCH_REQUIRE_GPIOLIB
423 select GENERIC_CLOCKEVENTS
424 select GENERIC_IRQ_CHIP
425 select MIGHT_HAVE_CACHE_L2X0
431 Support for CSR SiRFprimaII/Marco/Polo platforms
435 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
442 This is an evaluation board for the StrongARM processor available
443 from Digital. It has limited hardware on-board, including an
444 Ethernet interface, two PCMCIA sockets, two serial ports and a
449 select ARCH_HAS_HOLES_MEMORYMODEL
450 select ARCH_REQUIRE_GPIOLIB
451 select ARCH_USES_GETTIMEOFFSET
456 select NEED_MACH_MEMORY_H
458 This enables support for the Cirrus EP93xx series of CPUs.
460 config ARCH_FOOTBRIDGE
464 select GENERIC_CLOCKEVENTS
466 select NEED_MACH_IO_H if !MMU
467 select NEED_MACH_MEMORY_H
469 Support for systems based on the DC21285 companion chip
470 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
473 bool "Freescale MXS-based"
474 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
479 select HAVE_CLK_PREPARE
480 select MULTI_IRQ_HANDLER
485 Support for Freescale MXS-based family of processors
488 bool "Hilscher NetX based"
492 select GENERIC_CLOCKEVENTS
494 This enables support for systems based on the Hilscher NetX Soc
497 bool "Hynix HMS720x-based"
498 select ARCH_USES_GETTIMEOFFSET
502 This enables support for systems based on the Hynix HMS720x
507 select ARCH_SUPPORTS_MSI
509 select NEED_MACH_MEMORY_H
510 select NEED_RET_TO_USER
515 Support for Intel's IOP13XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
522 select NEED_MACH_GPIO_H
523 select NEED_RET_TO_USER
527 Support for Intel's 80219 and IOP32X (XScale) family of
533 select ARCH_REQUIRE_GPIOLIB
535 select NEED_MACH_GPIO_H
536 select NEED_RET_TO_USER
540 Support for Intel's IOP33X (XScale) family of processors.
545 select ARCH_HAS_DMA_SET_COHERENT_MASK
546 select ARCH_REQUIRE_GPIOLIB
549 select DMABOUNCE if PCI
550 select GENERIC_CLOCKEVENTS
551 select MIGHT_HAVE_PCI
552 select NEED_MACH_IO_H
554 Support for Intel's IXP4XX (XScale) family of processors.
558 select ARCH_REQUIRE_GPIOLIB
559 select COMMON_CLK_DOVE
561 select GENERIC_CLOCKEVENTS
562 select MIGHT_HAVE_PCI
565 select PLAT_ORION_LEGACY
566 select USB_ARCH_HAS_EHCI
568 Support for the Marvell Dove SoC 88AP510
571 bool "Marvell Kirkwood"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
578 select PINCTRL_KIRKWOOD
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Kirkwood series SoCs:
582 88F6180, 88F6192 and 88F6281.
585 bool "Marvell MV78xx0"
586 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
590 select PLAT_ORION_LEGACY
592 Support for the following Marvell MV78xx0 series SoCs:
598 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
602 select PLAT_ORION_LEGACY
604 Support for the following Marvell Orion 5x series SoCs:
605 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
606 Orion-2 (5281), Orion-1-90 (6183).
609 bool "Marvell PXA168/910/MMP2"
611 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_ALLOCATOR
614 select GENERIC_CLOCKEVENTS
617 select NEED_MACH_GPIO_H
622 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
625 bool "Micrel/Kendin KS8695"
626 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
630 select NEED_MACH_MEMORY_H
632 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
633 System-on-Chip devices.
636 bool "Nuvoton W90X900 CPU"
637 select ARCH_REQUIRE_GPIOLIB
641 select GENERIC_CLOCKEVENTS
643 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
644 At present, the w90x900 has been renamed nuc900, regarding
645 the ARM series product line, you can login the following
646 link address to know more.
648 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
649 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
653 select ARCH_REQUIRE_GPIOLIB
658 select GENERIC_CLOCKEVENTS
661 select USB_ARCH_HAS_OHCI
664 Support for the NXP LPC32XX family of processors
668 select ARCH_HAS_CPUFREQ
669 select ARCH_REQUIRE_GPIOLIB
674 select GENERIC_CLOCKEVENTS
677 select MIGHT_HAVE_CACHE_L2X0
681 This enables support for NVIDIA Tegra based systems (Tegra APX,
682 Tegra 6xx and Tegra 2 series).
685 bool "PXA2xx/PXA3xx-based"
687 select ARCH_HAS_CPUFREQ
689 select ARCH_REQUIRE_GPIOLIB
690 select ARM_CPU_SUSPEND if PM
694 select GENERIC_CLOCKEVENTS
697 select MULTI_IRQ_HANDLER
698 select NEED_MACH_GPIO_H
702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
706 select ARCH_REQUIRE_GPIOLIB
708 select GENERIC_CLOCKEVENTS
711 Support for Qualcomm MSM/QSD based systems. This runs on the
712 apps processor of the MSM/QSD and depends on a shared memory
713 interface to the modem processor which runs the baseband
714 stack and controls some vital subsystems
715 (clock and power control, etc).
718 bool "Renesas SH-Mobile / R-Mobile"
720 select GENERIC_CLOCKEVENTS
722 select HAVE_MACH_CLKDEV
724 select MIGHT_HAVE_CACHE_L2X0
725 select MULTI_IRQ_HANDLER
726 select NEED_MACH_MEMORY_H
729 select PM_GENERIC_DOMAINS if PM
732 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
737 select ARCH_MAY_HAVE_PC_FDC
738 select ARCH_SPARSEMEM_ENABLE
739 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_PATA_PLATFORM
744 select NEED_MACH_IO_H
745 select NEED_MACH_MEMORY_H
748 On the Acorn Risc-PC, Linux can support the internal IDE disk and
749 CD-ROM interface, serial and parallel port, and the floppy drive.
753 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
756 select ARCH_SPARSEMEM_ENABLE
761 select GENERIC_CLOCKEVENTS
764 select NEED_MACH_GPIO_H
765 select NEED_MACH_MEMORY_H
768 Support for StrongARM 11x0 based boards.
771 bool "Samsung S3C24XX SoCs"
772 select ARCH_HAS_CPUFREQ
775 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
782 select NEED_MACH_IO_H
784 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
785 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
786 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
787 Samsung SMDK2410 development board (and derivatives).
790 bool "Samsung S3C64XX"
791 select ARCH_HAS_CPUFREQ
792 select ARCH_REQUIRE_GPIOLIB
797 select GENERIC_CLOCKEVENTS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 select NEED_MACH_GPIO_H
806 select S3C_GPIO_TRACK
807 select SAMSUNG_CLKSRC
808 select SAMSUNG_GPIOLIB_4BIT
809 select SAMSUNG_IRQ_VIC_TIMER
810 select USB_ARCH_HAS_OHCI
812 Samsung S3C64XX series based systems
815 bool "Samsung S5P6440 S5P6450"
819 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
826 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
830 bool "Samsung S5PC100"
834 select GENERIC_CLOCKEVENTS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select HAVE_S3C_RTC if RTC_CLASS
840 select NEED_MACH_GPIO_H
842 Samsung S5PC100 series based systems
845 bool "Samsung S5PV210/S5PC110"
846 select ARCH_HAS_CPUFREQ
847 select ARCH_HAS_HOLES_MEMORYMODEL
848 select ARCH_SPARSEMEM_ENABLE
852 select GENERIC_CLOCKEVENTS
854 select HAVE_S3C2410_I2C if I2C
855 select HAVE_S3C2410_WATCHDOG if WATCHDOG
856 select HAVE_S3C_RTC if RTC_CLASS
857 select NEED_MACH_GPIO_H
858 select NEED_MACH_MEMORY_H
860 Samsung S5PV210/S5PC110 series based systems
863 bool "Samsung EXYNOS"
864 select ARCH_HAS_CPUFREQ
865 select ARCH_HAS_HOLES_MEMORYMODEL
866 select ARCH_SPARSEMEM_ENABLE
869 select GENERIC_CLOCKEVENTS
871 select HAVE_S3C2410_I2C if I2C
872 select HAVE_S3C2410_WATCHDOG if WATCHDOG
873 select HAVE_S3C_RTC if RTC_CLASS
874 select NEED_MACH_GPIO_H
875 select NEED_MACH_MEMORY_H
877 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
881 select ARCH_USES_GETTIMEOFFSET
885 select NEED_MACH_MEMORY_H
889 Support for the StrongARM based Digital DNARD machine, also known
890 as "Shark" (<http://www.shark-linux.de/shark.html>).
893 bool "ST-Ericsson U300 Series"
895 select ARCH_REQUIRE_GPIOLIB
897 select ARM_PATCH_PHYS_VIRT
903 select GENERIC_CLOCKEVENTS
907 Support for ST-Ericsson U300 series mobile platforms.
910 bool "ST-Ericsson U8500 Series"
912 select ARCH_HAS_CPUFREQ
913 select ARCH_REQUIRE_GPIOLIB
917 select GENERIC_CLOCKEVENTS
919 select MIGHT_HAVE_CACHE_L2X0
922 Support for ST-Ericsson's Ux500 architecture
925 bool "STMicroelectronics Nomadik"
926 select ARCH_REQUIRE_GPIOLIB
929 select CLKSRC_NOMADIK_MTU
932 select GENERIC_CLOCKEVENTS
933 select MIGHT_HAVE_CACHE_L2X0
936 select PINCTRL_STN8815
939 Support for the Nomadik platform by ST-Ericsson
943 select ARCH_HAS_CPUFREQ
944 select ARCH_REQUIRE_GPIOLIB
949 select GENERIC_CLOCKEVENTS
952 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
956 select ARCH_HAS_HOLES_MEMORYMODEL
957 select ARCH_REQUIRE_GPIOLIB
959 select GENERIC_ALLOCATOR
960 select GENERIC_CLOCKEVENTS
961 select GENERIC_IRQ_CHIP
963 select NEED_MACH_GPIO_H
967 Support for TI's DaVinci platform.
972 select ARCH_HAS_CPUFREQ
973 select ARCH_HAS_HOLES_MEMORYMODEL
975 select ARCH_REQUIRE_GPIOLIB
978 select GENERIC_CLOCKEVENTS
979 select GENERIC_IRQ_CHIP
983 select NEED_MACH_IO_H if PCCARD
984 select NEED_MACH_MEMORY_H
986 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
990 menu "Multiple platform selection"
991 depends on ARCH_MULTIPLATFORM
993 comment "CPU Core family selection"
996 bool "ARMv4 based platforms (FA526, StrongARM)"
997 depends on !ARCH_MULTI_V6_V7
998 select ARCH_MULTI_V4_V5
1000 config ARCH_MULTI_V4T
1001 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1002 depends on !ARCH_MULTI_V6_V7
1003 select ARCH_MULTI_V4_V5
1005 config ARCH_MULTI_V5
1006 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1007 depends on !ARCH_MULTI_V6_V7
1008 select ARCH_MULTI_V4_V5
1010 config ARCH_MULTI_V4_V5
1013 config ARCH_MULTI_V6
1014 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1015 select ARCH_MULTI_V6_V7
1018 config ARCH_MULTI_V7
1019 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1021 select ARCH_MULTI_V6_V7
1022 select ARCH_VEXPRESS
1025 config ARCH_MULTI_V6_V7
1028 config ARCH_MULTI_CPU_AUTO
1029 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1030 select ARCH_MULTI_V5
1035 # This is sorted alphabetically by mach-* pathname. However, plat-*
1036 # Kconfigs may be included either alphabetically (according to the
1037 # plat- suffix) or along side the corresponding mach-* source.
1039 source "arch/arm/mach-mvebu/Kconfig"
1041 source "arch/arm/mach-at91/Kconfig"
1043 source "arch/arm/mach-bcm/Kconfig"
1045 source "arch/arm/mach-clps711x/Kconfig"
1047 source "arch/arm/mach-cns3xxx/Kconfig"
1049 source "arch/arm/mach-davinci/Kconfig"
1051 source "arch/arm/mach-dove/Kconfig"
1053 source "arch/arm/mach-ep93xx/Kconfig"
1055 source "arch/arm/mach-footbridge/Kconfig"
1057 source "arch/arm/mach-gemini/Kconfig"
1059 source "arch/arm/mach-h720x/Kconfig"
1061 source "arch/arm/mach-highbank/Kconfig"
1063 source "arch/arm/mach-integrator/Kconfig"
1065 source "arch/arm/mach-iop32x/Kconfig"
1067 source "arch/arm/mach-iop33x/Kconfig"
1069 source "arch/arm/mach-iop13xx/Kconfig"
1071 source "arch/arm/mach-ixp4xx/Kconfig"
1073 source "arch/arm/mach-kirkwood/Kconfig"
1075 source "arch/arm/mach-ks8695/Kconfig"
1077 source "arch/arm/mach-msm/Kconfig"
1079 source "arch/arm/mach-mv78xx0/Kconfig"
1081 source "arch/arm/mach-imx/Kconfig"
1083 source "arch/arm/mach-mxs/Kconfig"
1085 source "arch/arm/mach-netx/Kconfig"
1087 source "arch/arm/mach-nomadik/Kconfig"
1089 source "arch/arm/plat-omap/Kconfig"
1091 source "arch/arm/mach-omap1/Kconfig"
1093 source "arch/arm/mach-omap2/Kconfig"
1095 source "arch/arm/mach-orion5x/Kconfig"
1097 source "arch/arm/mach-picoxcell/Kconfig"
1099 source "arch/arm/mach-pxa/Kconfig"
1100 source "arch/arm/plat-pxa/Kconfig"
1102 source "arch/arm/mach-mmp/Kconfig"
1104 source "arch/arm/mach-realview/Kconfig"
1106 source "arch/arm/mach-sa1100/Kconfig"
1108 source "arch/arm/plat-samsung/Kconfig"
1110 source "arch/arm/mach-socfpga/Kconfig"
1112 source "arch/arm/plat-spear/Kconfig"
1114 source "arch/arm/mach-s3c24xx/Kconfig"
1117 source "arch/arm/mach-s3c64xx/Kconfig"
1120 source "arch/arm/mach-s5p64x0/Kconfig"
1122 source "arch/arm/mach-s5pc100/Kconfig"
1124 source "arch/arm/mach-s5pv210/Kconfig"
1126 source "arch/arm/mach-exynos/Kconfig"
1128 source "arch/arm/mach-shmobile/Kconfig"
1130 source "arch/arm/mach-sunxi/Kconfig"
1132 source "arch/arm/mach-prima2/Kconfig"
1134 source "arch/arm/mach-tegra/Kconfig"
1136 source "arch/arm/mach-u300/Kconfig"
1138 source "arch/arm/mach-ux500/Kconfig"
1140 source "arch/arm/mach-versatile/Kconfig"
1142 source "arch/arm/mach-vexpress/Kconfig"
1143 source "arch/arm/plat-versatile/Kconfig"
1145 source "arch/arm/mach-virt/Kconfig"
1147 source "arch/arm/mach-vt8500/Kconfig"
1149 source "arch/arm/mach-w90x900/Kconfig"
1151 source "arch/arm/mach-zynq/Kconfig"
1153 # Definitions to make life easier
1159 select GENERIC_CLOCKEVENTS
1165 select GENERIC_IRQ_CHIP
1168 config PLAT_ORION_LEGACY
1175 config PLAT_VERSATILE
1178 config ARM_TIMER_SP804
1181 select HAVE_SCHED_CLOCK
1183 source arch/arm/mm/Kconfig
1187 default 16 if ARCH_EP93XX
1191 bool "Enable iWMMXt support"
1192 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1193 default y if PXA27x || PXA3xx || ARCH_MMP
1195 Enable support for iWMMXt context switching at run time if
1196 running on a CPU that supports it.
1200 depends on CPU_XSCALE
1203 config MULTI_IRQ_HANDLER
1206 Allow each machine to specify it's own IRQ handler at run time.
1209 source "arch/arm/Kconfig-nommu"
1212 config ARM_ERRATA_326103
1213 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1216 Executing a SWP instruction to read-only memory does not set bit 11
1217 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1218 treat the access as a read, preventing a COW from occurring and
1219 causing the faulting task to livelock.
1221 config ARM_ERRATA_411920
1222 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1223 depends on CPU_V6 || CPU_V6K
1225 Invalidation of the Instruction Cache operation can
1226 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1227 It does not affect the MPCore. This option enables the ARM Ltd.
1228 recommended workaround.
1230 config ARM_ERRATA_430973
1231 bool "ARM errata: Stale prediction on replaced interworking branch"
1234 This option enables the workaround for the 430973 Cortex-A8
1235 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1236 interworking branch is replaced with another code sequence at the
1237 same virtual address, whether due to self-modifying code or virtual
1238 to physical address re-mapping, Cortex-A8 does not recover from the
1239 stale interworking branch prediction. This results in Cortex-A8
1240 executing the new code sequence in the incorrect ARM or Thumb state.
1241 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1242 and also flushes the branch target cache at every context switch.
1243 Note that setting specific bits in the ACTLR register may not be
1244 available in non-secure mode.
1246 config ARM_ERRATA_458693
1247 bool "ARM errata: Processor deadlock when a false hazard is created"
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1252 erratum. For very specific sequences of memory operations, it is
1253 possible for a hazard condition intended for a cache line to instead
1254 be incorrectly associated with a different cache line. This false
1255 hazard might then cause a processor deadlock. The workaround enables
1256 the L1 caching of the NEON accesses and disables the PLD instruction
1257 in the ACTLR register. Note that setting specific bits in the ACTLR
1258 register may not be available in non-secure mode.
1260 config ARM_ERRATA_460075
1261 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1263 depends on !ARCH_MULTIPLATFORM
1265 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1266 erratum. Any asynchronous access to the L2 cache may encounter a
1267 situation in which recent store transactions to the L2 cache are lost
1268 and overwritten with stale memory contents from external memory. The
1269 workaround disables the write-allocate mode for the L2 cache via the
1270 ACTLR register. Note that setting specific bits in the ACTLR register
1271 may not be available in non-secure mode.
1273 config ARM_ERRATA_742230
1274 bool "ARM errata: DMB operation may be faulty"
1275 depends on CPU_V7 && SMP
1276 depends on !ARCH_MULTIPLATFORM
1278 This option enables the workaround for the 742230 Cortex-A9
1279 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1280 between two write operations may not ensure the correct visibility
1281 ordering of the two writes. This workaround sets a specific bit in
1282 the diagnostic register of the Cortex-A9 which causes the DMB
1283 instruction to behave as a DSB, ensuring the correct behaviour of
1286 config ARM_ERRATA_742231
1287 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1288 depends on CPU_V7 && SMP
1289 depends on !ARCH_MULTIPLATFORM
1291 This option enables the workaround for the 742231 Cortex-A9
1292 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1293 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1294 accessing some data located in the same cache line, may get corrupted
1295 data due to bad handling of the address hazard when the line gets
1296 replaced from one of the CPUs at the same time as another CPU is
1297 accessing it. This workaround sets specific bits in the diagnostic
1298 register of the Cortex-A9 which reduces the linefill issuing
1299 capabilities of the processor.
1301 config PL310_ERRATA_588369
1302 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1303 depends on CACHE_L2X0
1305 The PL310 L2 cache controller implements three types of Clean &
1306 Invalidate maintenance operations: by Physical Address
1307 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1308 They are architecturally defined to behave as the execution of a
1309 clean operation followed immediately by an invalidate operation,
1310 both performing to the same memory location. This functionality
1311 is not correctly implemented in PL310 as clean lines are not
1312 invalidated as a result of these operations.
1314 config ARM_ERRATA_720789
1315 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1318 This option enables the workaround for the 720789 Cortex-A9 (prior to
1319 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1320 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1321 As a consequence of this erratum, some TLB entries which should be
1322 invalidated are not, resulting in an incoherency in the system page
1323 tables. The workaround changes the TLB flushing routines to invalidate
1324 entries regardless of the ASID.
1326 config PL310_ERRATA_727915
1327 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1328 depends on CACHE_L2X0
1330 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1331 operation (offset 0x7FC). This operation runs in background so that
1332 PL310 can handle normal accesses while it is in progress. Under very
1333 rare circumstances, due to this erratum, write data can be lost when
1334 PL310 treats a cacheable write transaction during a Clean &
1335 Invalidate by Way operation.
1337 config ARM_ERRATA_743622
1338 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1340 depends on !ARCH_MULTIPLATFORM
1342 This option enables the workaround for the 743622 Cortex-A9
1343 (r2p*) erratum. Under very rare conditions, a faulty
1344 optimisation in the Cortex-A9 Store Buffer may lead to data
1345 corruption. This workaround sets a specific bit in the diagnostic
1346 register of the Cortex-A9 which disables the Store Buffer
1347 optimisation, preventing the defect from occurring. This has no
1348 visible impact on the overall performance or power consumption of the
1351 config ARM_ERRATA_751472
1352 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1354 depends on !ARCH_MULTIPLATFORM
1356 This option enables the workaround for the 751472 Cortex-A9 (prior
1357 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1358 completion of a following broadcasted operation if the second
1359 operation is received by a CPU before the ICIALLUIS has completed,
1360 potentially leading to corrupted entries in the cache or TLB.
1362 config PL310_ERRATA_753970
1363 bool "PL310 errata: cache sync operation may be faulty"
1364 depends on CACHE_PL310
1366 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1368 Under some condition the effect of cache sync operation on
1369 the store buffer still remains when the operation completes.
1370 This means that the store buffer is always asked to drain and
1371 this prevents it from merging any further writes. The workaround
1372 is to replace the normal offset of cache sync operation (0x730)
1373 by another offset targeting an unmapped PL310 register 0x740.
1374 This has the same effect as the cache sync operation: store buffer
1375 drain and waiting for all buffers empty.
1377 config ARM_ERRATA_754322
1378 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1381 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1382 r3p*) erratum. A speculative memory access may cause a page table walk
1383 which starts prior to an ASID switch but completes afterwards. This
1384 can populate the micro-TLB with a stale entry which may be hit with
1385 the new ASID. This workaround places two dsb instructions in the mm
1386 switching code so that no page table walks can cross the ASID switch.
1388 config ARM_ERRATA_754327
1389 bool "ARM errata: no automatic Store Buffer drain"
1390 depends on CPU_V7 && SMP
1392 This option enables the workaround for the 754327 Cortex-A9 (prior to
1393 r2p0) erratum. The Store Buffer does not have any automatic draining
1394 mechanism and therefore a livelock may occur if an external agent
1395 continuously polls a memory location waiting to observe an update.
1396 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1397 written polling loops from denying visibility of updates to memory.
1399 config ARM_ERRATA_364296
1400 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1401 depends on CPU_V6 && !SMP
1403 This options enables the workaround for the 364296 ARM1136
1404 r0p2 erratum (possible cache data corruption with
1405 hit-under-miss enabled). It sets the undocumented bit 31 in
1406 the auxiliary control register and the FI bit in the control
1407 register, thus disabling hit-under-miss without putting the
1408 processor into full low interrupt latency mode. ARM11MPCore
1411 config ARM_ERRATA_764369
1412 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1413 depends on CPU_V7 && SMP
1415 This option enables the workaround for erratum 764369
1416 affecting Cortex-A9 MPCore with two or more processors (all
1417 current revisions). Under certain timing circumstances, a data
1418 cache line maintenance operation by MVA targeting an Inner
1419 Shareable memory region may fail to proceed up to either the
1420 Point of Coherency or to the Point of Unification of the
1421 system. This workaround adds a DSB instruction before the
1422 relevant cache maintenance functions and sets a specific bit
1423 in the diagnostic control register of the SCU.
1425 config PL310_ERRATA_769419
1426 bool "PL310 errata: no automatic Store Buffer drain"
1427 depends on CACHE_L2X0
1429 On revisions of the PL310 prior to r3p2, the Store Buffer does
1430 not automatically drain. This can cause normal, non-cacheable
1431 writes to be retained when the memory system is idle, leading
1432 to suboptimal I/O performance for drivers using coherent DMA.
1433 This option adds a write barrier to the cpu_idle loop so that,
1434 on systems with an outer cache, the store buffer is drained
1437 config ARM_ERRATA_775420
1438 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1441 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1442 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1443 operation aborts with MMU exception, it might cause the processor
1444 to deadlock. This workaround puts DSB before executing ISB if
1445 an abort may occur on cache maintenance.
1449 source "arch/arm/common/Kconfig"
1459 Find out whether you have ISA slots on your motherboard. ISA is the
1460 name of a bus system, i.e. the way the CPU talks to the other stuff
1461 inside your box. Other bus systems are PCI, EISA, MicroChannel
1462 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1463 newer boards don't support it. If you have ISA, say Y, otherwise N.
1465 # Select ISA DMA controller support
1470 config ARCH_NO_VIRT_TO_BUS
1472 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1474 # Select ISA DMA interface
1479 bool "PCI support" if MIGHT_HAVE_PCI
1481 Find out whether you have a PCI motherboard. PCI is the name of a
1482 bus system, i.e. the way the CPU talks to the other stuff inside
1483 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1484 VESA. If you have PCI, say Y, otherwise N.
1490 config PCI_NANOENGINE
1491 bool "BSE nanoEngine PCI support"
1492 depends on SA1100_NANOENGINE
1494 Enable PCI on the BSE nanoEngine board.
1499 # Select the host bridge type
1500 config PCI_HOST_VIA82C505
1502 depends on PCI && ARCH_SHARK
1505 config PCI_HOST_ITE8152
1507 depends on PCI && MACH_ARMCORE
1511 source "drivers/pci/Kconfig"
1513 source "drivers/pcmcia/Kconfig"
1517 menu "Kernel Features"
1522 This option should be selected by machines which have an SMP-
1525 The only effect of this option is to make the SMP-related
1526 options available to the user for configuration.
1529 bool "Symmetric Multi-Processing"
1530 depends on CPU_V6K || CPU_V7
1531 depends on GENERIC_CLOCKEVENTS
1534 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1535 select USE_GENERIC_SMP_HELPERS
1537 This enables support for systems with more than one CPU. If you have
1538 a system with only one CPU, like most personal computers, say N. If
1539 you have a system with more than one CPU, say Y.
1541 If you say N here, the kernel will run on single and multiprocessor
1542 machines, but will use only one CPU of a multiprocessor machine. If
1543 you say Y here, the kernel will run on many, but not all, single
1544 processor machines. On a single processor machine, the kernel will
1545 run faster if you say N here.
1547 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1548 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1549 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1551 If you don't know what to do here, say N.
1554 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1555 depends on SMP && !XIP_KERNEL
1558 SMP kernels contain instructions which fail on non-SMP processors.
1559 Enabling this option allows the kernel to modify itself to make
1560 these instructions safe. Disabling it allows about 1K of space
1563 If you don't know what to do here, say Y.
1565 config ARM_CPU_TOPOLOGY
1566 bool "Support cpu topology definition"
1567 depends on SMP && CPU_V7
1570 Support ARM cpu topology definition. The MPIDR register defines
1571 affinity between processors which is then used to describe the cpu
1572 topology of an ARM System.
1575 bool "Multi-core scheduler support"
1576 depends on ARM_CPU_TOPOLOGY
1578 Multi-core scheduler support improves the CPU scheduler's decision
1579 making when dealing with multi-core CPU chips at a cost of slightly
1580 increased overhead in some places. If unsure say N here.
1583 bool "SMT scheduler support"
1584 depends on ARM_CPU_TOPOLOGY
1586 Improves the CPU scheduler's decision making when dealing with
1587 MultiThreading at a cost of slightly increased overhead in some
1588 places. If unsure say N here.
1593 This option enables support for the ARM system coherency unit
1595 config HAVE_ARM_ARCH_TIMER
1596 bool "Architected timer support"
1598 select ARM_ARCH_TIMER
1600 This option enables support for the ARM architected timer
1606 This options enables support for the ARM timer and watchdog unit
1609 prompt "Memory split"
1612 Select the desired split between kernel and user memory.
1614 If you are not absolutely sure what you are doing, leave this
1618 bool "3G/1G user/kernel split"
1620 bool "2G/2G user/kernel split"
1622 bool "1G/3G user/kernel split"
1627 default 0x40000000 if VMSPLIT_1G
1628 default 0x80000000 if VMSPLIT_2G
1632 int "Maximum number of CPUs (2-32)"
1638 bool "Support for hot-pluggable CPUs"
1639 depends on SMP && HOTPLUG
1641 Say Y here to experiment with turning CPUs off and on. CPUs
1642 can be controlled through /sys/devices/system/cpu.
1645 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1648 Say Y here if you want Linux to communicate with system firmware
1649 implementing the PSCI specification for CPU-centric power
1650 management operations described in ARM document number ARM DEN
1651 0022A ("Power State Coordination Interface System Software on
1655 bool "Use local timer interrupts"
1658 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1660 Enable support for local timers on SMP platforms, rather then the
1661 legacy IPI broadcast method. Local timers allows the system
1662 accounting to be spread across the timer interval, preventing a
1663 "thundering herd" at every timer tick.
1667 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1668 default 355 if ARCH_U8500
1669 default 264 if MACH_H4700
1670 default 512 if SOC_OMAP5
1671 default 288 if ARCH_VT8500 || ARCH_SUNXI
1674 Maximum number of GPIOs in the system.
1676 If unsure, leave the default value.
1678 source kernel/Kconfig.preempt
1682 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1683 ARCH_S5PV210 || ARCH_EXYNOS4
1684 default AT91_TIMER_HZ if ARCH_AT91
1685 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1689 def_bool HIGH_RES_TIMERS
1691 config THUMB2_KERNEL
1692 bool "Compile the kernel in Thumb-2 mode"
1693 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1695 select ARM_ASM_UNIFIED
1698 By enabling this option, the kernel will be compiled in
1699 Thumb-2 mode. A compiler/assembler that understand the unified
1700 ARM-Thumb syntax is needed.
1704 config THUMB2_AVOID_R_ARM_THM_JUMP11
1705 bool "Work around buggy Thumb-2 short branch relocations in gas"
1706 depends on THUMB2_KERNEL && MODULES
1709 Various binutils versions can resolve Thumb-2 branches to
1710 locally-defined, preemptible global symbols as short-range "b.n"
1711 branch instructions.
1713 This is a problem, because there's no guarantee the final
1714 destination of the symbol, or any candidate locations for a
1715 trampoline, are within range of the branch. For this reason, the
1716 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1717 relocation in modules at all, and it makes little sense to add
1720 The symptom is that the kernel fails with an "unsupported
1721 relocation" error when loading some modules.
1723 Until fixed tools are available, passing
1724 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1725 code which hits this problem, at the cost of a bit of extra runtime
1726 stack usage in some cases.
1728 The problem is described in more detail at:
1729 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1731 Only Thumb-2 kernels are affected.
1733 Unless you are sure your tools don't have this problem, say Y.
1735 config ARM_ASM_UNIFIED
1739 bool "Use the ARM EABI to compile the kernel"
1741 This option allows for the kernel to be compiled using the latest
1742 ARM ABI (aka EABI). This is only useful if you are using a user
1743 space environment that is also compiled with EABI.
1745 Since there are major incompatibilities between the legacy ABI and
1746 EABI, especially with regard to structure member alignment, this
1747 option also changes the kernel syscall calling convention to
1748 disambiguate both ABIs and allow for backward compatibility support
1749 (selected with CONFIG_OABI_COMPAT).
1751 To use this you need GCC version 4.0.0 or later.
1754 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1755 depends on AEABI && !THUMB2_KERNEL
1758 This option preserves the old syscall interface along with the
1759 new (ARM EABI) one. It also provides a compatibility layer to
1760 intercept syscalls that have structure arguments which layout
1761 in memory differs between the legacy ABI and the new ARM EABI
1762 (only for non "thumb" binaries). This option adds a tiny
1763 overhead to all syscalls and produces a slightly larger kernel.
1764 If you know you'll be using only pure EABI user space then you
1765 can say N here. If this option is not selected and you attempt
1766 to execute a legacy ABI binary then the result will be
1767 UNPREDICTABLE (in fact it can be predicted that it won't work
1768 at all). If in doubt say Y.
1770 config ARCH_HAS_HOLES_MEMORYMODEL
1773 config ARCH_SPARSEMEM_ENABLE
1776 config ARCH_SPARSEMEM_DEFAULT
1777 def_bool ARCH_SPARSEMEM_ENABLE
1779 config ARCH_SELECT_MEMORY_MODEL
1780 def_bool ARCH_SPARSEMEM_ENABLE
1782 config HAVE_ARCH_PFN_VALID
1783 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1786 bool "High Memory Support"
1789 The address space of ARM processors is only 4 Gigabytes large
1790 and it has to accommodate user address space, kernel address
1791 space as well as some memory mapped IO. That means that, if you
1792 have a large amount of physical memory and/or IO, not all of the
1793 memory can be "permanently mapped" by the kernel. The physical
1794 memory that is not permanently mapped is called "high memory".
1796 Depending on the selected kernel/user memory split, minimum
1797 vmalloc space and actual amount of RAM, you may not need this
1798 option which should result in a slightly faster kernel.
1803 bool "Allocate 2nd-level pagetables from highmem"
1806 config HW_PERF_EVENTS
1807 bool "Enable hardware performance counter support for perf events"
1808 depends on PERF_EVENTS
1811 Enable hardware performance counter support for perf events. If
1812 disabled, perf events will use software events only.
1816 config FORCE_MAX_ZONEORDER
1817 int "Maximum zone order" if ARCH_SHMOBILE
1818 range 11 64 if ARCH_SHMOBILE
1819 default "12" if SOC_AM33XX
1820 default "9" if SA1111
1823 The kernel memory allocator divides physically contiguous memory
1824 blocks into "zones", where each zone is a power of two number of
1825 pages. This option selects the largest power of two that the kernel
1826 keeps in the memory allocator. If you need to allocate very large
1827 blocks of physically contiguous memory, then you may need to
1828 increase this value.
1830 This config option is actually maximum order plus one. For example,
1831 a value of 11 means that the largest free memory block is 2^10 pages.
1833 config ALIGNMENT_TRAP
1835 depends on CPU_CP15_MMU
1836 default y if !ARCH_EBSA110
1837 select HAVE_PROC_CPU if PROC_FS
1839 ARM processors cannot fetch/store information which is not
1840 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1841 address divisible by 4. On 32-bit ARM processors, these non-aligned
1842 fetch/store instructions will be emulated in software if you say
1843 here, which has a severe performance impact. This is necessary for
1844 correct operation of some network protocols. With an IP-only
1845 configuration it is safe to say N, otherwise say Y.
1847 config UACCESS_WITH_MEMCPY
1848 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1850 default y if CPU_FEROCEON
1852 Implement faster copy_to_user and clear_user methods for CPU
1853 cores where a 8-word STM instruction give significantly higher
1854 memory write throughput than a sequence of individual 32bit stores.
1856 A possible side effect is a slight increase in scheduling latency
1857 between threads sharing the same address space if they invoke
1858 such copy operations with large buffers.
1860 However, if the CPU data cache is using a write-allocate mode,
1861 this option is unlikely to provide any performance gain.
1865 prompt "Enable seccomp to safely compute untrusted bytecode"
1867 This kernel feature is useful for number crunching applications
1868 that may need to compute untrusted bytecode during their
1869 execution. By using pipes or other transports made available to
1870 the process as file descriptors supporting the read/write
1871 syscalls, it's possible to isolate those applications in
1872 their own address space using seccomp. Once seccomp is
1873 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1874 and the task is only allowed to execute a few safe syscalls
1875 defined by each seccomp mode.
1877 config CC_STACKPROTECTOR
1878 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1880 This option turns on the -fstack-protector GCC feature. This
1881 feature puts, at the beginning of functions, a canary value on
1882 the stack just before the return address, and validates
1883 the value just before actually returning. Stack based buffer
1884 overflows (that need to overwrite this return address) now also
1885 overwrite the canary, which gets detected and the attack is then
1886 neutralized via a kernel panic.
1887 This feature requires gcc version 4.2 or above.
1894 bool "Xen guest support on ARM (EXPERIMENTAL)"
1895 depends on ARM && OF
1896 depends on CPU_V7 && !CPU_V6
1898 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1905 bool "Flattened Device Tree support"
1908 select OF_EARLY_FLATTREE
1910 Include support for flattened device tree machine descriptions.
1913 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1916 This is the traditional way of passing data to the kernel at boot
1917 time. If you are solely relying on the flattened device tree (or
1918 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1919 to remove ATAGS support from your kernel binary. If unsure,
1922 config DEPRECATED_PARAM_STRUCT
1923 bool "Provide old way to pass kernel parameters"
1926 This was deprecated in 2001 and announced to live on for 5 years.
1927 Some old boot loaders still use this way.
1929 # Compressed boot loader in ROM. Yes, we really want to ask about
1930 # TEXT and BSS so we preserve their values in the config files.
1931 config ZBOOT_ROM_TEXT
1932 hex "Compressed ROM boot loader base address"
1935 The physical address at which the ROM-able zImage is to be
1936 placed in the target. Platforms which normally make use of
1937 ROM-able zImage formats normally set this to a suitable
1938 value in their defconfig file.
1940 If ZBOOT_ROM is not enabled, this has no effect.
1942 config ZBOOT_ROM_BSS
1943 hex "Compressed ROM boot loader BSS address"
1946 The base address of an area of read/write memory in the target
1947 for the ROM-able zImage which must be available while the
1948 decompressor is running. It must be large enough to hold the
1949 entire decompressed kernel plus an additional 128 KiB.
1950 Platforms which normally make use of ROM-able zImage formats
1951 normally set this to a suitable value in their defconfig file.
1953 If ZBOOT_ROM is not enabled, this has no effect.
1956 bool "Compressed boot loader in ROM/flash"
1957 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1959 Say Y here if you intend to execute your compressed kernel image
1960 (zImage) directly from ROM or flash. If unsure, say N.
1963 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1964 depends on ZBOOT_ROM && ARCH_SH7372
1965 default ZBOOT_ROM_NONE
1967 Include experimental SD/MMC loading code in the ROM-able zImage.
1968 With this enabled it is possible to write the ROM-able zImage
1969 kernel image to an MMC or SD card and boot the kernel straight
1970 from the reset vector. At reset the processor Mask ROM will load
1971 the first part of the ROM-able zImage which in turn loads the
1972 rest the kernel image to RAM.
1974 config ZBOOT_ROM_NONE
1975 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1977 Do not load image from SD or MMC
1979 config ZBOOT_ROM_MMCIF
1980 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1982 Load image from MMCIF hardware block.
1984 config ZBOOT_ROM_SH_MOBILE_SDHI
1985 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1987 Load image from SDHI hardware block
1991 config ARM_APPENDED_DTB
1992 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1993 depends on OF && !ZBOOT_ROM
1995 With this option, the boot code will look for a device tree binary
1996 (DTB) appended to zImage
1997 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1999 This is meant as a backward compatibility convenience for those
2000 systems with a bootloader that can't be upgraded to accommodate
2001 the documented boot protocol using a device tree.
2003 Beware that there is very little in terms of protection against
2004 this option being confused by leftover garbage in memory that might
2005 look like a DTB header after a reboot if no actual DTB is appended
2006 to zImage. Do not leave this option active in a production kernel
2007 if you don't intend to always append a DTB. Proper passing of the
2008 location into r2 of a bootloader provided DTB is always preferable
2011 config ARM_ATAG_DTB_COMPAT
2012 bool "Supplement the appended DTB with traditional ATAG information"
2013 depends on ARM_APPENDED_DTB
2015 Some old bootloaders can't be updated to a DTB capable one, yet
2016 they provide ATAGs with memory configuration, the ramdisk address,
2017 the kernel cmdline string, etc. Such information is dynamically
2018 provided by the bootloader and can't always be stored in a static
2019 DTB. To allow a device tree enabled kernel to be used with such
2020 bootloaders, this option allows zImage to extract the information
2021 from the ATAG list and store it at run time into the appended DTB.
2024 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2025 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2027 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2028 bool "Use bootloader kernel arguments if available"
2030 Uses the command-line options passed by the boot loader instead of
2031 the device tree bootargs property. If the boot loader doesn't provide
2032 any, the device tree bootargs property will be used.
2034 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2035 bool "Extend with bootloader kernel arguments"
2037 The command-line arguments provided by the boot loader will be
2038 appended to the the device tree bootargs property.
2043 string "Default kernel command string"
2046 On some architectures (EBSA110 and CATS), there is currently no way
2047 for the boot loader to pass arguments to the kernel. For these
2048 architectures, you should supply some command-line options at build
2049 time by entering them here. As a minimum, you should specify the
2050 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2053 prompt "Kernel command line type" if CMDLINE != ""
2054 default CMDLINE_FROM_BOOTLOADER
2057 config CMDLINE_FROM_BOOTLOADER
2058 bool "Use bootloader kernel arguments if available"
2060 Uses the command-line options passed by the boot loader. If
2061 the boot loader doesn't provide any, the default kernel command
2062 string provided in CMDLINE will be used.
2064 config CMDLINE_EXTEND
2065 bool "Extend bootloader kernel arguments"
2067 The command-line arguments provided by the boot loader will be
2068 appended to the default kernel command string.
2070 config CMDLINE_FORCE
2071 bool "Always use the default kernel command string"
2073 Always use the default kernel command string, even if the boot
2074 loader passes other arguments to the kernel.
2075 This is useful if you cannot or don't want to change the
2076 command-line options your boot loader passes to the kernel.
2080 bool "Kernel Execute-In-Place from ROM"
2081 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2083 Execute-In-Place allows the kernel to run from non-volatile storage
2084 directly addressable by the CPU, such as NOR flash. This saves RAM
2085 space since the text section of the kernel is not loaded from flash
2086 to RAM. Read-write sections, such as the data section and stack,
2087 are still copied to RAM. The XIP kernel is not compressed since
2088 it has to run directly from flash, so it will take more space to
2089 store it. The flash address used to link the kernel object files,
2090 and for storing it, is configuration dependent. Therefore, if you
2091 say Y here, you must know the proper physical address where to
2092 store the kernel image depending on your own flash memory usage.
2094 Also note that the make target becomes "make xipImage" rather than
2095 "make zImage" or "make Image". The final kernel binary to put in
2096 ROM memory will be arch/arm/boot/xipImage.
2100 config XIP_PHYS_ADDR
2101 hex "XIP Kernel Physical Location"
2102 depends on XIP_KERNEL
2103 default "0x00080000"
2105 This is the physical address in your flash memory the kernel will
2106 be linked for and stored to. This address is dependent on your
2110 bool "Kexec system call (EXPERIMENTAL)"
2111 depends on (!SMP || HOTPLUG_CPU)
2113 kexec is a system call that implements the ability to shutdown your
2114 current kernel, and to start another kernel. It is like a reboot
2115 but it is independent of the system firmware. And like a reboot
2116 you can start any kernel with it, not just Linux.
2118 It is an ongoing process to be certain the hardware in a machine
2119 is properly shutdown, so do not be surprised if this code does not
2120 initially work for you. It may help to enable device hotplugging
2124 bool "Export atags in procfs"
2125 depends on ATAGS && KEXEC
2128 Should the atags used to boot the kernel be exported in an "atags"
2129 file in procfs. Useful with kexec.
2132 bool "Build kdump crash kernel (EXPERIMENTAL)"
2134 Generate crash dump after being started by kexec. This should
2135 be normally only set in special crash dump kernels which are
2136 loaded in the main kernel with kexec-tools into a specially
2137 reserved region and then later executed after a crash by
2138 kdump/kexec. The crash dump kernel must be compiled to a
2139 memory address not used by the main kernel
2141 For more details see Documentation/kdump/kdump.txt
2143 config AUTO_ZRELADDR
2144 bool "Auto calculation of the decompressed kernel image address"
2145 depends on !ZBOOT_ROM && !ARCH_U300
2147 ZRELADDR is the physical address where the decompressed kernel
2148 image will be placed. If AUTO_ZRELADDR is selected, the address
2149 will be determined at run-time by masking the current IP with
2150 0xf8000000. This assumes the zImage being placed in the first 128MB
2151 from start of memory.
2155 menu "CPU Power Management"
2159 source "drivers/cpufreq/Kconfig"
2162 tristate "CPUfreq driver for i.MX CPUs"
2163 depends on ARCH_MXC && CPU_FREQ
2164 select CPU_FREQ_TABLE
2166 This enables the CPUfreq driver for i.MX CPUs.
2168 config CPU_FREQ_SA1100
2171 config CPU_FREQ_SA1110
2174 config CPU_FREQ_INTEGRATOR
2175 tristate "CPUfreq driver for ARM Integrator CPUs"
2176 depends on ARCH_INTEGRATOR && CPU_FREQ
2179 This enables the CPUfreq driver for ARM Integrator CPUs.
2181 For details, take a look at <file:Documentation/cpu-freq>.
2187 depends on CPU_FREQ && ARCH_PXA && PXA25x
2189 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2190 select CPU_FREQ_TABLE
2195 Internal configuration node for common cpufreq on Samsung SoC
2197 config CPU_FREQ_S3C24XX
2198 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2199 depends on ARCH_S3C24XX && CPU_FREQ
2202 This enables the CPUfreq driver for the Samsung S3C24XX family
2205 For details, take a look at <file:Documentation/cpu-freq>.
2209 config CPU_FREQ_S3C24XX_PLL
2210 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2211 depends on CPU_FREQ_S3C24XX
2213 Compile in support for changing the PLL frequency from the
2214 S3C24XX series CPUfreq driver. The PLL takes time to settle
2215 after a frequency change, so by default it is not enabled.
2217 This also means that the PLL tables for the selected CPU(s) will
2218 be built which may increase the size of the kernel image.
2220 config CPU_FREQ_S3C24XX_DEBUG
2221 bool "Debug CPUfreq Samsung driver core"
2222 depends on CPU_FREQ_S3C24XX
2224 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2226 config CPU_FREQ_S3C24XX_IODEBUG
2227 bool "Debug CPUfreq Samsung driver IO timing"
2228 depends on CPU_FREQ_S3C24XX
2230 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2232 config CPU_FREQ_S3C24XX_DEBUGFS
2233 bool "Export debugfs for CPUFreq"
2234 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2236 Export status information via debugfs.
2240 source "drivers/cpuidle/Kconfig"
2244 menu "Floating point emulation"
2246 comment "At least one emulation must be selected"
2249 bool "NWFPE math emulation"
2250 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2252 Say Y to include the NWFPE floating point emulator in the kernel.
2253 This is necessary to run most binaries. Linux does not currently
2254 support floating point hardware so you need to say Y here even if
2255 your machine has an FPA or floating point co-processor podule.
2257 You may say N here if you are going to load the Acorn FPEmulator
2258 early in the bootup.
2261 bool "Support extended precision"
2262 depends on FPE_NWFPE
2264 Say Y to include 80-bit support in the kernel floating-point
2265 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2266 Note that gcc does not generate 80-bit operations by default,
2267 so in most cases this option only enlarges the size of the
2268 floating point emulator without any good reason.
2270 You almost surely want to say N here.
2273 bool "FastFPE math emulation (EXPERIMENTAL)"
2274 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2276 Say Y here to include the FAST floating point emulator in the kernel.
2277 This is an experimental much faster emulator which now also has full
2278 precision for the mantissa. It does not support any exceptions.
2279 It is very simple, and approximately 3-6 times faster than NWFPE.
2281 It should be sufficient for most programs. It may be not suitable
2282 for scientific calculations, but you have to check this for yourself.
2283 If you do not feel you need a faster FP emulation you should better
2287 bool "VFP-format floating point maths"
2288 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2290 Say Y to include VFP support code in the kernel. This is needed
2291 if your hardware includes a VFP unit.
2293 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2294 release notes and additional status information.
2296 Say N if your target does not have VFP hardware.
2304 bool "Advanced SIMD (NEON) Extension support"
2305 depends on VFPv3 && CPU_V7
2307 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2312 menu "Userspace binary formats"
2314 source "fs/Kconfig.binfmt"
2317 tristate "RISC OS personality"
2320 Say Y here to include the kernel code necessary if you want to run
2321 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2322 experimental; if this sounds frightening, say N and sleep in peace.
2323 You can also say M here to compile this support as a module (which
2324 will be called arthur).
2328 menu "Power management options"
2330 source "kernel/power/Kconfig"
2332 config ARCH_SUSPEND_POSSIBLE
2333 depends on !ARCH_S5PC100
2334 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2335 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2338 config ARM_CPU_SUSPEND
2343 source "net/Kconfig"
2345 source "drivers/Kconfig"
2349 source "arch/arm/Kconfig.debug"
2351 source "security/Kconfig"
2353 source "crypto/Kconfig"
2355 source "lib/Kconfig"
2357 source "arch/arm/kvm/Kconfig"