1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
47 select DMA_GLOBAL_POOL if !MMU
49 select DMA_REMAP if MMU
51 select EDAC_ATOMIC_SCRUB
52 select GENERIC_ALLOCATOR
53 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
54 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
55 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
56 select GENERIC_IRQ_IPI if SMP
57 select GENERIC_CPU_AUTOPROBE
58 select GENERIC_EARLY_IOREMAP
59 select GENERIC_IDLE_POLL_SETUP
60 select GENERIC_IRQ_PROBE
61 select GENERIC_IRQ_SHOW
62 select GENERIC_IRQ_SHOW_LEVEL
63 select GENERIC_LIB_DEVMEM_IS_ALLOWED
64 select GENERIC_PCI_IOMAP
65 select GENERIC_SCHED_CLOCK
66 select GENERIC_SMP_IDLE_THREAD
67 select HARDIRQS_SW_RESEND
68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
72 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
73 select HAVE_ARCH_MMAP_RND_BITS if MMU
74 select HAVE_ARCH_PFN_VALID
75 select HAVE_ARCH_SECCOMP
76 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
77 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
78 select HAVE_ARCH_TRACEHOOK
79 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
80 select HAVE_ARM_SMCCC if CPU_V7
81 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
82 select HAVE_CONTEXT_TRACKING
83 select HAVE_C_RECORDMCOUNT
84 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
85 select HAVE_DMA_CONTIGUOUS if MMU
86 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
87 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
88 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
89 select HAVE_EXIT_THREAD
90 select HAVE_FAST_GUP if ARM_LPAE
91 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
92 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
93 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
94 select HAVE_GCC_PLUGINS
95 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
96 select HAVE_IRQ_TIME_ACCOUNTING
97 select HAVE_KERNEL_GZIP
98 select HAVE_KERNEL_LZ4
99 select HAVE_KERNEL_LZMA
100 select HAVE_KERNEL_LZO
101 select HAVE_KERNEL_XZ
102 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
103 select HAVE_KRETPROBES if HAVE_KPROBES
104 select HAVE_MOD_ARCH_SPECIFIC
106 select HAVE_OPTPROBES if !THUMB2_KERNEL
107 select HAVE_PERF_EVENTS
108 select HAVE_PERF_REGS
109 select HAVE_PERF_USER_STACK_DUMP
110 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
111 select HAVE_REGS_AND_STACK_ACCESS_API
113 select HAVE_STACKPROTECTOR
114 select HAVE_SYSCALL_TRACEPOINTS
116 select HAVE_VIRT_CPU_ACCOUNTING_GEN
117 select IRQ_FORCED_THREADING
118 select MODULES_USE_ELF_REL
119 select NEED_DMA_MAP_STATE
120 select OF_EARLY_FLATTREE if OF
122 select OLD_SIGSUSPEND3
123 select PCI_SYSCALL if PCI
124 select PERF_USE_VMALLOC
126 select SYS_SUPPORTS_APM_EMULATION
127 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
128 # Above selects are sorted alphabetically; please add new ones
129 # according to that. Thanks.
131 The ARM series is a line of low-power-consumption RISC chip designs
132 licensed by ARM Ltd and targeted at embedded applications and
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
135 Europe. There is an ARM Linux project with a web page at
136 <http://www.arm.linux.org.uk/>.
138 config ARM_HAS_SG_CHAIN
141 config ARM_DMA_USE_IOMMU
143 select ARM_HAS_SG_CHAIN
144 select NEED_SG_DMA_LENGTH
148 config ARM_DMA_IOMMU_ALIGNMENT
149 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
153 DMA mapping framework by default aligns all buffers to the smallest
154 PAGE_SIZE order which is greater than or equal to the requested buffer
155 size. This works well for buffers up to a few hundreds kilobytes, but
156 for larger buffers it just a waste of address space. Drivers which has
157 relatively small addressing window (like 64Mib) might run out of
158 virtual space with just a few allocations.
160 With this parameter you can specify the maximum PAGE_SIZE order for
161 DMA IOMMU buffers. Larger buffers will be aligned only to this
162 specified order. The order is expressed as a power of two multiplied
167 config SYS_SUPPORTS_APM_EMULATION
172 select GENERIC_ALLOCATOR
183 config STACKTRACE_SUPPORT
187 config LOCKDEP_SUPPORT
191 config ARCH_HAS_ILOG2_U32
194 config ARCH_HAS_ILOG2_U64
197 config ARCH_HAS_BANDGAP
200 config FIX_EARLYCON_MEM
203 config GENERIC_HWEIGHT
207 config GENERIC_CALIBRATE_DELAY
211 config ARCH_MAY_HAVE_PC_FDC
214 config ARCH_SUPPORTS_UPROBES
217 config ARCH_HAS_DMA_SET_COHERENT_MASK
220 config GENERIC_ISA_DMA
226 config NEED_RET_TO_USER
232 config ARM_PATCH_PHYS_VIRT
233 bool "Patch physical to virtual translations at runtime" if EMBEDDED
235 depends on !XIP_KERNEL && MMU
237 Patch phys-to-virt and virt-to-phys translation functions at
238 boot and module load time according to the position of the
239 kernel in system memory.
241 This can only be used with non-XIP MMU kernels where the base
242 of physical memory is at a 2 MiB boundary.
244 Only disable this option if you know that you do not require
245 this feature (eg, building a kernel for a single machine) and
246 you need to shrink the kernel to the minimal size.
248 config NEED_MACH_IO_H
251 Select this when mach/io.h is required to provide special
252 definitions for this platform. The need for mach/io.h should
253 be avoided when possible.
255 config NEED_MACH_MEMORY_H
258 Select this when mach/memory.h is required to provide special
259 definitions for this platform. The need for mach/memory.h should
260 be avoided when possible.
263 hex "Physical address of main memory" if MMU
264 depends on !ARM_PATCH_PHYS_VIRT
265 default DRAM_BASE if !MMU
266 default 0x00000000 if ARCH_FOOTBRIDGE
267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
268 default 0x20000000 if ARCH_S5PV210
269 default 0xc0000000 if ARCH_SA1100
271 Please provide the physical address corresponding to the
272 location of main memory in your system.
278 config PGTABLE_LEVELS
280 default 3 if ARM_LPAE
286 bool "MMU-based Paged Memory Management Support"
289 Select if you want MMU-based virtualised addressing space
290 support by paged memory management. If unsure, say 'Y'.
292 config ARCH_MMAP_RND_BITS_MIN
295 config ARCH_MMAP_RND_BITS_MAX
296 default 14 if PAGE_OFFSET=0x40000000
297 default 15 if PAGE_OFFSET=0x80000000
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARM_SINGLE_ARMV7M if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARCH_FLATMEM_ENABLE
313 select ARCH_SPARSEMEM_ENABLE
314 select ARCH_SELECT_MEMORY_MODEL
315 select ARM_HAS_SG_CHAIN
316 select ARM_PATCH_PHYS_VIRT
320 select GENERIC_IRQ_MULTI_HANDLER
322 select PCI_DOMAINS_GENERIC if PCI
326 config ARM_SINGLE_ARMV7M
327 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
340 select ARCH_SPARSEMEM_ENABLE
342 imply ARM_PATCH_PHYS_VIRT
344 select GENERIC_IRQ_MULTI_HANDLER
349 select HAVE_LEGACY_CLK
351 This enables support for the Cirrus EP93xx series of CPUs.
353 config ARCH_FOOTBRIDGE
357 select NEED_MACH_IO_H if !MMU
358 select NEED_MACH_MEMORY_H
360 Support for systems based on the DC21285 companion chip
361 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
369 select NEED_RET_TO_USER
373 Support for Intel's 80219 and IOP32X (XScale) family of
379 select ARCH_HAS_DMA_SET_COHERENT_MASK
380 select ARCH_SUPPORTS_BIG_ENDIAN
382 select DMABOUNCE if PCI
383 select GENERIC_IRQ_MULTI_HANDLER
389 # With the new PCI driver this is not needed
390 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
391 select USB_EHCI_BIG_ENDIAN_DESC
392 select USB_EHCI_BIG_ENDIAN_MMIO
394 Support for Intel's IXP4XX (XScale) family of processors.
399 select GENERIC_IRQ_MULTI_HANDLER
405 select PLAT_ORION_LEGACY
407 select PM_GENERIC_DOMAINS if PM
409 Support for the Marvell Dove SoC 88AP510
412 bool "PXA2xx/PXA3xx-based"
415 select ARM_CPU_SUSPEND if PM
421 select CPU_XSCALE if !CPU_XSC3
422 select GENERIC_IRQ_MULTI_HANDLER
429 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
435 select ARCH_MAY_HAVE_PC_FDC
436 select ARCH_SPARSEMEM_ENABLE
437 select ARM_HAS_SG_CHAIN
440 select HAVE_PATA_PLATFORM
442 select LEGACY_TIMER_TICK
443 select NEED_MACH_IO_H
444 select NEED_MACH_MEMORY_H
447 On the Acorn Risc-PC, Linux can support the internal IDE disk and
448 CD-ROM interface, serial and parallel port, and the floppy drive.
453 select ARCH_SPARSEMEM_ENABLE
456 select TIMER_OF if OF
460 select GENERIC_IRQ_MULTI_HANDLER
464 select NEED_MACH_MEMORY_H
467 Support for StrongARM 11x0 based boards.
470 bool "Samsung S3C24XX SoCs"
472 select CLKSRC_SAMSUNG_PWM
475 select GENERIC_IRQ_MULTI_HANDLER
476 select HAVE_S3C2410_I2C if I2C
477 select HAVE_S3C_RTC if RTC_CLASS
478 select NEED_MACH_IO_H
479 select S3C2410_WATCHDOG
484 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
485 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
486 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
487 Samsung SMDK2410 development board (and derivatives).
494 select GENERIC_IRQ_CHIP
495 select GENERIC_IRQ_MULTI_HANDLER
497 select HAVE_LEGACY_CLK
499 select NEED_MACH_IO_H if PCCARD
500 select NEED_MACH_MEMORY_H
503 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
507 menu "Multiple platform selection"
508 depends on ARCH_MULTIPLATFORM
510 comment "CPU Core family selection"
513 bool "ARMv4 based platforms (FA526)"
514 depends on !ARCH_MULTI_V6_V7
515 select ARCH_MULTI_V4_V5
518 config ARCH_MULTI_V4T
519 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
520 depends on !ARCH_MULTI_V6_V7
521 select ARCH_MULTI_V4_V5
522 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
523 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
524 CPU_ARM925T || CPU_ARM940T)
527 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
528 depends on !ARCH_MULTI_V6_V7
529 select ARCH_MULTI_V4_V5
530 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
531 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
532 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
534 config ARCH_MULTI_V4_V5
538 bool "ARMv6 based platforms (ARM11)"
539 select ARCH_MULTI_V6_V7
543 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
545 select ARCH_MULTI_V6_V7
549 config ARCH_MULTI_V6_V7
551 select MIGHT_HAVE_CACHE_L2X0
553 config ARCH_MULTI_CPU_AUTO
554 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
560 bool "Dummy Virtual Machine"
561 depends on ARCH_MULTI_V7
564 select ARM_GIC_V2M if PCI
566 select ARM_GIC_V3_ITS if PCI
568 select HAVE_ARM_ARCH_TIMER
569 select ARCH_SUPPORTS_BIG_ENDIAN
572 # This is sorted alphabetically by mach-* pathname. However, plat-*
573 # Kconfigs may be included either alphabetically (according to the
574 # plat- suffix) or along side the corresponding mach-* source.
576 source "arch/arm/mach-actions/Kconfig"
578 source "arch/arm/mach-alpine/Kconfig"
580 source "arch/arm/mach-artpec/Kconfig"
582 source "arch/arm/mach-asm9260/Kconfig"
584 source "arch/arm/mach-aspeed/Kconfig"
586 source "arch/arm/mach-at91/Kconfig"
588 source "arch/arm/mach-axxia/Kconfig"
590 source "arch/arm/mach-bcm/Kconfig"
592 source "arch/arm/mach-berlin/Kconfig"
594 source "arch/arm/mach-clps711x/Kconfig"
596 source "arch/arm/mach-cns3xxx/Kconfig"
598 source "arch/arm/mach-davinci/Kconfig"
600 source "arch/arm/mach-digicolor/Kconfig"
602 source "arch/arm/mach-dove/Kconfig"
604 source "arch/arm/mach-ep93xx/Kconfig"
606 source "arch/arm/mach-exynos/Kconfig"
608 source "arch/arm/mach-footbridge/Kconfig"
610 source "arch/arm/mach-gemini/Kconfig"
612 source "arch/arm/mach-highbank/Kconfig"
614 source "arch/arm/mach-hisi/Kconfig"
616 source "arch/arm/mach-imx/Kconfig"
618 source "arch/arm/mach-integrator/Kconfig"
620 source "arch/arm/mach-iop32x/Kconfig"
622 source "arch/arm/mach-ixp4xx/Kconfig"
624 source "arch/arm/mach-keystone/Kconfig"
626 source "arch/arm/mach-lpc32xx/Kconfig"
628 source "arch/arm/mach-mediatek/Kconfig"
630 source "arch/arm/mach-meson/Kconfig"
632 source "arch/arm/mach-milbeaut/Kconfig"
634 source "arch/arm/mach-mmp/Kconfig"
636 source "arch/arm/mach-moxart/Kconfig"
638 source "arch/arm/mach-mstar/Kconfig"
640 source "arch/arm/mach-mv78xx0/Kconfig"
642 source "arch/arm/mach-mvebu/Kconfig"
644 source "arch/arm/mach-mxs/Kconfig"
646 source "arch/arm/mach-nomadik/Kconfig"
648 source "arch/arm/mach-npcm/Kconfig"
650 source "arch/arm/mach-nspire/Kconfig"
652 source "arch/arm/plat-omap/Kconfig"
654 source "arch/arm/mach-omap1/Kconfig"
656 source "arch/arm/mach-omap2/Kconfig"
658 source "arch/arm/mach-orion5x/Kconfig"
660 source "arch/arm/mach-oxnas/Kconfig"
662 source "arch/arm/mach-pxa/Kconfig"
663 source "arch/arm/plat-pxa/Kconfig"
665 source "arch/arm/mach-qcom/Kconfig"
667 source "arch/arm/mach-rda/Kconfig"
669 source "arch/arm/mach-realtek/Kconfig"
671 source "arch/arm/mach-realview/Kconfig"
673 source "arch/arm/mach-rockchip/Kconfig"
675 source "arch/arm/mach-s3c/Kconfig"
677 source "arch/arm/mach-s5pv210/Kconfig"
679 source "arch/arm/mach-sa1100/Kconfig"
681 source "arch/arm/mach-shmobile/Kconfig"
683 source "arch/arm/mach-socfpga/Kconfig"
685 source "arch/arm/mach-spear/Kconfig"
687 source "arch/arm/mach-sti/Kconfig"
689 source "arch/arm/mach-stm32/Kconfig"
691 source "arch/arm/mach-sunxi/Kconfig"
693 source "arch/arm/mach-tegra/Kconfig"
695 source "arch/arm/mach-uniphier/Kconfig"
697 source "arch/arm/mach-ux500/Kconfig"
699 source "arch/arm/mach-versatile/Kconfig"
701 source "arch/arm/mach-vexpress/Kconfig"
703 source "arch/arm/mach-vt8500/Kconfig"
705 source "arch/arm/mach-zynq/Kconfig"
707 # ARMv7-M architecture
709 bool "NXP LPC18xx/LPC43xx"
710 depends on ARM_SINGLE_ARMV7M
711 select ARCH_HAS_RESET_CONTROLLER
713 select CLKSRC_LPC32XX
716 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
717 high performance microcontrollers.
720 bool "ARM MPS2 platform"
721 depends on ARM_SINGLE_ARMV7M
725 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
726 with a range of available cores like Cortex-M3/M4/M7.
728 Please, note that depends which Application Note is used memory map
729 for the platform may vary, so adjustment of RAM base might be needed.
731 # Definitions to make life easier
742 select GENERIC_IRQ_CHIP
745 config PLAT_ORION_LEGACY
752 config PLAT_VERSATILE
755 source "arch/arm/mm/Kconfig"
758 bool "Enable iWMMXt support"
759 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
760 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
762 Enable support for iWMMXt context switching at run time if
763 running on a CPU that supports it.
766 source "arch/arm/Kconfig-nommu"
769 config PJ4B_ERRATA_4742
770 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
771 depends on CPU_PJ4B && MACH_ARMADA_370
774 When coming out of either a Wait for Interrupt (WFI) or a Wait for
775 Event (WFE) IDLE states, a specific timing sensitivity exists between
776 the retiring WFI/WFE instructions and the newly issued subsequent
777 instructions. This sensitivity can result in a CPU hang scenario.
779 The software must insert either a Data Synchronization Barrier (DSB)
780 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
783 config ARM_ERRATA_326103
784 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
787 Executing a SWP instruction to read-only memory does not set bit 11
788 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
789 treat the access as a read, preventing a COW from occurring and
790 causing the faulting task to livelock.
792 config ARM_ERRATA_411920
793 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
794 depends on CPU_V6 || CPU_V6K
796 Invalidation of the Instruction Cache operation can
797 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
798 It does not affect the MPCore. This option enables the ARM Ltd.
799 recommended workaround.
801 config ARM_ERRATA_430973
802 bool "ARM errata: Stale prediction on replaced interworking branch"
805 This option enables the workaround for the 430973 Cortex-A8
806 r1p* erratum. If a code sequence containing an ARM/Thumb
807 interworking branch is replaced with another code sequence at the
808 same virtual address, whether due to self-modifying code or virtual
809 to physical address re-mapping, Cortex-A8 does not recover from the
810 stale interworking branch prediction. This results in Cortex-A8
811 executing the new code sequence in the incorrect ARM or Thumb state.
812 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
813 and also flushes the branch target cache at every context switch.
814 Note that setting specific bits in the ACTLR register may not be
815 available in non-secure mode.
817 config ARM_ERRATA_458693
818 bool "ARM errata: Processor deadlock when a false hazard is created"
820 depends on !ARCH_MULTIPLATFORM
822 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
823 erratum. For very specific sequences of memory operations, it is
824 possible for a hazard condition intended for a cache line to instead
825 be incorrectly associated with a different cache line. This false
826 hazard might then cause a processor deadlock. The workaround enables
827 the L1 caching of the NEON accesses and disables the PLD instruction
828 in the ACTLR register. Note that setting specific bits in the ACTLR
829 register may not be available in non-secure mode.
831 config ARM_ERRATA_460075
832 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
834 depends on !ARCH_MULTIPLATFORM
836 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
837 erratum. Any asynchronous access to the L2 cache may encounter a
838 situation in which recent store transactions to the L2 cache are lost
839 and overwritten with stale memory contents from external memory. The
840 workaround disables the write-allocate mode for the L2 cache via the
841 ACTLR register. Note that setting specific bits in the ACTLR register
842 may not be available in non-secure mode.
844 config ARM_ERRATA_742230
845 bool "ARM errata: DMB operation may be faulty"
846 depends on CPU_V7 && SMP
847 depends on !ARCH_MULTIPLATFORM
849 This option enables the workaround for the 742230 Cortex-A9
850 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
851 between two write operations may not ensure the correct visibility
852 ordering of the two writes. This workaround sets a specific bit in
853 the diagnostic register of the Cortex-A9 which causes the DMB
854 instruction to behave as a DSB, ensuring the correct behaviour of
857 config ARM_ERRATA_742231
858 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
859 depends on CPU_V7 && SMP
860 depends on !ARCH_MULTIPLATFORM
862 This option enables the workaround for the 742231 Cortex-A9
863 (r2p0..r2p2) erratum. Under certain conditions, specific to the
864 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
865 accessing some data located in the same cache line, may get corrupted
866 data due to bad handling of the address hazard when the line gets
867 replaced from one of the CPUs at the same time as another CPU is
868 accessing it. This workaround sets specific bits in the diagnostic
869 register of the Cortex-A9 which reduces the linefill issuing
870 capabilities of the processor.
872 config ARM_ERRATA_643719
873 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
874 depends on CPU_V7 && SMP
877 This option enables the workaround for the 643719 Cortex-A9 (prior to
878 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
879 register returns zero when it should return one. The workaround
880 corrects this value, ensuring cache maintenance operations which use
881 it behave as intended and avoiding data corruption.
883 config ARM_ERRATA_720789
884 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
887 This option enables the workaround for the 720789 Cortex-A9 (prior to
888 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
889 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
890 As a consequence of this erratum, some TLB entries which should be
891 invalidated are not, resulting in an incoherency in the system page
892 tables. The workaround changes the TLB flushing routines to invalidate
893 entries regardless of the ASID.
895 config ARM_ERRATA_743622
896 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
898 depends on !ARCH_MULTIPLATFORM
900 This option enables the workaround for the 743622 Cortex-A9
901 (r2p*) erratum. Under very rare conditions, a faulty
902 optimisation in the Cortex-A9 Store Buffer may lead to data
903 corruption. This workaround sets a specific bit in the diagnostic
904 register of the Cortex-A9 which disables the Store Buffer
905 optimisation, preventing the defect from occurring. This has no
906 visible impact on the overall performance or power consumption of the
909 config ARM_ERRATA_751472
910 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
912 depends on !ARCH_MULTIPLATFORM
914 This option enables the workaround for the 751472 Cortex-A9 (prior
915 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
916 completion of a following broadcasted operation if the second
917 operation is received by a CPU before the ICIALLUIS has completed,
918 potentially leading to corrupted entries in the cache or TLB.
920 config ARM_ERRATA_754322
921 bool "ARM errata: possible faulty MMU translations following an ASID switch"
924 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
925 r3p*) erratum. A speculative memory access may cause a page table walk
926 which starts prior to an ASID switch but completes afterwards. This
927 can populate the micro-TLB with a stale entry which may be hit with
928 the new ASID. This workaround places two dsb instructions in the mm
929 switching code so that no page table walks can cross the ASID switch.
931 config ARM_ERRATA_754327
932 bool "ARM errata: no automatic Store Buffer drain"
933 depends on CPU_V7 && SMP
935 This option enables the workaround for the 754327 Cortex-A9 (prior to
936 r2p0) erratum. The Store Buffer does not have any automatic draining
937 mechanism and therefore a livelock may occur if an external agent
938 continuously polls a memory location waiting to observe an update.
939 This workaround defines cpu_relax() as smp_mb(), preventing correctly
940 written polling loops from denying visibility of updates to memory.
942 config ARM_ERRATA_364296
943 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
946 This options enables the workaround for the 364296 ARM1136
947 r0p2 erratum (possible cache data corruption with
948 hit-under-miss enabled). It sets the undocumented bit 31 in
949 the auxiliary control register and the FI bit in the control
950 register, thus disabling hit-under-miss without putting the
951 processor into full low interrupt latency mode. ARM11MPCore
954 config ARM_ERRATA_764369
955 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
956 depends on CPU_V7 && SMP
958 This option enables the workaround for erratum 764369
959 affecting Cortex-A9 MPCore with two or more processors (all
960 current revisions). Under certain timing circumstances, a data
961 cache line maintenance operation by MVA targeting an Inner
962 Shareable memory region may fail to proceed up to either the
963 Point of Coherency or to the Point of Unification of the
964 system. This workaround adds a DSB instruction before the
965 relevant cache maintenance functions and sets a specific bit
966 in the diagnostic control register of the SCU.
968 config ARM_ERRATA_775420
969 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
972 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
973 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
974 operation aborts with MMU exception, it might cause the processor
975 to deadlock. This workaround puts DSB before executing ISB if
976 an abort may occur on cache maintenance.
978 config ARM_ERRATA_798181
979 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
980 depends on CPU_V7 && SMP
982 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
983 adequately shooting down all use of the old entries. This
984 option enables the Linux kernel workaround for this erratum
985 which sends an IPI to the CPUs that are running the same ASID
986 as the one being invalidated.
988 config ARM_ERRATA_773022
989 bool "ARM errata: incorrect instructions may be executed from loop buffer"
992 This option enables the workaround for the 773022 Cortex-A15
993 (up to r0p4) erratum. In certain rare sequences of code, the
994 loop buffer may deliver incorrect instructions. This
995 workaround disables the loop buffer to avoid the erratum.
997 config ARM_ERRATA_818325_852422
998 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1001 This option enables the workaround for:
1002 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1003 instruction might deadlock. Fixed in r0p1.
1004 - Cortex-A12 852422: Execution of a sequence of instructions might
1005 lead to either a data corruption or a CPU deadlock. Not fixed in
1006 any Cortex-A12 cores yet.
1007 This workaround for all both errata involves setting bit[12] of the
1008 Feature Register. This bit disables an optimisation applied to a
1009 sequence of 2 instructions that use opposing condition codes.
1011 config ARM_ERRATA_821420
1012 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1015 This option enables the workaround for the 821420 Cortex-A12
1016 (all revs) erratum. In very rare timing conditions, a sequence
1017 of VMOV to Core registers instructions, for which the second
1018 one is in the shadow of a branch or abort, can lead to a
1019 deadlock when the VMOV instructions are issued out-of-order.
1021 config ARM_ERRATA_825619
1022 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1025 This option enables the workaround for the 825619 Cortex-A12
1026 (all revs) erratum. Within rare timing constraints, executing a
1027 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1028 and Device/Strongly-Ordered loads and stores might cause deadlock
1030 config ARM_ERRATA_857271
1031 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1034 This option enables the workaround for the 857271 Cortex-A12
1035 (all revs) erratum. Under very rare timing conditions, the CPU might
1036 hang. The workaround is expected to have a < 1% performance impact.
1038 config ARM_ERRATA_852421
1039 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1042 This option enables the workaround for the 852421 Cortex-A17
1043 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1044 execution of a DMB ST instruction might fail to properly order
1045 stores from GroupA and stores from GroupB.
1047 config ARM_ERRATA_852423
1048 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1051 This option enables the workaround for:
1052 - Cortex-A17 852423: Execution of a sequence of instructions might
1053 lead to either a data corruption or a CPU deadlock. Not fixed in
1054 any Cortex-A17 cores yet.
1055 This is identical to Cortex-A12 erratum 852422. It is a separate
1056 config option from the A12 erratum due to the way errata are checked
1059 config ARM_ERRATA_857272
1060 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1063 This option enables the workaround for the 857272 Cortex-A17 erratum.
1064 This erratum is not known to be fixed in any A17 revision.
1065 This is identical to Cortex-A12 erratum 857271. It is a separate
1066 config option from the A12 erratum due to the way errata are checked
1071 source "arch/arm/common/Kconfig"
1078 Find out whether you have ISA slots on your motherboard. ISA is the
1079 name of a bus system, i.e. the way the CPU talks to the other stuff
1080 inside your box. Other bus systems are PCI, EISA, MicroChannel
1081 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1082 newer boards don't support it. If you have ISA, say Y, otherwise N.
1084 # Select ISA DMA controller support
1089 # Select ISA DMA interface
1093 config PCI_NANOENGINE
1094 bool "BSE nanoEngine PCI support"
1095 depends on SA1100_NANOENGINE
1097 Enable PCI on the BSE nanoEngine board.
1099 config ARM_ERRATA_814220
1100 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1103 The v7 ARM states that all cache and branch predictor maintenance
1104 operations that do not specify an address execute, relative to
1105 each other, in program order.
1106 However, because of this erratum, an L2 set/way cache maintenance
1107 operation can overtake an L1 set/way cache maintenance operation.
1108 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1113 menu "Kernel Features"
1118 This option should be selected by machines which have an SMP-
1121 The only effect of this option is to make the SMP-related
1122 options available to the user for configuration.
1125 bool "Symmetric Multi-Processing"
1126 depends on CPU_V6K || CPU_V7
1128 depends on MMU || ARM_MPU
1131 This enables support for systems with more than one CPU. If you have
1132 a system with only one CPU, say N. If you have a system with more
1133 than one CPU, say Y.
1135 If you say N here, the kernel will run on uni- and multiprocessor
1136 machines, but will use only one CPU of a multiprocessor machine. If
1137 you say Y here, the kernel will run on many, but not all,
1138 uniprocessor machines. On a uniprocessor machine, the kernel
1139 will run faster if you say N here.
1141 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1142 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1143 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1145 If you don't know what to do here, say N.
1148 bool "Allow booting SMP kernel on uniprocessor systems"
1149 depends on SMP && !XIP_KERNEL && MMU
1152 SMP kernels contain instructions which fail on non-SMP processors.
1153 Enabling this option allows the kernel to modify itself to make
1154 these instructions safe. Disabling it allows about 1K of space
1157 If you don't know what to do here, say Y.
1159 config ARM_CPU_TOPOLOGY
1160 bool "Support cpu topology definition"
1161 depends on SMP && CPU_V7
1164 Support ARM cpu topology definition. The MPIDR register defines
1165 affinity between processors which is then used to describe the cpu
1166 topology of an ARM System.
1169 bool "Multi-core scheduler support"
1170 depends on ARM_CPU_TOPOLOGY
1172 Multi-core scheduler support improves the CPU scheduler's decision
1173 making when dealing with multi-core CPU chips at a cost of slightly
1174 increased overhead in some places. If unsure say N here.
1177 bool "SMT scheduler support"
1178 depends on ARM_CPU_TOPOLOGY
1180 Improves the CPU scheduler's decision making when dealing with
1181 MultiThreading at a cost of slightly increased overhead in some
1182 places. If unsure say N here.
1187 This option enables support for the ARM snoop control unit
1189 config HAVE_ARM_ARCH_TIMER
1190 bool "Architected timer support"
1192 select ARM_ARCH_TIMER
1194 This option enables support for the ARM architected timer
1199 This options enables support for the ARM timer and watchdog unit
1202 bool "Multi-Cluster Power Management"
1203 depends on CPU_V7 && SMP
1205 This option provides the common power management infrastructure
1206 for (multi-)cluster based systems, such as big.LITTLE based
1209 config MCPM_QUAD_CLUSTER
1213 To avoid wasting resources unnecessarily, MCPM only supports up
1214 to 2 clusters by default.
1215 Platforms with 3 or 4 clusters that use MCPM must select this
1216 option to allow the additional clusters to be managed.
1219 bool "big.LITTLE support (Experimental)"
1220 depends on CPU_V7 && SMP
1223 This option enables support selections for the big.LITTLE
1224 system architecture.
1227 bool "big.LITTLE switcher support"
1228 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1231 The big.LITTLE "switcher" provides the core functionality to
1232 transparently handle transition between a cluster of A15's
1233 and a cluster of A7's in a big.LITTLE system.
1235 config BL_SWITCHER_DUMMY_IF
1236 tristate "Simple big.LITTLE switcher user interface"
1237 depends on BL_SWITCHER && DEBUG_KERNEL
1239 This is a simple and dummy char dev interface to control
1240 the big.LITTLE switcher core code. It is meant for
1241 debugging purposes only.
1244 prompt "Memory split"
1248 Select the desired split between kernel and user memory.
1250 If you are not absolutely sure what you are doing, leave this
1254 bool "3G/1G user/kernel split"
1255 config VMSPLIT_3G_OPT
1256 depends on !ARM_LPAE
1257 bool "3G/1G user/kernel split (for full 1G low memory)"
1259 bool "2G/2G user/kernel split"
1261 bool "1G/3G user/kernel split"
1266 default PHYS_OFFSET if !MMU
1267 default 0x40000000 if VMSPLIT_1G
1268 default 0x80000000 if VMSPLIT_2G
1269 default 0xB0000000 if VMSPLIT_3G_OPT
1272 config KASAN_SHADOW_OFFSET
1275 default 0x1f000000 if PAGE_OFFSET=0x40000000
1276 default 0x5f000000 if PAGE_OFFSET=0x80000000
1277 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1278 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1282 int "Maximum number of CPUs (2-32)"
1283 range 2 16 if DEBUG_KMAP_LOCAL
1284 range 2 32 if !DEBUG_KMAP_LOCAL
1288 The maximum number of CPUs that the kernel can support.
1289 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1290 debugging is enabled, which uses half of the per-CPU fixmap
1291 slots as guard regions.
1294 bool "Support for hot-pluggable CPUs"
1296 select GENERIC_IRQ_MIGRATION
1298 Say Y here to experiment with turning CPUs off and on. CPUs
1299 can be controlled through /sys/devices/system/cpu.
1302 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1303 depends on HAVE_ARM_SMCCC
1306 Say Y here if you want Linux to communicate with system firmware
1307 implementing the PSCI specification for CPU-centric power
1308 management operations described in ARM document number ARM DEN
1309 0022A ("Power State Coordination Interface System Software on
1312 # The GPIO number here must be sorted by descending number. In case of
1313 # a multiplatform kernel, we just want the highest value required by the
1314 # selected platforms.
1317 default 2048 if ARCH_INTEL_SOCFPGA
1318 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1319 ARCH_ZYNQ || ARCH_ASPEED
1320 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1321 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1322 default 416 if ARCH_SUNXI
1323 default 392 if ARCH_U8500
1324 default 352 if ARCH_VT8500
1325 default 288 if ARCH_ROCKCHIP
1326 default 264 if MACH_H4700
1329 Maximum number of GPIOs in the system.
1331 If unsure, leave the default value.
1335 default 128 if SOC_AT91RM9200
1339 depends on HZ_FIXED = 0
1340 prompt "Timer frequency"
1364 default HZ_FIXED if HZ_FIXED != 0
1365 default 100 if HZ_100
1366 default 200 if HZ_200
1367 default 250 if HZ_250
1368 default 300 if HZ_300
1369 default 500 if HZ_500
1373 def_bool HIGH_RES_TIMERS
1375 config THUMB2_KERNEL
1376 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1377 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1378 default y if CPU_THUMBONLY
1381 By enabling this option, the kernel will be compiled in
1386 config ARM_PATCH_IDIV
1387 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1388 depends on CPU_32v7 && !XIP_KERNEL
1391 The ARM compiler inserts calls to __aeabi_idiv() and
1392 __aeabi_uidiv() when it needs to perform division on signed
1393 and unsigned integers. Some v7 CPUs have support for the sdiv
1394 and udiv instructions that can be used to implement those
1397 Enabling this option allows the kernel to modify itself to
1398 replace the first two instructions of these library functions
1399 with the sdiv or udiv plus "bx lr" instructions when the CPU
1400 it is running on supports them. Typically this will be faster
1401 and less power intensive than running the original library
1402 code to do integer division.
1405 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1406 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1407 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1409 This option allows for the kernel to be compiled using the latest
1410 ARM ABI (aka EABI). This is only useful if you are using a user
1411 space environment that is also compiled with EABI.
1413 Since there are major incompatibilities between the legacy ABI and
1414 EABI, especially with regard to structure member alignment, this
1415 option also changes the kernel syscall calling convention to
1416 disambiguate both ABIs and allow for backward compatibility support
1417 (selected with CONFIG_OABI_COMPAT).
1419 To use this you need GCC version 4.0.0 or later.
1422 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1423 depends on AEABI && !THUMB2_KERNEL
1425 This option preserves the old syscall interface along with the
1426 new (ARM EABI) one. It also provides a compatibility layer to
1427 intercept syscalls that have structure arguments which layout
1428 in memory differs between the legacy ABI and the new ARM EABI
1429 (only for non "thumb" binaries). This option adds a tiny
1430 overhead to all syscalls and produces a slightly larger kernel.
1432 The seccomp filter system will not be available when this is
1433 selected, since there is no way yet to sensibly distinguish
1434 between calling conventions during filtering.
1436 If you know you'll be using only pure EABI user space then you
1437 can say N here. If this option is not selected and you attempt
1438 to execute a legacy ABI binary then the result will be
1439 UNPREDICTABLE (in fact it can be predicted that it won't work
1440 at all). If in doubt say N.
1442 config ARCH_SELECT_MEMORY_MODEL
1445 config ARCH_FLATMEM_ENABLE
1448 config ARCH_SPARSEMEM_ENABLE
1450 select SPARSEMEM_STATIC if SPARSEMEM
1453 bool "High Memory Support"
1457 The address space of ARM processors is only 4 Gigabytes large
1458 and it has to accommodate user address space, kernel address
1459 space as well as some memory mapped IO. That means that, if you
1460 have a large amount of physical memory and/or IO, not all of the
1461 memory can be "permanently mapped" by the kernel. The physical
1462 memory that is not permanently mapped is called "high memory".
1464 Depending on the selected kernel/user memory split, minimum
1465 vmalloc space and actual amount of RAM, you may not need this
1466 option which should result in a slightly faster kernel.
1471 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1475 The VM uses one page of physical memory for each page table.
1476 For systems with a lot of processes, this can use a lot of
1477 precious low memory, eventually leading to low memory being
1478 consumed by page tables. Setting this option will allow
1479 user-space 2nd level page tables to reside in high memory.
1481 config CPU_SW_DOMAIN_PAN
1482 bool "Enable use of CPU domains to implement privileged no-access"
1483 depends on MMU && !ARM_LPAE
1486 Increase kernel security by ensuring that normal kernel accesses
1487 are unable to access userspace addresses. This can help prevent
1488 use-after-free bugs becoming an exploitable privilege escalation
1489 by ensuring that magic values (such as LIST_POISON) will always
1490 fault when dereferenced.
1492 CPUs with low-vector mappings use a best-efforts implementation.
1493 Their lower 1MB needs to remain accessible for the vectors, but
1494 the remainder of userspace will become appropriately inaccessible.
1496 config HW_PERF_EVENTS
1500 config ARCH_WANT_GENERAL_HUGETLB
1503 config ARM_MODULE_PLTS
1504 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1508 Allocate PLTs when loading modules so that jumps and calls whose
1509 targets are too far away for their relative offsets to be encoded
1510 in the instructions themselves can be bounced via veneers in the
1511 module's PLT. This allows modules to be allocated in the generic
1512 vmalloc area after the dedicated module memory area has been
1513 exhausted. The modules will use slightly more memory, but after
1514 rounding up to page size, the actual memory footprint is usually
1517 Disabling this is usually safe for small single-platform
1518 configurations. If unsure, say y.
1520 config FORCE_MAX_ZONEORDER
1521 int "Maximum zone order"
1522 default "12" if SOC_AM33XX
1523 default "9" if SA1111
1526 The kernel memory allocator divides physically contiguous memory
1527 blocks into "zones", where each zone is a power of two number of
1528 pages. This option selects the largest power of two that the kernel
1529 keeps in the memory allocator. If you need to allocate very large
1530 blocks of physically contiguous memory, then you may need to
1531 increase this value.
1533 This config option is actually maximum order plus one. For example,
1534 a value of 11 means that the largest free memory block is 2^10 pages.
1536 config ALIGNMENT_TRAP
1537 def_bool CPU_CP15_MMU
1538 select HAVE_PROC_CPU if PROC_FS
1540 ARM processors cannot fetch/store information which is not
1541 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1542 address divisible by 4. On 32-bit ARM processors, these non-aligned
1543 fetch/store instructions will be emulated in software if you say
1544 here, which has a severe performance impact. This is necessary for
1545 correct operation of some network protocols. With an IP-only
1546 configuration it is safe to say N, otherwise say Y.
1548 config UACCESS_WITH_MEMCPY
1549 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1551 default y if CPU_FEROCEON
1553 Implement faster copy_to_user and clear_user methods for CPU
1554 cores where a 8-word STM instruction give significantly higher
1555 memory write throughput than a sequence of individual 32bit stores.
1557 A possible side effect is a slight increase in scheduling latency
1558 between threads sharing the same address space if they invoke
1559 such copy operations with large buffers.
1561 However, if the CPU data cache is using a write-allocate mode,
1562 this option is unlikely to provide any performance gain.
1565 bool "Enable paravirtualization code"
1567 This changes the kernel so it can modify itself when it is run
1568 under a hypervisor, potentially improving performance significantly
1569 over full virtualization.
1571 config PARAVIRT_TIME_ACCOUNTING
1572 bool "Paravirtual steal time accounting"
1575 Select this option to enable fine granularity task steal time
1576 accounting. Time spent executing other tasks in parallel with
1577 the current vCPU is discounted from the vCPU power. To account for
1578 that, there can be a small performance impact.
1580 If in doubt, say N here.
1587 bool "Xen guest support on ARM"
1588 depends on ARM && AEABI && OF
1589 depends on CPU_V7 && !CPU_V6
1590 depends on !GENERIC_ATOMIC64
1592 select ARCH_DMA_ADDR_T_64BIT
1598 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1600 config STACKPROTECTOR_PER_TASK
1601 bool "Use a unique stack canary value for each task"
1602 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1603 select GCC_PLUGIN_ARM_SSP_PER_TASK
1606 Due to the fact that GCC uses an ordinary symbol reference from
1607 which to load the value of the stack canary, this value can only
1608 change at reboot time on SMP systems, and all tasks running in the
1609 kernel's address space are forced to use the same canary value for
1610 the entire duration that the system is up.
1612 Enable this option to switch to a different method that uses a
1613 different canary value for each task.
1620 bool "Flattened Device Tree support"
1624 Include support for flattened device tree machine descriptions.
1627 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1630 This is the traditional way of passing data to the kernel at boot
1631 time. If you are solely relying on the flattened device tree (or
1632 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1633 to remove ATAGS support from your kernel binary. If unsure,
1636 config DEPRECATED_PARAM_STRUCT
1637 bool "Provide old way to pass kernel parameters"
1640 This was deprecated in 2001 and announced to live on for 5 years.
1641 Some old boot loaders still use this way.
1643 # Compressed boot loader in ROM. Yes, we really want to ask about
1644 # TEXT and BSS so we preserve their values in the config files.
1645 config ZBOOT_ROM_TEXT
1646 hex "Compressed ROM boot loader base address"
1649 The physical address at which the ROM-able zImage is to be
1650 placed in the target. Platforms which normally make use of
1651 ROM-able zImage formats normally set this to a suitable
1652 value in their defconfig file.
1654 If ZBOOT_ROM is not enabled, this has no effect.
1656 config ZBOOT_ROM_BSS
1657 hex "Compressed ROM boot loader BSS address"
1660 The base address of an area of read/write memory in the target
1661 for the ROM-able zImage which must be available while the
1662 decompressor is running. It must be large enough to hold the
1663 entire decompressed kernel plus an additional 128 KiB.
1664 Platforms which normally make use of ROM-able zImage formats
1665 normally set this to a suitable value in their defconfig file.
1667 If ZBOOT_ROM is not enabled, this has no effect.
1670 bool "Compressed boot loader in ROM/flash"
1671 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1672 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1674 Say Y here if you intend to execute your compressed kernel image
1675 (zImage) directly from ROM or flash. If unsure, say N.
1677 config ARM_APPENDED_DTB
1678 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1681 With this option, the boot code will look for a device tree binary
1682 (DTB) appended to zImage
1683 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1685 This is meant as a backward compatibility convenience for those
1686 systems with a bootloader that can't be upgraded to accommodate
1687 the documented boot protocol using a device tree.
1689 Beware that there is very little in terms of protection against
1690 this option being confused by leftover garbage in memory that might
1691 look like a DTB header after a reboot if no actual DTB is appended
1692 to zImage. Do not leave this option active in a production kernel
1693 if you don't intend to always append a DTB. Proper passing of the
1694 location into r2 of a bootloader provided DTB is always preferable
1697 config ARM_ATAG_DTB_COMPAT
1698 bool "Supplement the appended DTB with traditional ATAG information"
1699 depends on ARM_APPENDED_DTB
1701 Some old bootloaders can't be updated to a DTB capable one, yet
1702 they provide ATAGs with memory configuration, the ramdisk address,
1703 the kernel cmdline string, etc. Such information is dynamically
1704 provided by the bootloader and can't always be stored in a static
1705 DTB. To allow a device tree enabled kernel to be used with such
1706 bootloaders, this option allows zImage to extract the information
1707 from the ATAG list and store it at run time into the appended DTB.
1710 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1711 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1713 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1714 bool "Use bootloader kernel arguments if available"
1716 Uses the command-line options passed by the boot loader instead of
1717 the device tree bootargs property. If the boot loader doesn't provide
1718 any, the device tree bootargs property will be used.
1720 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1721 bool "Extend with bootloader kernel arguments"
1723 The command-line arguments provided by the boot loader will be
1724 appended to the the device tree bootargs property.
1729 string "Default kernel command string"
1732 On some architectures (e.g. CATS), there is currently no way
1733 for the boot loader to pass arguments to the kernel. For these
1734 architectures, you should supply some command-line options at build
1735 time by entering them here. As a minimum, you should specify the
1736 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1739 prompt "Kernel command line type" if CMDLINE != ""
1740 default CMDLINE_FROM_BOOTLOADER
1743 config CMDLINE_FROM_BOOTLOADER
1744 bool "Use bootloader kernel arguments if available"
1746 Uses the command-line options passed by the boot loader. If
1747 the boot loader doesn't provide any, the default kernel command
1748 string provided in CMDLINE will be used.
1750 config CMDLINE_EXTEND
1751 bool "Extend bootloader kernel arguments"
1753 The command-line arguments provided by the boot loader will be
1754 appended to the default kernel command string.
1756 config CMDLINE_FORCE
1757 bool "Always use the default kernel command string"
1759 Always use the default kernel command string, even if the boot
1760 loader passes other arguments to the kernel.
1761 This is useful if you cannot or don't want to change the
1762 command-line options your boot loader passes to the kernel.
1766 bool "Kernel Execute-In-Place from ROM"
1767 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1769 Execute-In-Place allows the kernel to run from non-volatile storage
1770 directly addressable by the CPU, such as NOR flash. This saves RAM
1771 space since the text section of the kernel is not loaded from flash
1772 to RAM. Read-write sections, such as the data section and stack,
1773 are still copied to RAM. The XIP kernel is not compressed since
1774 it has to run directly from flash, so it will take more space to
1775 store it. The flash address used to link the kernel object files,
1776 and for storing it, is configuration dependent. Therefore, if you
1777 say Y here, you must know the proper physical address where to
1778 store the kernel image depending on your own flash memory usage.
1780 Also note that the make target becomes "make xipImage" rather than
1781 "make zImage" or "make Image". The final kernel binary to put in
1782 ROM memory will be arch/arm/boot/xipImage.
1786 config XIP_PHYS_ADDR
1787 hex "XIP Kernel Physical Location"
1788 depends on XIP_KERNEL
1789 default "0x00080000"
1791 This is the physical address in your flash memory the kernel will
1792 be linked for and stored to. This address is dependent on your
1795 config XIP_DEFLATED_DATA
1796 bool "Store kernel .data section compressed in ROM"
1797 depends on XIP_KERNEL
1800 Before the kernel is actually executed, its .data section has to be
1801 copied to RAM from ROM. This option allows for storing that data
1802 in compressed form and decompressed to RAM rather than merely being
1803 copied, saving some precious ROM space. A possible drawback is a
1804 slightly longer boot delay.
1807 bool "Kexec system call (EXPERIMENTAL)"
1808 depends on (!SMP || PM_SLEEP_SMP)
1812 kexec is a system call that implements the ability to shutdown your
1813 current kernel, and to start another kernel. It is like a reboot
1814 but it is independent of the system firmware. And like a reboot
1815 you can start any kernel with it, not just Linux.
1817 It is an ongoing process to be certain the hardware in a machine
1818 is properly shutdown, so do not be surprised if this code does not
1819 initially work for you.
1822 bool "Export atags in procfs"
1823 depends on ATAGS && KEXEC
1826 Should the atags used to boot the kernel be exported in an "atags"
1827 file in procfs. Useful with kexec.
1830 bool "Build kdump crash kernel (EXPERIMENTAL)"
1832 Generate crash dump after being started by kexec. This should
1833 be normally only set in special crash dump kernels which are
1834 loaded in the main kernel with kexec-tools into a specially
1835 reserved region and then later executed after a crash by
1836 kdump/kexec. The crash dump kernel must be compiled to a
1837 memory address not used by the main kernel
1839 For more details see Documentation/admin-guide/kdump/kdump.rst
1841 config AUTO_ZRELADDR
1842 bool "Auto calculation of the decompressed kernel image address"
1844 ZRELADDR is the physical address where the decompressed kernel
1845 image will be placed. If AUTO_ZRELADDR is selected, the address
1846 will be determined at run-time, either by masking the current IP
1847 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1848 This assumes the zImage being placed in the first 128MB from
1855 bool "UEFI runtime support"
1856 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1858 select EFI_PARAMS_FROM_FDT
1860 select EFI_GENERIC_STUB
1861 select EFI_RUNTIME_WRAPPERS
1863 This option provides support for runtime services provided
1864 by UEFI firmware (such as non-volatile variables, realtime
1865 clock, and platform reset). A UEFI stub is also provided to
1866 allow the kernel to be booted as an EFI application. This
1867 is only useful for kernels that may run on systems that have
1871 bool "Enable support for SMBIOS (DMI) tables"
1875 This enables SMBIOS/DMI feature for systems.
1877 This option is only useful on systems that have UEFI firmware.
1878 However, even with this option, the resultant kernel should
1879 continue to boot on existing non-UEFI platforms.
1881 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1882 i.e., the the practice of identifying the platform via DMI to
1883 decide whether certain workarounds for buggy hardware and/or
1884 firmware need to be enabled. This would require the DMI subsystem
1885 to be enabled much earlier than we do on ARM, which is non-trivial.
1889 menu "CPU Power Management"
1891 source "drivers/cpufreq/Kconfig"
1893 source "drivers/cpuidle/Kconfig"
1897 menu "Floating point emulation"
1899 comment "At least one emulation must be selected"
1902 bool "NWFPE math emulation"
1903 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1905 Say Y to include the NWFPE floating point emulator in the kernel.
1906 This is necessary to run most binaries. Linux does not currently
1907 support floating point hardware so you need to say Y here even if
1908 your machine has an FPA or floating point co-processor podule.
1910 You may say N here if you are going to load the Acorn FPEmulator
1911 early in the bootup.
1914 bool "Support extended precision"
1915 depends on FPE_NWFPE
1917 Say Y to include 80-bit support in the kernel floating-point
1918 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1919 Note that gcc does not generate 80-bit operations by default,
1920 so in most cases this option only enlarges the size of the
1921 floating point emulator without any good reason.
1923 You almost surely want to say N here.
1926 bool "FastFPE math emulation (EXPERIMENTAL)"
1927 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1929 Say Y here to include the FAST floating point emulator in the kernel.
1930 This is an experimental much faster emulator which now also has full
1931 precision for the mantissa. It does not support any exceptions.
1932 It is very simple, and approximately 3-6 times faster than NWFPE.
1934 It should be sufficient for most programs. It may be not suitable
1935 for scientific calculations, but you have to check this for yourself.
1936 If you do not feel you need a faster FP emulation you should better
1940 bool "VFP-format floating point maths"
1941 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1943 Say Y to include VFP support code in the kernel. This is needed
1944 if your hardware includes a VFP unit.
1946 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1947 release notes and additional status information.
1949 Say N if your target does not have VFP hardware.
1957 bool "Advanced SIMD (NEON) Extension support"
1958 depends on VFPv3 && CPU_V7
1960 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1963 config KERNEL_MODE_NEON
1964 bool "Support for NEON in kernel mode"
1965 depends on NEON && AEABI
1967 Say Y to include support for NEON in kernel mode.
1971 menu "Power management options"
1973 source "kernel/power/Kconfig"
1975 config ARCH_SUSPEND_POSSIBLE
1976 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1977 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1980 config ARM_CPU_SUSPEND
1981 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1982 depends on ARCH_SUSPEND_POSSIBLE
1984 config ARCH_HIBERNATION_POSSIBLE
1987 default y if ARCH_SUSPEND_POSSIBLE
1991 source "drivers/firmware/Kconfig"
1994 source "arch/arm/crypto/Kconfig"
1997 source "arch/arm/Kconfig.assembler"