2 * Copyright(c) 2015 EZchip Technologies.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
17 #ifndef _PLAT_EZNPS_CTOP_H
18 #define _PLAT_EZNPS_CTOP_H
20 #ifndef CONFIG_ARC_PLAT_EZNPS
21 #error "Incorrect ctop.h include"
24 #include <soc/nps/common.h>
26 /* core auxiliary registers */
28 #define CTOP_AUX_BASE (-0x800)
30 #define CTOP_AUX_BASE 0xFFFFF800
33 #define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
34 #define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
35 #define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
36 #define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
37 #define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
38 #define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
39 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
40 #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
41 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
42 #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
43 #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
44 #define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
45 #define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
46 #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
48 /* EZchip core instructions */
49 #define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
50 #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
51 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
52 #define CTOP_INST_SCHD_RW 0x3E6F7004
53 #define CTOP_INST_SCHD_RD 0x3E6F7084
54 #define CTOP_INST_ASRI_0_R3 0x3B56003E
55 #define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
56 #define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
57 #define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
58 #define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
59 #define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
60 #define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
62 /* Do not use D$ for address in 2G-3G */
63 #define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28)
65 #define NPS_MSU_EN_CFG 0x80
66 #define NPS_CRG_BLKID 0x480
67 #define NPS_CRG_SYNC_BIT _BITUL(0)
68 #define NPS_GIM_BLKID 0x5C0
70 /* GIM registers and fields*/
71 #define NPS_GIM_UART_LINE _BITUL(7)
72 #define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10)
73 #define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11)
74 #define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25)
75 #define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26)
78 /* Functional registers definition */
79 struct nps_host_reg_mtm_cfg {
82 u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
83 __reserved:9, nat:3, ten:16;
89 struct nps_host_reg_mtm_cpu_cfg {
92 u32 csa:22, dmsid:6, __reserved:3, cs:1;
98 struct nps_host_reg_thr_init {
101 u32 str:1, __reserved:27, thr_id:4;
107 struct nps_host_reg_thr_init_sts {
110 u32 bsy:1, err:1, __reserved:26, thr_id:4;
116 struct nps_host_reg_msu_en_cfg {
120 rtc_en:1, ipc_en:1, gim_1_en:1,
121 gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
122 buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
123 buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
124 buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
125 buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
126 pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
132 struct nps_host_reg_gim_p_int_dst {
135 u32 int_out_en:1, __reserved1:4,
136 is:1, intm:2, __reserved2:4,
137 nid:4, __reserved3:4, cid:4,
138 __reserved4:4, tid:4;
144 /* AUX registers definition */
145 struct nps_host_reg_aux_udmc {
148 u32 dcp:1, cme:1, __reserved:19, nat:3,
149 __reserved2:5, dcas:3;
155 struct nps_host_reg_aux_mt_ctrl {
158 u32 mten:1, hsen:1, scd:1, sten:1,
159 st_cnt:8, __reserved:8,
160 hs_cnt:8, __reserved1:4;
166 struct nps_host_reg_aux_hw_comply {
169 u32 me:1, le:1, te:1, knc:1, __reserved:28;
175 struct nps_host_reg_aux_lpc {
178 u32 mep:1, __reserved:31;
185 #define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
188 #define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
189 #define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
190 #define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
191 #define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
192 #define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
193 #define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
194 #define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
195 #define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
199 .macro GET_CPU_ID reg
200 lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID]
201 #ifndef CONFIG_EZNPS_MTM_EXT
206 #endif /* __ASSEMBLY__ */
208 #endif /* _PLAT_EZNPS_CTOP_H */