2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 * -sched_clock( ) no longer jiffies based. Uses the same clocksource
12 * Rajeshwarr/Vineetg: Mar 2008
13 * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
14 * for arch independent gettimeofday()
15 * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
17 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
21 * Each can programmed to go from @count to @limit and optionally
22 * interrupt when that happens.
23 * A write to Control Register clears the Interrupt
25 * We've designated TIMER0 for events (clockevents)
26 * while TIMER1 for free running (clocksource)
28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
29 * which however is currently broken
32 #include <linux/interrupt.h>
33 #include <linux/clk.h>
34 #include <linux/clk-provider.h>
35 #include <linux/clocksource.h>
36 #include <linux/clockchips.h>
37 #include <linux/cpu.h>
39 #include <linux/of_irq.h>
41 #include <asm/arcregs.h>
45 /* Timer related Aux registers */
46 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
47 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
48 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
49 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
50 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
51 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
53 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
54 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
56 #define ARC_TIMER_MAX 0xFFFFFFFF
58 static unsigned long arc_timer_freq;
60 static int noinline arc_get_timer_clk(struct device_node *node)
65 clk = of_clk_get(node, 0);
67 pr_err("timer missing clk");
71 ret = clk_prepare_enable(clk);
73 pr_err("Couldn't enable parent clk\n");
77 arc_timer_freq = clk_get_rate(clk);
82 /********** Clock Source Device *********/
84 #ifdef CONFIG_ARC_HAS_GFRC
86 static cycle_t arc_read_gfrc(struct clocksource *cs)
90 #ifdef CONFIG_CPU_BIG_ENDIAN
98 local_irq_save(flags);
100 __mcip_cmd(CMD_GFRC_READ_LO, 0);
101 stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
103 __mcip_cmd(CMD_GFRC_READ_HI, 0);
104 stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
106 local_irq_restore(flags);
111 static struct clocksource arc_counter_gfrc = {
112 .name = "ARConnect GFRC",
114 .read = arc_read_gfrc,
115 .mask = CLOCKSOURCE_MASK(64),
116 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
119 static int __init arc_cs_setup_gfrc(struct device_node *node)
121 int exists = cpuinfo_arc700[0].extn.gfrc;
124 if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
127 ret = arc_get_timer_clk(node);
131 return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
133 CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
137 #ifdef CONFIG_ARC_HAS_RTC
139 #define AUX_RTC_CTRL 0x103
140 #define AUX_RTC_LOW 0x104
141 #define AUX_RTC_HIGH 0x105
143 static cycle_t arc_read_rtc(struct clocksource *cs)
145 unsigned long status;
147 #ifdef CONFIG_CPU_BIG_ENDIAN
148 struct { u32 high, low; };
150 struct { u32 low, high; };
156 * hardware has an internal state machine which tracks readout of
157 * low/high and updates the CTRL.status if
158 * - interrupt/exception taken between the two reads
159 * - high increments after low has been read
162 stamp.low = read_aux_reg(AUX_RTC_LOW);
163 stamp.high = read_aux_reg(AUX_RTC_HIGH);
164 status = read_aux_reg(AUX_RTC_CTRL);
165 } while (!(status & _BITUL(31)));
170 static struct clocksource arc_counter_rtc = {
173 .read = arc_read_rtc,
174 .mask = CLOCKSOURCE_MASK(64),
175 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
178 static int __init arc_cs_setup_rtc(struct device_node *node)
180 int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
183 if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
186 /* Local to CPU hence not usable in SMP */
187 if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
190 ret = arc_get_timer_clk(node);
194 write_aux_reg(AUX_RTC_CTRL, 1);
196 return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
198 CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
203 * 32bit TIMER1 to keep counting monotonically and wraparound
206 static cycle_t arc_read_timer1(struct clocksource *cs)
208 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
211 static struct clocksource arc_counter_timer1 = {
212 .name = "ARC Timer1",
214 .read = arc_read_timer1,
215 .mask = CLOCKSOURCE_MASK(32),
216 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
219 static int __init arc_cs_setup_timer1(struct device_node *node)
223 /* Local to CPU hence not usable in SMP */
224 if (IS_ENABLED(CONFIG_SMP))
227 ret = arc_get_timer_clk(node);
231 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
232 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
233 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
235 return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
238 /********** Clock Event Device *********/
240 static int arc_timer_irq;
243 * Arm the timer to interrupt after @cycles
244 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
246 static void arc_timer_event_setup(unsigned int cycles)
248 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
249 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
251 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
255 static int arc_clkevent_set_next_event(unsigned long delta,
256 struct clock_event_device *dev)
258 arc_timer_event_setup(delta);
262 static int arc_clkevent_set_periodic(struct clock_event_device *dev)
265 * At X Hz, 1 sec = 1000ms -> X cycles;
266 * 10ms -> X / 100 cycles
268 arc_timer_event_setup(arc_timer_freq / HZ);
272 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
273 .name = "ARC Timer0",
274 .features = CLOCK_EVT_FEAT_ONESHOT |
275 CLOCK_EVT_FEAT_PERIODIC,
277 .set_next_event = arc_clkevent_set_next_event,
278 .set_state_periodic = arc_clkevent_set_periodic,
281 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
284 * Note that generic IRQ core could have passed @evt for @dev_id if
285 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
287 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
288 int irq_reenable = clockevent_state_periodic(evt);
291 * Any write to CTRL reg ACks the interrupt, we rewrite the
292 * Count when [N]ot [H]alted bit.
293 * And re-arm it if perioid by [I]nterrupt [E]nable bit
295 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
297 evt->event_handler(evt);
303 static int arc_timer_starting_cpu(unsigned int cpu)
305 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
307 evt->cpumask = cpumask_of(smp_processor_id());
309 clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX);
310 enable_percpu_irq(arc_timer_irq, 0);
314 static int arc_timer_dying_cpu(unsigned int cpu)
316 disable_percpu_irq(arc_timer_irq);
321 * clockevent setup for boot CPU
323 static int __init arc_clockevent_setup(struct device_node *node)
325 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
328 arc_timer_irq = irq_of_parse_and_map(node, 0);
329 if (arc_timer_irq <= 0) {
330 pr_err("clockevent: missing irq");
334 ret = arc_get_timer_clk(node);
336 pr_err("clockevent: missing clk");
340 /* Needs apriori irq_set_percpu_devid() done in intc map function */
341 ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
342 "Timer0 (per-cpu-tick)", evt);
344 pr_err("clockevent: unable to request irq\n");
348 ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
349 "AP_ARC_TIMER_STARTING",
350 arc_timer_starting_cpu,
351 arc_timer_dying_cpu);
353 pr_err("Failed to setup hotplug state");
359 static int __init arc_of_timer_init(struct device_node *np)
361 static int init_count = 0;
366 ret = arc_clockevent_setup(np);
368 ret = arc_cs_setup_timer1(np);
373 CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
376 * Called from start_kernel() - boot CPU only
378 void __init time_init(void)