arch/arc/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 #include <linux/seq_file.h>
   7 #include <linux/fs.h>
   8 #include <linux/delay.h>
   9 #include <linux/root_dev.h>
  10 #include <linux/clk.h>
  11 #include <linux/clocksource.h>
  12 #include <linux/console.h>
  13 #include <linux/module.h>
  14 #include <linux/sizes.h>
  15 #include <linux/cpu.h>
  16 #include <linux/of_clk.h>
  17 #include <linux/of_fdt.h>
  18 #include <linux/of.h>
  19 #include <linux/cache.h>
  20 #include <uapi/linux/mount.h>
  21 #include <asm/sections.h>
  22 #include <asm/arcregs.h>
  23 #include <asm/asserts.h>
  24 #include <asm/tlb.h>
  25 #include <asm/setup.h>
  26 #include <asm/page.h>
  27 #include <asm/irq.h>
  28 #include <asm/unwind.h>
  29 #include <asm/mach_desc.h>
  30 #include <asm/smp.h>
  31 #include <asm/dsp-impl.h>
  32
  33 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
  34
  35 unsigned int intr_to_DE_cnt;
  36
  37 /* Part of U-boot ABI: see head.S */
  38 int __initdata uboot_tag;
  39 int __initdata uboot_magic;
  40 char __initdata *uboot_arg;
  41
  42 const struct machine_desc *machine_desc;
  43
  44 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
  45
  46 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  47
  48 static const struct id_to_str arc_legacy_rel[] = {
  49         /* ID.ARCVER,   Release */
  50 #ifdef CONFIG_ISA_ARCOMPACT
  51         { 0x34,         "R4.10"},
  52         { 0x35,         "R4.11"},
  53 #else
  54         { 0x51,         "R2.0" },
  55         { 0x52,         "R2.1" },
  56         { 0x53,         "R3.0" },
  57 #endif
  58         { 0x00,         NULL   }
  59 };
  60
  61 static const struct id_to_str arc_hs_ver54_rel[] = {
  62         /* UARCH.MAJOR, Release */
  63         {  0,           "R3.10a"},
  64         {  1,           "R3.50a"},
  65         {  2,           "R3.60a"},
  66         {  3,           "R4.00a"},
  67         {  0xFF,        NULL   }
  68 };
  69
  70 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
  71 {
  72         if (is_isa_arcompact()) {
  73                 struct bcr_iccm_arcompact iccm;
  74                 struct bcr_dccm_arcompact dccm;
  75
  76                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  77                 if (iccm.ver) {
  78                         cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
  79                         cpu->iccm.base_addr = iccm.base << 16;
  80                 }
  81
  82                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
  83                 if (dccm.ver) {
  84                         unsigned long base;
  85                         cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
  86
  87                         base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
  88                         cpu->dccm.base_addr = base & ~0xF;
  89                 }
  90         } else {
  91                 struct bcr_iccm_arcv2 iccm;
  92                 struct bcr_dccm_arcv2 dccm;
  93                 unsigned long region;
  94
  95                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  96                 if (iccm.ver) {
  97                         cpu->iccm.sz = 256 << iccm.sz00;        /* 512B to 16M */
  98                         if (iccm.sz00 == 0xF && iccm.sz01 > 0)
  99                                 cpu->iccm.sz <<= iccm.sz01;
 100
 101                         region = read_aux_reg(ARC_REG_AUX_ICCM);
 102                         cpu->iccm.base_addr = region & 0xF0000000;
 103                 }
 104
 105                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
 106                 if (dccm.ver) {
 107                         cpu->dccm.sz = 256 << dccm.sz0;
 108                         if (dccm.sz0 == 0xF && dccm.sz1 > 0)
 109                                 cpu->dccm.sz <<= dccm.sz1;
 110
 111                         region = read_aux_reg(ARC_REG_AUX_DCCM);
 112                         cpu->dccm.base_addr = region & 0xF0000000;
 113                 }
 114         }
 115 }
 116
 117 static void decode_arc_core(struct cpuinfo_arc *cpu)
 118 {
 119         struct bcr_uarch_build_arcv2 uarch;
 120         const struct id_to_str *tbl;
 121
 122         if (cpu->core.family < 0x54) { /* includes arc700 */
 123
 124                 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
 125                         if (cpu->core.family == tbl->id) {
 126                                 cpu->release = tbl->str;
 127                                 break;
 128                         }
 129                 }
 130
 131                 if (is_isa_arcompact())
 132                         cpu->name = "ARC700";
 133                 else if (tbl->str)
 134                         cpu->name = "HS38";
 135                 else
 136                         cpu->name = cpu->release = "Unknown";
 137
 138                 return;
 139         }
 140
 141         /*
 142          * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
 143          * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
 144          * releases only update it.
 145          */
 146         READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
 147
 148         if (uarch.prod == 4) {
 149                 cpu->name = "HS48";
 150                 cpu->extn.dual = 1;
 151
 152         } else {
 153                 cpu->name = "HS38";
 154         }
 155
 156         for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
 157                 if (uarch.maj == tbl->id) {
 158                         cpu->release = tbl->str;
 159                         break;
 160                 }
 161         }
 162 }
 163
 164 static void read_arc_build_cfg_regs(void)
 165 {
 166         struct bcr_timer timer;
 167         struct bcr_generic bcr;
 168         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 169         struct bcr_isa_arcv2 isa;
 170         struct bcr_actionpoint ap;
 171
 172         FIX_PTR(cpu);
 173
 174         READ_BCR(AUX_IDENTITY, cpu->core);
 175         decode_arc_core(cpu);
 176
 177         READ_BCR(ARC_REG_TIMERS_BCR, timer);
 178         cpu->extn.timer0 = timer.t0;
 179         cpu->extn.timer1 = timer.t1;
 180         cpu->extn.rtc = timer.rtc;
 181
 182         cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
 183
 184         READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
 185
 186         /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
 187         read_decode_ccm_bcr(cpu);
 188
 189         read_decode_mmu_bcr();
 190         read_decode_cache_bcr();
 191
 192         if (is_isa_arcompact()) {
 193                 struct bcr_fp_arcompact sp, dp;
 194                 struct bcr_bpu_arcompact bpu;
 195
 196                 READ_BCR(ARC_REG_FP_BCR, sp);
 197                 READ_BCR(ARC_REG_DPFP_BCR, dp);
 198                 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
 199                 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
 200
 201                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 202                 cpu->bpu.ver = bpu.ver;
 203                 cpu->bpu.full = bpu.fam ? 1 : 0;
 204                 if (bpu.ent) {
 205                         cpu->bpu.num_cache = 256 << (bpu.ent - 1);
 206                         cpu->bpu.num_pred = 256 << (bpu.ent - 1);
 207                 }
 208         } else {
 209                 struct bcr_fp_arcv2 spdp;
 210                 struct bcr_bpu_arcv2 bpu;
 211
 212                 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
 213                 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
 214                 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
 215
 216                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 217                 cpu->bpu.ver = bpu.ver;
 218                 cpu->bpu.full = bpu.ft;
 219                 cpu->bpu.num_cache = 256 << bpu.bce;
 220                 cpu->bpu.num_pred = 2048 << bpu.pte;
 221                 cpu->bpu.ret_stk = 4 << bpu.rse;
 222
 223                 /* if dual issue hardware, is it enabled ? */
 224                 if (cpu->extn.dual) {
 225                         unsigned int exec_ctrl;
 226
 227                         READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
 228                         cpu->extn.dual_enb = !(exec_ctrl & 1);
 229                 }
 230         }
 231
 232         READ_BCR(ARC_REG_AP_BCR, ap);
 233         if (ap.ver) {
 234                 cpu->extn.ap_num = 2 << ap.num;
 235                 cpu->extn.ap_full = !ap.min;
 236         }
 237
 238         READ_BCR(ARC_REG_SMART_BCR, bcr);
 239         cpu->extn.smart = bcr.ver ? 1 : 0;
 240
 241         READ_BCR(ARC_REG_RTT_BCR, bcr);
 242         cpu->extn.rtt = bcr.ver ? 1 : 0;
 243
 244         READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 245
 246         /* some hacks for lack of feature BCR info in old ARC700 cores */
 247         if (is_isa_arcompact()) {
 248                 if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
 249                         cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
 250                 else {
 251                         /* ARC700_BUILD only has 2 bits of isa info */
 252                         struct bcr_generic bcr = *(struct bcr_generic *)&isa;
 253                         cpu->isa.atomic = bcr.info & 1;
 254                 }
 255
 256                 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 257
 258                  /* there's no direct way to distinguish 750 vs. 770 */
 259                 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
 260                         cpu->name = "ARC750";
 261         } else {
 262                 cpu->isa = isa;
 263         }
 264 }
 265
 266 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 267 {
 268         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 269         struct bcr_identity *core = &cpu->core;
 270         char mpy_opt[16];
 271         int n = 0;
 272
 273         FIX_PTR(cpu);
 274
 275         n += scnprintf(buf + n, len - n,
 276                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 277                        core->family, core->cpu_id, core->chip_id);
 278
 279         n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
 280                        cpu_id, cpu->name, cpu->release,
 281                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
 282                        IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
 283                        IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
 284
 285         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
 286                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
 287                        IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
 288                        IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
 289                        IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
 290
 291         if (cpu->extn_mpy.ver) {
 292                 if (is_isa_arcompact()) {
 293                         scnprintf(mpy_opt, 16, "mpy");
 294                 } else {
 295
 296                         int opt = 2;    /* stock MPY/MPYH */
 297
 298                         if (cpu->extn_mpy.dsp)  /* OPT 7-9 */
 299                                 opt = cpu->extn_mpy.dsp + 6;
 300
 301                         scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
 302                 }
 303         }
 304
 305         n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
 306                        IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 307                        IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
 308                        IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
 309                        IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
 310                        IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
 311
 312         if (cpu->bpu.ver) {
 313                 n += scnprintf(buf + n, len - n,
 314                               "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
 315                               IS_AVAIL1(cpu->bpu.full, "full"),
 316                               IS_AVAIL1(!cpu->bpu.full, "partial"),
 317                               cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
 318
 319                 if (is_isa_arcv2()) {
 320                         struct bcr_lpb lpb;
 321
 322                         READ_BCR(ARC_REG_LPB_BUILD, lpb);
 323                         if (lpb.ver) {
 324                                 unsigned int ctl;
 325                                 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
 326
 327                                 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
 328                                                lpb.entries,
 329                                                IS_DISABLED_RUN(!ctl));
 330                         }
 331                 }
 332                 n += scnprintf(buf + n, len - n, "\n");
 333         }
 334
 335         return buf;
 336 }
 337
 338 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
 339 {
 340         int n = 0;
 341         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 342
 343         FIX_PTR(cpu);
 344
 345         n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
 346
 347         if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
 348                 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
 349                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
 350                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 351
 352         if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
 353                 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
 354                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
 355                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
 356                 if (cpu->extn.ap_num) {
 357                         n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
 358                                        cpu->extn.ap_num,
 359                                        cpu->extn.ap_full ? "full":"min");
 360                 }
 361                 n += scnprintf(buf + n, len - n, "\n");
 362         }
 363
 364         if (cpu->dccm.sz || cpu->iccm.sz)
 365                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
 366                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
 367                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 368
 369         if (is_isa_arcv2()) {
 370
 371                 /* Error Protection: ECC/Parity */
 372                 struct bcr_erp erp;
 373                 READ_BCR(ARC_REG_ERP_BUILD, erp);
 374
 375                 if (erp.ver) {
 376                         struct  ctl_erp ctl;
 377                         READ_BCR(ARC_REG_ERP_CTRL, ctl);
 378
 379                         /* inverted bits: 0 means enabled */
 380                         n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
 381                                 IS_AVAIL3(erp.ic,  !ctl.dpi, "IC "),
 382                                 IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
 383                                 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
 384                 }
 385         }
 386
 387         return buf;
 388 }
 389
 390 void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena)
 391 {
 392         if (hw_exists && !opt_ena)
 393                 pr_warn(" ! Enable %s for working apps\n", opt_name);
 394         else if (!hw_exists && opt_ena)
 395                 panic("Disable %s, hardware NOT present\n", opt_name);
 396 }
 397
 398 void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena)
 399 {
 400         if (!hw_exists && opt_ena)
 401                 panic("Disable %s, hardware NOT present\n", opt_name);
 402 }
 403
 404 static void arc_chk_core_config(void)
 405 {
 406         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 407         int present = 0;
 408
 409         if (!cpu->extn.timer0)
 410                 panic("Timer0 is not present!\n");
 411
 412         if (!cpu->extn.timer1)
 413                 panic("Timer1 is not present!\n");
 414
 415 #ifdef CONFIG_ARC_HAS_DCCM
 416         /*
 417          * DCCM can be arbit placed in hardware.
 418          * Make sure it's placement/sz matches what Linux is built with
 419          */
 420         if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
 421                 panic("Linux built with incorrect DCCM Base address\n");
 422
 423         if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
 424                 panic("Linux built with incorrect DCCM Size\n");
 425 #endif
 426
 427 #ifdef CONFIG_ARC_HAS_ICCM
 428         if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
 429                 panic("Linux built with incorrect ICCM Size\n");
 430 #endif
 431
 432         /*
 433          * FP hardware/software config sanity
 434          * -If hardware present, kernel needs to save/restore FPU state
 435          * -If not, it will crash trying to save/restore the non-existant regs
 436          */
 437
 438         if (is_isa_arcompact()) {
 439                 /* only DPDP checked since SP has no arch visible regs */
 440                 present = cpu->extn.fpu_dp;
 441                 CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present);
 442         } else {
 443                 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
 444                 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
 445                 CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present);
 446
 447                 dsp_config_check();
 448         }
 449 }
 450
 451 /*
 452  * Initialize and setup the processor core
 453  * This is called by all the CPUs thus should not do special case stuff
 454  *    such as only for boot CPU etc
 455  */
 456
 457 void setup_processor(void)
 458 {
 459         char str[512];
 460         int cpu_id = smp_processor_id();
 461
 462         read_arc_build_cfg_regs();
 463         arc_init_IRQ();
 464
 465         pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 466
 467         arc_mmu_init();
 468         arc_cache_init();
 469
 470         pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
 471         pr_info("%s", arc_platform_smp_cpuinfo());
 472
 473         arc_chk_core_config();
 474 }
 475
 476 static inline bool uboot_arg_invalid(unsigned long addr)
 477 {
 478         /*
 479          * Check that it is a untranslated address (although MMU is not enabled
 480          * yet, it being a high address ensures this is not by fluke)
 481          */
 482         if (addr < PAGE_OFFSET)
 483                 return true;
 484
 485         /* Check that address doesn't clobber resident kernel image */
 486         return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
 487 }
 488
 489 #define IGNORE_ARGS             "Ignore U-boot args: "
 490
 491 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
 492 #define UBOOT_TAG_NONE          0
 493 #define UBOOT_TAG_CMDLINE       1
 494 #define UBOOT_TAG_DTB           2
 495 /* We always pass 0 as magic from U-boot */
 496 #define UBOOT_MAGIC_VALUE       0
 497
 498 void __init handle_uboot_args(void)
 499 {
 500         bool use_embedded_dtb = true;
 501         bool append_cmdline = false;
 502
 503         /* check that we know this tag */
 504         if (uboot_tag != UBOOT_TAG_NONE &&
 505             uboot_tag != UBOOT_TAG_CMDLINE &&
 506             uboot_tag != UBOOT_TAG_DTB) {
 507                 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
 508                 goto ignore_uboot_args;
 509         }
 510
 511         if (uboot_magic != UBOOT_MAGIC_VALUE) {
 512                 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
 513                 goto ignore_uboot_args;
 514         }
 515
 516         if (uboot_tag != UBOOT_TAG_NONE &&
 517             uboot_arg_invalid((unsigned long)uboot_arg)) {
 518                 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
 519                 goto ignore_uboot_args;
 520         }
 521
 522         /* see if U-boot passed an external Device Tree blob */
 523         if (uboot_tag == UBOOT_TAG_DTB) {
 524                 machine_desc = setup_machine_fdt((void *)uboot_arg);
 525
 526                 /* external Device Tree blob is invalid - use embedded one */
 527                 use_embedded_dtb = !machine_desc;
 528         }
 529
 530         if (uboot_tag == UBOOT_TAG_CMDLINE)
 531                 append_cmdline = true;
 532
 533 ignore_uboot_args:
 534
 535         if (use_embedded_dtb) {
 536                 machine_desc = setup_machine_fdt(__dtb_start);
 537                 if (!machine_desc)
 538                         panic("Embedded DT invalid\n");
 539         }
 540
 541         /*
 542          * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
 543          * append processing can only happen after.
 544          */
 545         if (append_cmdline) {
 546                 /* Ensure a whitespace between the 2 cmdlines */
 547                 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
 548                 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
 549         }
 550 }
 551
 552 void __init setup_arch(char **cmdline_p)
 553 {
 554         handle_uboot_args();
 555
 556         /* Save unparsed command line copy for /proc/cmdline */
 557         *cmdline_p = boot_command_line;
 558
 559         /* To force early parsing of things like mem=xxx */
 560         parse_early_param();
 561
 562         /* Platform/board specific: e.g. early console registration */
 563         if (machine_desc->init_early)
 564                 machine_desc->init_early();
 565
 566         smp_init_cpus();
 567
 568         setup_processor();
 569         setup_arch_memory();
 570
 571         /* copy flat DT out of .init and then unflatten it */
 572         unflatten_and_copy_device_tree();
 573
 574         /* Can be issue if someone passes cmd line arg "ro"
 575          * But that is unlikely so keeping it as it is
 576          */
 577         root_mountflags &= ~MS_RDONLY;
 578
 579         arc_unwind_init();
 580 }
 581
 582 /*
 583  * Called from start_kernel() - boot CPU only
 584  */
 585 void __init time_init(void)
 586 {
 587         of_clk_init(NULL);
 588         timer_probe();
 589 }
 590
 591 static int __init customize_machine(void)
 592 {
 593         if (machine_desc->init_machine)
 594                 machine_desc->init_machine();
 595
 596         return 0;
 597 }
 598 arch_initcall(customize_machine);
 599
 600 static int __init init_late_machine(void)
 601 {
 602         if (machine_desc->init_late)
 603                 machine_desc->init_late();
 604
 605         return 0;
 606 }
 607 late_initcall(init_late_machine);
 608 /*
 609  *  Get CPU information for use by the procfs.
 610  */
 611
 612 #define cpu_to_ptr(c)   ((void *)(0xFFFF0000 | (unsigned int)(c)))
 613 #define ptr_to_cpu(p)   (~0xFFFF0000UL & (unsigned int)(p))
 614
 615 static int show_cpuinfo(struct seq_file *m, void *v)
 616 {
 617         char *str;
 618         int cpu_id = ptr_to_cpu(v);
 619         struct device *cpu_dev = get_cpu_device(cpu_id);
 620         struct clk *cpu_clk;
 621         unsigned long freq = 0;
 622
 623         if (!cpu_online(cpu_id)) {
 624                 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
 625                 goto done;
 626         }
 627
 628         str = (char *)__get_free_page(GFP_KERNEL);
 629         if (!str)
 630                 goto done;
 631
 632         seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 633
 634         cpu_clk = clk_get(cpu_dev, NULL);
 635         if (IS_ERR(cpu_clk)) {
 636                 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
 637                            cpu_id);
 638         } else {
 639                 freq = clk_get_rate(cpu_clk);
 640         }
 641         if (freq)
 642                 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
 643                            freq / 1000000, (freq / 10000) % 100);
 644
 645         seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
 646                    loops_per_jiffy / (500000 / HZ),
 647                    (loops_per_jiffy / (5000 / HZ)) % 100);
 648
 649         seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 650         seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
 651         seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
 652         seq_printf(m, arc_platform_smp_cpuinfo());
 653
 654         free_page((unsigned long)str);
 655 done:
 656         seq_printf(m, "\n");
 657
 658         return 0;
 659 }
 660
 661 static void *c_start(struct seq_file *m, loff_t *pos)
 662 {
 663         /*
 664          * Callback returns cpu-id to iterator for show routine, NULL to stop.
 665          * However since NULL is also a valid cpu-id (0), we use a round-about
 666          * way to pass it w/o having to kmalloc/free a 2 byte string.
 667          * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
 668          */
 669         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 670 }
 671
 672 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 673 {
 674         ++*pos;
 675         return c_start(m, pos);
 676 }
 677
 678 static void c_stop(struct seq_file *m, void *v)
 679 {
 680 }
 681
 682 const struct seq_operations cpuinfo_op = {
 683         .start  = c_start,
 684         .next   = c_next,
 685         .stop   = c_stop,
 686         .show   = show_cpuinfo
 687 };
 688
 689 static DEFINE_PER_CPU(struct cpu, cpu_topology);
 690
 691 static int __init topology_init(void)
 692 {
 693         int cpu;
 694
 695         for_each_present_cpu(cpu)
 696             register_cpu(&per_cpu(cpu_topology, cpu), cpu);
 697
 698         return 0;
 699 }
 700
 701 subsys_initcall(topology_init);