1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
5 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
8 #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
9 #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
10 #include <asm/errno.h>
11 #include <asm/arcregs.h>
12 #include <asm/irqflags.h>
14 ; A maximum number of supported interrupts in the core interrupt controller.
15 ; This number is not equal to the maximum interrupt number (256) because
16 ; first 16 lines are reserved for exceptions and are not configurable.
17 #define NR_CPU_IRQS 240
23 ;############################ Vector Table #################################
25 .section .vector,"a",@progbits
28 # Initial 16 slots are Exception Vectors
29 VECTOR res_service ; Reset Vector
30 VECTOR mem_service ; Mem exception
31 VECTOR instr_service ; Instrn Error
32 VECTOR EV_MachineCheck ; Fatal Machine check
33 VECTOR EV_TLBMissI ; Intruction TLB miss
34 VECTOR EV_TLBMissD ; Data TLB miss
35 VECTOR EV_TLBProtV ; Protection Violation
36 VECTOR EV_PrivilegeV ; Privilege Violation
37 VECTOR EV_SWI ; Software Breakpoint
38 VECTOR EV_Trap ; Trap exception
39 VECTOR EV_Extension ; Extn Instruction Exception
40 VECTOR EV_DivZero ; Divide by Zero
41 VECTOR EV_DCError ; Data Cache Error
42 VECTOR EV_Misaligned ; Misaligned Data Access
43 VECTOR reserved ; Reserved slots
44 VECTOR reserved ; Reserved slots
46 # Begin Interrupt Vectors
47 VECTOR handle_interrupt ; (16) Timer0
48 VECTOR handle_interrupt ; unused (Timer1)
49 VECTOR handle_interrupt ; unused (WDT)
50 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
51 VECTOR handle_interrupt ; (20) perf Interrupt
52 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
53 VECTOR handle_interrupt ; unused
54 VECTOR handle_interrupt ; (23) unused
58 VECTOR handle_interrupt
61 .section .text, "ax",@progbits
64 flag 1 ; Unexpected event, halt
66 ;##################### Interrupt Handling ##############################
68 ENTRY(handle_interrupt)
70 INTERRUPT_PROLOGUE irq
72 # irq control APIs local_irq_save/restore/disable/enable fiddle with
73 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
74 # However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
75 # query in hard ISR path would return false (since .IE is set) which would
76 # trips genirq interrupt handling asserts.
78 # So do a "soft" disable of interrutps here.
80 # Note this disable is only for consistent book-keeping as further interrupts
81 # will be disabled anyways even w/o this. Hardware tracks active interrupts
82 # seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts
83 # unless this one returns (or higher prio becomes pending in 2-prio scheme)
87 ; icause is banked: one per priority level
88 ; so a higher prio interrupt taken here won't clobber prev prio icause
90 mov blink, ret_from_exception
97 ;################### Non TLB Exception Handling #############################
100 ; TODO: implement this
106 ; TODO: implement this
112 ; TODO: implement this
117 ; ---------------------------------------------
118 ; Memory Error Exception Handler
119 ; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
120 ; Instruction fetch or Data access, under a single Exception Vector
121 ; ---------------------------------------------
140 lr r0, [efa] ; Faulting Data address
145 SAVE_CALLEE_SAVED_USER
146 mov r2, sp ; callee_regs
148 bl do_misaligned_access
150 ; TBD: optimize - do this only if a callee reg was involved
151 ; either a dst of emulated LD/ST or src with address-writeback
152 RESTORE_CALLEE_SAVED_USER
157 ; ---------------------------------------------
158 ; Protection Violation Exception Handler
159 ; ---------------------------------------------
165 lr r0, [efa] ; Faulting Data address
170 mov blink, ret_from_exception
175 ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
176 ; need to call do_page_fault().
177 ; ECR in pt_regs provides whether access was R/W/X
179 .global call_do_page_fault
180 .set call_do_page_fault, EV_TLBProtV
182 ;############# Common Handlers for ARCompact and ARCv2 ##############
186 ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
188 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
189 ; IRQ shd definitely not happen between now and rtie
190 ; All 2 entry points to here already disable interrupts
195 # Interrpts are actually disabled from this point on, but will get
196 # reenabled after we return from interrupt/exception.
197 # But irq tracer needs to be told now...
200 ld r0, [sp, PT_status32] ; U/K mode at time of entry
201 lr r10, [AUX_IRQ_ACT]
203 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE
204 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
206 ;####### Return from Intr #######
209 ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
210 btst r0, STATUS_DE_BIT ; Z flag set if bit clear
211 bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
214 ; Handle special case #1: (Entry via Exception, Return via IRQ)
216 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
217 ; task now returning to U mode (riding the Intr)
218 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
219 ; won't be switched to correct U mode value (from AUX_SP)
220 ; So force AUX_IRQ_ACT.U for such a case
222 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
223 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
224 sr r11, [AUX_IRQ_ACT]
226 INTERRUPT_EPILOGUE irq
229 ;####### Return from Exception / pure kernel mode #######
231 .Lexcept_ret: ; Expects r0 has PT_status32
233 debug_marker_syscall:
237 ;####### Return from Intr to insn in delay slot #######
239 ; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
241 ; Intr returning to a Delay Slot (DS) insn
242 ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
243 ; entry was via Exception in DS which got preempted in kernel).
245 ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
247 ; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
248 ; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
250 .Lintr_ret_to_delay_slot:
253 ld r2, [@intr_to_DE_cnt]
255 st r2, [@intr_to_DE_cnt]
258 ld r3, [sp, PT_status32]
260 ; STAT32 for Int return created from scratch
261 ; (No delay dlot, disable Further intr in trampoline)
263 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
264 st r0, [sp, PT_status32]
266 mov r1, .Lintr_ret_to_delay_slot_2
269 ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
273 b .Lisr_ret_fast_path
275 .Lintr_ret_to_delay_slot_2:
276 ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
277 sub sp, sp, SZ_PT_REGS
286 ; restore AUX_USER_SP if returning to U mode
287 bbit0 r9, STATUS_U_BIT, 1f
296 add sp, sp, SZ_PT_REGS
298 ; return from pure kernel mode to delay slot
301 END(ret_from_exception)