1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 #ifndef __ASM_IRQFLAGS_ARCOMPACT_H
8 #define __ASM_IRQFLAGS_ARCOMPACT_H
10 /* vineetg: March 2010 : local_irq_save( ) optimisation
11 * -Remove explicit mov of current status32 into reg, that is not needed
12 * -Use BIC insn instead of INVERTED + AND
13 * -Conditionally disable interrupts (if they are not enabled, don't disable)
16 #include <asm/arcregs.h>
18 /* status32 Reg bits related to Interrupt Handling */
19 #define STATUS_E1_BIT 1 /* Int 1 enable */
20 #define STATUS_E2_BIT 2 /* Int 2 enable */
21 #define STATUS_A1_BIT 3 /* Int 1 active */
22 #define STATUS_A2_BIT 4 /* Int 2 active */
23 #define STATUS_AE_BIT 5 /* Exception active */
25 #define STATUS_E1_MASK (1<<STATUS_E1_BIT)
26 #define STATUS_E2_MASK (1<<STATUS_E2_BIT)
27 #define STATUS_A1_MASK (1<<STATUS_A1_BIT)
28 #define STATUS_A2_MASK (1<<STATUS_A2_BIT)
29 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
30 #define STATUS_IE_MASK (STATUS_E1_MASK | STATUS_E2_MASK)
32 /* Other Interrupt Handling related Aux regs */
33 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
34 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
35 #define AUX_IRQ_LV12 0x43 /* interrupt level register */
37 #define AUX_IENABLE 0x40c
38 #define AUX_ITRIGGER 0x40d
39 #define AUX_IPULSE 0x415
41 #define ISA_INIT_STATUS_BITS STATUS_IE_MASK
45 /******************************************************************
48 * All of them have "memory" clobber (compiler barrier) which is needed to
49 * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
50 * are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
52 * Noted at the time of Abilis Timer List corruption
53 * Orig Bug + Rejected solution : https://lkml.org/lkml/2013/3/29/67
54 * Reasoning : https://lkml.org/lkml/2013/4/8/15
56 ******************************************************************/
59 * Save IRQ state and disable IRQs
61 static inline long arch_local_irq_save(void)
63 unsigned long temp, flags;
66 " lr %1, [status32] \n"
70 : "=r"(temp), "=r"(flags)
71 : "n"((STATUS_E1_MASK | STATUS_E2_MASK))
78 * restore saved IRQ state
80 static inline void arch_local_irq_restore(unsigned long flags)
91 * Unconditionally Enable IRQs
93 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
94 extern void arch_local_irq_enable(void);
96 static inline void arch_local_irq_enable(void)
100 __asm__ __volatile__(
101 " lr %0, [status32] \n"
105 : "n"((STATUS_E1_MASK | STATUS_E2_MASK))
111 * Unconditionally Disable IRQs
113 static inline void arch_local_irq_disable(void)
117 __asm__ __volatile__(
118 " lr %0, [status32] \n"
122 : "n"(~(STATUS_E1_MASK | STATUS_E2_MASK))
129 static inline long arch_local_save_flags(void)
133 __asm__ __volatile__(
134 " lr %0, [status32] \n"
145 static inline int arch_irqs_disabled_flags(unsigned long flags)
147 return !(flags & (STATUS_E1_MASK
148 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
154 static inline int arch_irqs_disabled(void)
156 return arch_irqs_disabled_flags(arch_local_save_flags());
161 #ifdef CONFIG_TRACE_IRQFLAGS
163 .macro TRACE_ASM_IRQ_DISABLE
164 bl trace_hardirqs_off
167 .macro TRACE_ASM_IRQ_ENABLE
173 .macro TRACE_ASM_IRQ_DISABLE
176 .macro TRACE_ASM_IRQ_ENABLE
181 .macro IRQ_DISABLE scratch
182 lr \scratch, [status32]
183 bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
185 TRACE_ASM_IRQ_DISABLE
188 .macro IRQ_ENABLE scratch
190 lr \scratch, [status32]
191 or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
195 #endif /* __ASSEMBLY__ */